[all-commits] [llvm/llvm-project] bd1983: [TableGen] V is always a TypedInit, so use cast (#...
Aiden Grossman via All-commits
all-commits at lists.llvm.org
Wed Jul 15 06:35:47 PDT 2026
Branch: refs/heads/users/boomanaiden154/main.lit-delete-the-external-shell
Home: https://github.com/llvm/llvm-project
Commit: bd1983e7ec9fef429787997684b48644dee583c4
https://github.com/llvm/llvm-project/commit/bd1983e7ec9fef429787997684b48644dee583c4
Author: AZero13 <gfunni234 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/TableGen/TGParser.cpp
Log Message:
-----------
[TableGen] V is always a TypedInit, so use cast (#209208)
No need to dyn_cast. It is functionally impossible for V to not be a
TypedInit at this point.
Commit: 848d409e60845352cfce85c2a23d1d262a0c68f3
https://github.com/llvm/llvm-project/commit/848d409e60845352cfce85c2a23d1d262a0c68f3
Author: Sairudra More <sairudra60 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
A flang/test/Integration/OpenMP/target-inreduction-llvmir.f90
A flang/test/Lower/OpenMP/Todo/target-inreduction-common.f90
A flang/test/Lower/OpenMP/Todo/target-inreduction-equivalence.f90
A flang/test/Lower/OpenMP/Todo/target-inreduction-firstprivate.f90
R flang/test/Lower/OpenMP/Todo/target-inreduction.f90
A flang/test/Lower/OpenMP/target-inreduction-unused.f90
A flang/test/Lower/OpenMP/target-inreduction.f90
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Dialect/OpenMP/host-op-filtering.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
A mlir/test/Target/LLVMIR/openmp-target-in-reduction-device.mlir
A mlir/test/Target/LLVMIR/openmp-target-in-reduction-multi.mlir
A mlir/test/Target/LLVMIR/openmp-target-in-reduction.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[flang][OpenMP] Lower target in_reduction (#199967)
This patch carries `in_reduction` through `omp.target` for host
execution.
The lowering looks up the task-reduction private storage with
`__kmpc_task_reduction_get_th_data` and binds the target region argument
to that private pointer. This makes uses inside the target region refer
to the task-private reduction storage instead of continuing to use the
original variable.
This also fixes the `omp::TargetOp::build(TargetOperands)` path so
`in_reduction` operands are preserved instead of being dropped.
On the Flang side, `target in_reduction` list items are added to the
target map entries when needed, giving the translation a matching mapped
value to rewrite.
### Stack / review order
This PR is related to the OpenMP task-reduction translation stack:
1. #199565 — `omp.taskgroup task_reduction` translation
2. #199670 — `omp.taskloop` `reduction` / `in_reduction` translation
3. #202611 — explicit `omp.task in_reduction` translation
This PR is a target-specific sibling follow-up:
* #199967 — `omp.target in_reduction` host lowering
The intended main review order for the task/taskloop stack is:
#199565 → #199670 → #202611
This PR should be reviewed as the `omp.target in_reduction` host-side
lowering work built on the same task-reduction runtime model, not as a
dependency of #202611.
Addresses #199904.
Assisted-by: Claude Opus 4.8 and ChatGPT 5.5
Commit: f859de88413c729166b08c00af5fcfe4f4b15b2d
https://github.com/llvm/llvm-project/commit/f859de88413c729166b08c00af5fcfe4f4b15b2d
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/lit.cfg.py
Log Message:
-----------
[LLVM] Use kwargs for ShTest constructor (#209676)
Since extra_substitutions is not the first argument (although it will be
soon).
Fixes https://lab.llvm.org/buildbot/#/builders/223/builds/7170.
This was broken by 3f46a5e91cdf2ade1d8ca350f4a57af8221407ea.
Commit: f8d8dc1f864fa887f949418a2ebb58e1a0d239b8
https://github.com/llvm/llvm-project/commit/f8d8dc1f864fa887f949418a2ebb58e1a0d239b8
Author: Wenju He <wenju.he at intel.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Support/raw_ostream.cpp
M llvm/unittests/Support/raw_ostream_test.cpp
Log Message:
-----------
[Support] Treat Windows "NUL" as the null device in writeToOutput (#208179)
llvm-objcopy (via writeToOutput) only special-cased "/dev/null", so on
Windows an output path of "NUL" fell through to TempFile::create() +
rename. Windows reserves "NUL" as a device name, so the rename fails
with "permission denied". This broke clang-offload-bundler's SYCL fat
object step when the driver is invoked with `-o nul` in downstream test
https://github.com/intel/llvm/blob/sycl/sycl/test/include_deps/header_reach.cpp
Assisted by: Claude
Commit: 11ebc0e6645c8c53c75bca93e9fddf0053507cc1
https://github.com/llvm/llvm-project/commit/11ebc0e6645c8c53c75bca93e9fddf0053507cc1
Author: Keshav Vinayak Jha <31160700+keshavvinayak01 at users.noreply.github.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
A llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-merge-values-build-vector-s16.mir
Log Message:
-----------
[AMDGPU][GlobalISel] Select s16 G_MERGE_VALUES into wider scalars (#207999)
With real-true16 (default on `gfx11`/`gfx12`), a scalar `s16` is a
register type, so the `G_MERGE_VALUES` legality rule started accepting
scalar merges built from `s16` pieces, e.g. `s64 = G_MERGE_VALUES(4 x
s16)`. The instruction selector has no pattern for that shape. So this
aborts with `cannot select` on something like:
```mlir
define amdgpu_kernel void @k(ptr %p) {
store i136 0, ptr %p, align 8
ret void
}
```
Make it selectable rather than restricting legalization: Pack pairs of
`s16` with `S_PACK_LL_B32_B16` then `REG_SEQUENCE`.
Assisted-by: Claude
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Commit: 454a66a65c66012004b2e1e711247f5ebf729957
https://github.com/llvm/llvm-project/commit/454a66a65c66012004b2e1e711247f5ebf729957
Author: Vikram Hegde <Vikram.Hegde at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
Log Message:
-----------
[CodeGen][NPM] Disable Machine verifier at the end of default pipelines (#208357)
keeping discussions in https://github.com/llvm/llvm-project/pull/176693.
Adds target option to disable machine verifier at the end of default
pilelines (O0,O1..). Also ref.
https://github.com/llvm/llvm-project/pull/201004 for discussions
regarding why this is required (temporarily atleast) so that NPM
migration is unblocked. should be removed once we have fixed all the
latent verifier issues.
Commit: 424421a80936e1d3cb824eecce51344acbc80253
https://github.com/llvm/llvm-project/commit/424421a80936e1d3cb824eecce51344acbc80253
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M orc-rt/include/CMakeLists.txt
M orc-rt/lib/executor/CMakeLists.txt
Log Message:
-----------
[orc-rt] Sort header and source lists in CMakeLists. NFC. (#209685)
Commit: 74822b4ee01f168f2d9a808594abb0c8936f5bbf
https://github.com/llvm/llvm-project/commit/74822b4ee01f168f2d9a808594abb0c8936f5bbf
Author: Weibo He <NewSigma at 163.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaType.cpp
M clang/test/SemaCXX/cxx2b-deducing-this.cpp
Log Message:
-----------
[clang][Sema] Fix rejected-valid for explicit object parameters in dependent nested classes context (#209107)
In #89078, we banned explicit object parameters from several invalid
contexts. This patch proposes we relax the restriction and allow
entering contexts so that nested classes can be visited correctly.
Close #136472
Commit: c4830afdbbc7b16a52a05d6a5b56e6c3fc14fb98
https://github.com/llvm/llvm-project/commit/c4830afdbbc7b16a52a05d6a5b56e6c3fc14fb98
Author: David Zbarsky <dzbarsky at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang-tools-extra/clangd/ConfigYAML.cpp
Log Message:
-----------
[clangd] Use unique_function for config handlers (#203008)
`ConfigYAML.cpp`'s `DictParser` owns its callbacks for one parse and
never copies them, so this replaces `std::function` with move-only
`llvm::unique_function` and removes the unused copy machinery for each
lambda.
In a matched Release AArch64 build, `ConfigYAML.cpp.o` shrank by 94,560
bytes, stripped clangd shrank by 16,848 bytes, unstripped clangd shrank
by 82,512 bytes, and dyld fixups fell by 336.
Validated with the 16 `ParseYAML` unit tests and `clangd --check`; 12
paired runs of 100,000 parses improved mean user CPU time by 3.46% (95%
CI: 1.31% to 5.61%).
Work towards #202616
AI tool disclosure: Co-authored with OpenAI Codex.
Commit: b570a7754d9b84af8ceffd8834194d559077cda5
https://github.com/llvm/llvm-project/commit/b570a7754d9b84af8ceffd8834194d559077cda5
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/socket/BUILD.bazel
Log Message:
-----------
[libc][bazel] Add recently added sys/socket functions and syscall wrappers (#209457)
This patch adds the missing functions to BUILD.bazel:
- recvmmsg
- sendmmsg
- setsockopt
- shutdown
I also add the corresponding syscall wrapper libraries that these
functions depend on, along with a couple of additional type libraries.
I'm leaving the remaining sys/socket functions and test suites out for
now since some of them require additional infrastructure or type
definitions.
Assisted by Gemini.
Commit: 36c6568b04aff4e1cf00a60570ab4a4344692920
https://github.com/llvm/llvm-project/commit/36c6568b04aff4e1cf00a60570ab4a4344692920
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libc/src/__support/StringUtil/CMakeLists.txt
M libc/src/__support/StringUtil/signal_to_string.cpp
M libc/src/__support/StringUtil/tables/CMakeLists.txt
M libc/src/__support/StringUtil/tables/linux_extension_signals.h
M libc/src/__support/StringUtil/tables/posix_signals.h
M libc/src/__support/StringUtil/tables/stdc_signals.h
M libc/src/signal/kill.h
M libc/src/signal/linux/CMakeLists.txt
M libc/src/signal/linux/kill.cpp
M libc/src/signal/linux/sigemptyset.cpp
M libc/src/signal/raise.h
M libc/src/spawn/linux/CMakeLists.txt
M libc/src/spawn/linux/posix_spawn.cpp
M libc/src/sys/wait/linux/CMakeLists.txt
M libc/src/sys/wait/wait4Impl.h
M libc/src/unistd/linux/CMakeLists.txt
M libc/src/unistd/linux/fork.cpp
M libc/test/src/fenv/enabled_exceptions_test.cpp
M libc/test/src/signal/kill_test.cpp
M libc/test/src/signal/pthread_sigmask_test.cpp
M libc/test/src/signal/raise_test.cpp
M libc/test/src/signal/sigaddset_test.cpp
M libc/test/src/signal/sigdelset_test.cpp
M libc/test/src/signal/sigfillset_test.cpp
M libc/test/src/signal/signal_test.cpp
M libc/test/src/signal/sigprocmask_test.cpp
M libc/test/src/stdlib/abort_test.cpp
M libc/test/src/string/strsignal_test.cpp
M libc/test/src/sys/mman/linux/mprotect_test.cpp
Log Message:
-----------
[libc] Remove #include <signal.h> (#209433)
Replace it with granular includes of the appropriate type/macro proxy
headers.
Assisted by Gemini.
Commit: 7881a375884c3793d2fa7c31ab97781a43547f31
https://github.com/llvm/llvm-project/commit/7881a375884c3793d2fa7c31ab97781a43547f31
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/PackAndUnpackPatterns.cpp
M mlir/test/Dialect/Linalg/simplify-pack-unpack.mlir
Log Message:
-----------
[mlir][linalg] Refine pack/unpack simplification checks (NFC) (#209522)
Update `isPackOn1D`, which is used by both
`SimplifyPackToExpandShape` and `SimplifyUnPackToCollapseShape`:
* Rename it to `isPackOnEffectively1D` to better reflect its
functionality: the underlying pack can be multi-dimensional.
* Add checks to ensure that the unique non-unit inner tile is used to
tile the unique non-unit unpacked dimension (that was previously
left as an unchecked assumption).
* Add comments to the test file for these patterns, grouping the tests
according to the functionality/cases being tested.
Commit: 89fa7352a2cfd5ec498ba442de77d257475954f2
https://github.com/llvm/llvm-project/commit/89fa7352a2cfd5ec498ba442de77d257475954f2
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/arpa/inet.yaml
M libc/src/arpa/inet/CMakeLists.txt
A libc/src/arpa/inet/inet_ntoa.cpp
A libc/src/arpa/inet/inet_ntoa.h
M libc/test/src/arpa/inet/CMakeLists.txt
A libc/test/src/arpa/inet/inet_ntoa_test.cpp
Log Message:
-----------
[libc] Implement inet_ntoa (#208702)
Implement inet_ntoa, reusing the internal net::ipv4_to_str helper that
backs inet_ntop.
The result is stored in a *thread-local* static buffer. A thread-local
buffer is not required for POSIX conformance, but there is some
precedent for that, both in llvm libc (e.g. `strsignal`) and in glibc
(whose `inet_ntoa` uses it). I'm doing the same for maximum
compatiblity.
Assisted by Gemini.
Commit: 69e0994c93bc56f96e5f0ef83fdd0121a829c9d0
https://github.com/llvm/llvm-project/commit/69e0994c93bc56f96e5f0ef83fdd0121a829c9d0
Author: Wendi <uwendi at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/docs/QualGroup.rst
Log Message:
-----------
[Docs] Document Qualification WG artifacts and meeting archive (#209382)
# Summary
Update the LLVM Qualification Working Group page to point readers to the
group's directory in the `llvm-wgs` repository.
The new **Working Group artifacts** section explains that the directory
is the central location for the group's public technical outputs and
working materials, including qualification guidance, templates,
analyses, and proposals.
The **Meeting Materials** section is also updated to reflect the
migration of meeting materials, agendas, and minutes to the `llvm-wgs`
repository. The repository is presented as the long-term archive, while
the existing Discourse thread remains the location where upcoming
agendas and newly published minutes are shared.
# Changes
- Add a link to the Qualification Working Group's `fusa-qual-wg`
directory.
- Explain the purpose and maturity of the artifacts stored there.
- Link directly to the meeting materials and meeting minutes
directories.
- Add a link to the repository-based meeting archive.
- Retain the Discourse thread as the communication channel for agendas
and minutes.
# Related repository
https://github.com/llvm/llvm-wgs/tree/main/fusa-qual-wg
Commit: bff9c544bd87087d1e13a7b1c6298aa9e21a313c
https://github.com/llvm/llvm-project/commit/bff9c544bd87087d1e13a7b1c6298aa9e21a313c
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/test/MC/RISCV/corev/XCValu-invalid.s
M llvm/test/MC/RISCV/corev/XCVbi-invalid.s
M llvm/test/MC/RISCV/corev/XCVbitmanip-invalid.s
M llvm/test/MC/RISCV/corev/XCVelw-invalid.s
M llvm/test/MC/RISCV/corev/XCVmac-invalid.s
M llvm/test/MC/RISCV/corev/XCVmem-invalid.s
M llvm/test/MC/RISCV/corev/XCVsimd-invalid.s
M llvm/test/MC/RISCV/function-call-invalid.s
M llvm/test/MC/RISCV/priv-invalid.s
M llvm/test/MC/RISCV/rv32d-invalid.s
M llvm/test/MC/RISCV/rv32f-invalid.s
M llvm/test/MC/RISCV/rv32i-aliases-invalid.s
M llvm/test/MC/RISCV/rv32i-invalid.s
M llvm/test/MC/RISCV/rv32q-invalid.s
M llvm/test/MC/RISCV/rv32xqccmp-invalid.s
M llvm/test/MC/RISCV/rv32zcmp-invalid.s
M llvm/test/MC/RISCV/rv32zdinx-invalid.s
M llvm/test/MC/RISCV/rv32zfh-invalid.s
M llvm/test/MC/RISCV/rv32zhinx-invalid.s
M llvm/test/MC/RISCV/rv64d-invalid.s
M llvm/test/MC/RISCV/rv64f-invalid.s
M llvm/test/MC/RISCV/rv64i-aliases-invalid.s
M llvm/test/MC/RISCV/rv64q-invalid.s
M llvm/test/MC/RISCV/rv64xqccmp-invalid.s
M llvm/test/MC/RISCV/rv64xtheadfmemidx-invalid.s
M llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s
M llvm/test/MC/RISCV/rv64zcmp-invalid.s
M llvm/test/MC/RISCV/rv64zdinx-invalid.s
M llvm/test/MC/RISCV/rv64zfh-invalid.s
M llvm/test/MC/RISCV/rv64zfinx-invalid.s
M llvm/test/MC/RISCV/rv64zhinx-invalid.s
M llvm/test/MC/RISCV/rve-invalid.s
M llvm/test/MC/RISCV/rvzfbfmin-invalid.s
M llvm/test/MC/RISCV/rvzfhmin-invalid.s
M llvm/test/MC/RISCV/rvzicond-invalid.s
M llvm/test/MC/RISCV/tlsdesc.s
M llvm/test/MC/RISCV/xmips-invalid.s
M llvm/test/MC/RISCV/xqcibm-invalid.s
M llvm/test/MC/RISCV/xqcili-invalid.s
M llvm/test/MC/RISCV/xqcilo-invalid.s
M llvm/test/MC/RISCV/xqcisim-invalid.s
M llvm/test/MC/RISCV/xqcisls-invalid.s
M llvm/test/MC/RISCV/xtheadcondmov-invalid.s
M llvm/test/MC/RISCV/xtheadmac-invalid.s
Log Message:
-----------
[RISCV][MC] Improve GPR Error Messages (#209669)
- For the usual GPR RegClass
- For the GPRX0 RegClass as used by the `PseudoC_ADDI_NOP` instruction.
- For the SR07 regclass used by Zcmp and Xqccmp instructions.
Commit: 2d6692d577cfee5af4d96a0759a14b55ee58b6e1
https://github.com/llvm/llvm-project/commit/2d6692d577cfee5af4d96a0759a14b55ee58b6e1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/si-scheduler.ll
M llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll
M llvm/test/CodeGen/AMDGPU/si-spill-cf.ll
M llvm/test/CodeGen/AMDGPU/si-split-load-store-alias-info.ll
M llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-return-unreachable.ll
M llvm/test/CodeGen/AMDGPU/si-vector-hang.ll
M llvm/test/CodeGen/AMDGPU/sibling-call.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/siloadstoreopt-misaligned-regsequence.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call-2.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/simplify-libcall-nobuiltin-def.ll
M llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
M llvm/test/CodeGen/AMDGPU/simplify-libcalls2.ll
M llvm/test/CodeGen/AMDGPU/simulated-trap-pseudo-expand.ll
M llvm/test/CodeGen/AMDGPU/sink-addr-memory-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir
M llvm/test/CodeGen/AMDGPU/sink-after-control-flow.mir
M llvm/test/CodeGen/AMDGPU/sink-image-sample.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/skip-fold-regsequence.mir
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/skip-promote-alloca-vector-users.ll
M llvm/test/CodeGen/AMDGPU/smed3.ll
M llvm/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir
M llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir
M llvm/test/CodeGen/AMDGPU/smfmac_alloc_failure_no_agpr_O0.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/smrd-fold-offset.mir
M llvm/test/CodeGen/AMDGPU/smrd-gfx10.ll
M llvm/test/CodeGen/AMDGPU/smrd-vccz-bug.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/smrd_vmem_war.ll
M llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir
M llvm/test/CodeGen/AMDGPU/soft-clause-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/soft-clause-exceeds-register-budget.ll
M llvm/test/CodeGen/AMDGPU/sopk-compares.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/speculative-execution-freecasts.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
M llvm/test/CodeGen/AMDGPU/spill-alloc-sgpr-init-bug.ll
M llvm/test/CodeGen/AMDGPU/spill-cfg-position.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
M llvm/test/CodeGen/AMDGPU/spill-regpressure-less.mir
M llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-sgpr-stack-no-sgpr.ll
M llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
M llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir
M llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
M llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr-update-regscavenger.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
M llvm/test/CodeGen/AMDGPU/spill-wait.mir
M llvm/test/CodeGen/AMDGPU/spill-wide-sgpr.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/spill192.mir
M llvm/test/CodeGen/AMDGPU/spill224.mir
M llvm/test/CodeGen/AMDGPU/spill288.mir
M llvm/test/CodeGen/AMDGPU/spill320.mir
M llvm/test/CodeGen/AMDGPU/spill352.mir
M llvm/test/CodeGen/AMDGPU/spill384.mir
M llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir
M llvm/test/CodeGen/AMDGPU/spillv16.ll
M llvm/test/CodeGen/AMDGPU/spillv16.mir
M llvm/test/CodeGen/AMDGPU/spillv16Kernel.ll
M llvm/test/CodeGen/AMDGPU/spillv16Kernel.mir
M llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll
M llvm/test/CodeGen/AMDGPU/split-liverange-overlapping-copies.mir
M llvm/test/CodeGen/AMDGPU/split-mbb-lis-subrange.mir
M llvm/test/CodeGen/AMDGPU/split-smrd.ll
M llvm/test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll
M llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
M llvm/test/CodeGen/AMDGPU/splitkit-do-not-undo-subclass-split-with-remat.mir
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/splitkit.mir
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/sram-ecc-default.ll
M llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-any.ll
M llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-disabled.ll
M llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-enabled.ll
M llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl-bitcast-bv.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (33) (#209562)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 162a2767d624684869d710f25096b882a32109bc
https://github.com/llvm/llvm-project/commit/162a2767d624684869d710f25096b882a32109bc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M llvm/include/llvm/Object/OffloadBinary.h
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Object/OffloadBinary.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
clang-linker-wrapper: Use AMDGPU::TargetID for image compatibilty (2) (#209563)
This reverts commit aa5960600ac38fcd923e69777bad1293f56658d7.
Before the first attempt, clang-linker-wrapper inconsistently
applied linker reasoning to the target ID feature modifiers, but
not the base processor. e.g., gfx90a was considered mergable
with gfx90a:xnack+.
The first attempt at this changed introduced and used
TargetID::isCompatibleWith, which applied full linking
compatibility logic. This broke tests which combined
generic and covered non-generic targets in the build (e.g.,
gfx9-generic and gfx900). The archives would both be treated
as compatible, resulting in multiple definition errors.
Split the TargetID compatibility checks into 2 different kinds:
1 for exact target match used for archives, and 1 for logical
compatibility usable for objects. For archive purposes, this stops
treating xnack-any as the same target with an xnack specifier which
is a behavior change. It just so happens that clang would error if you
tried to compile xnack-any and xnack+/- in the same invocation, so this
behavior was only observable when directly using the binary tools.
Co-authored-by: Claude (Opus 4.8)
Commit: b790c5cd267974456806773f01dfb8936b22e4f2
https://github.com/llvm/llvm-project/commit/b790c5cd267974456806773f01dfb8936b22e4f2
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libc/src/__support/File/linux/CMakeLists.txt
M libc/src/__support/File/linux/file.cpp
M libc/src/pthread/CMakeLists.txt
M libc/src/pthread/pthread_condattr_getclock.cpp
M libc/src/pthread/pthread_condattr_getclock.h
M libc/src/pthread/pthread_condattr_setclock.cpp
M libc/src/pthread/pthread_condattr_setclock.h
M libc/src/sys/prctl/linux/CMakeLists.txt
M libc/src/sys/prctl/prctl.h
M libc/src/sys/random/getrandom.h
M libc/src/sys/random/linux/CMakeLists.txt
M libc/src/sys/resource/getrlimit.h
M libc/src/sys/resource/linux/CMakeLists.txt
M libc/src/sys/resource/setrlimit.h
M libc/src/sys/sendfile/linux/CMakeLists.txt
M libc/src/sys/sendfile/linux/sendfile.cpp
M libc/src/sys/sendfile/sendfile.h
M libc/src/sys/socket/linux/CMakeLists.txt
M libc/src/sys/socket/recv.h
M libc/src/sys/socket/send.h
M libc/src/sys/wait/linux/CMakeLists.txt
M libc/src/sys/wait/wait.h
M libc/src/sys/wait/waitpid.h
M libc/src/unistd/linux/CMakeLists.txt
M libc/src/unistd/linux/isatty.cpp
M libc/startup/linux/CMakeLists.txt
M libc/startup/linux/do_start.cpp
M libc/test/integration/src/sys/ptrace/linux/ptrace_test.cpp
M libc/test/src/fcntl/CMakeLists.txt
M libc/test/src/fcntl/creat_test.cpp
M libc/test/src/fcntl/fcntl_test.cpp
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/fdopen_test.cpp
M libc/test/src/string/memory_utils/protected_pages.h
M libc/test/src/sys/auxv/linux/CMakeLists.txt
M libc/test/src/sys/auxv/linux/getauxval_test.cpp
M libc/test/src/sys/mman/linux/CMakeLists.txt
M libc/test/src/sys/mman/linux/mlock_test.cpp
M libc/test/src/sys/mman/linux/mprotect_test.cpp
M libc/test/src/sys/mman/linux/posix_madvise_test.cpp
M libc/test/src/sys/mman/linux/remap_file_pages_test.cpp
M libc/test/src/sys/resource/CMakeLists.txt
M libc/test/src/sys/resource/getrlimit_setrlimit_test.cpp
M libc/test/src/sys/sendfile/CMakeLists.txt
M libc/test/src/sys/sendfile/sendfile_test.cpp
M libc/test/src/sys/socket/linux/CMakeLists.txt
M libc/test/src/sys/socket/linux/sendto_recvfrom_test.cpp
M libc/test/src/sys/socket/linux/socket_test.cpp
M libc/test/src/sys/socket/linux/socketopt_test.cpp
M libc/test/src/sys/socket/linux/socketpair_test.cpp
M libc/test/src/sys/stat/CMakeLists.txt
M libc/test/src/sys/stat/chmod_test.cpp
M libc/test/src/sys/stat/fchmod_test.cpp
M libc/test/src/sys/stat/fchmodat_test.cpp
M libc/test/src/sys/stat/fstat_test.cpp
M libc/test/src/sys/stat/lstat_test.cpp
M libc/test/src/sys/stat/stat_test.cpp
M libc/test/src/unistd/CMakeLists.txt
M libc/test/src/unistd/access_test.cpp
M libc/test/src/unistd/chown_test.cpp
M libc/test/src/unistd/dup2_test.cpp
M libc/test/src/unistd/dup3_test.cpp
M libc/test/src/unistd/dup_test.cpp
M libc/test/src/unistd/faccessat_test.cpp
M libc/test/src/unistd/fchown_test.cpp
M libc/test/src/unistd/ftruncate_test.cpp
M libc/test/src/unistd/isatty_test.cpp
M libc/test/src/unistd/link_test.cpp
M libc/test/src/unistd/linkat_test.cpp
M libc/test/src/unistd/pread_pwrite_test.cpp
M libc/test/src/unistd/read_write_test.cpp
M libc/test/src/unistd/symlink_test.cpp
M libc/test/src/unistd/symlinkat_test.cpp
M libc/test/src/unistd/syscall_test.cpp
M libc/test/src/unistd/truncate_test.cpp
M libc/test/src/unistd/unlink_test.cpp
M libc/test/src/unistd/unlinkat_test.cpp
Log Message:
-----------
[libc] Remove #include <sys/whatever.h> (#209449)
and replace with granular includes of type/macro proxy headers -- where
those headers exist. I'm leaving the creation of new proxy headers for
another patch.
Assisted by Gemini.
Commit: 15776b5cddd4bfd8ff06f2aac6e9eea09cf0112c
https://github.com/llvm/llvm-project/commit/15776b5cddd4bfd8ff06f2aac6e9eea09cf0112c
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/GenericCycleInfo.h
Log Message:
-----------
[CycleInfo] Remove GenericCycle::TopLevelCycle. NFC (#209677)
moveTopLevelCycleToNewParent maintains TopLevelCycle eagerly, rewriting
the whole re-parented subtree with depth_first. When discovery nests k
cycles one by one this is quadratic, and the df_iterator walk plus its
visited set dominate construction on deep nests (~78% of time on a
1500-deep nest).
Walk ParentCycle links in getTopLevelParentCycle instead and delete the
member. The walk is valid during construction too: parent links are
always current, and discovery queries blocks whose innermost cycle sits
at the top of the forest being merged, so the walk is short.
Aided by Claude Fable 5
Commit: af84127cbfc571f86cf7c9ac344223e190bb9970
https://github.com/llvm/llvm-project/commit/af84127cbfc571f86cf7c9ac344223e190bb9970
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
Log Message:
-----------
[SPIR-V] Remove dead typed pointer check in getArgSPIRVType (#209515)
Arg->getType() can never be a TypedPointerType since opaque pointers are
now the only pointer representation in LLVM IR
Commit: b78a0acaa964804151dd3a25eaec360baacfd631
https://github.com/llvm/llvm-project/commit/b78a0acaa964804151dd3a25eaec360baacfd631
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
Log Message:
-----------
[SPIR-V] Unify duplicated named MDNode lookup helper (#209376)
Commit: 771d152cd10a05a10023beb0ff289ea1180b1751
https://github.com/llvm/llvm-project/commit/771d152cd10a05a10023beb0ff289ea1180b1751
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/test/CodeGen/SPIRV/passes/SPIRVLegalizePointerCast.ll
Log Message:
-----------
[SPIR-V] Preserve offset alignment in pointer cast legalization (#209251)
Splitting a load/store into per-element accesses reused the original
alignment for every element, which could wrongly strengthen or discard
alignment
Compute each split access alignment via commonAlignment with its
DataLayout derived byte offset matching SPIRVLegalizerInfo.cpp
Commit: 046acff1018f034e2a5d714c7287b9055148d1c7
https://github.com/llvm/llvm-project/commit/046acff1018f034e2a5d714c7287b9055148d1c7
Author: SiHuaN <liyongtai at iscas.ac.cn>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
Log Message:
-----------
[RISCV][P-ext] Add packed saturating rounding shift codegen (#208630)
Add codegen for `pssha`, `psshar`, `psshl`, and `psshlr` on RV32 and
RV64.
Commit: 396a2d700bba0f9d4ac97198921beb7413e5ce5c
https://github.com/llvm/llvm-project/commit/396a2d700bba0f9d4ac97198921beb7413e5ce5c
Author: SiHuaN <liyongtai at iscas.ac.cn>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rvp-insert-subvector.ll
Log Message:
-----------
[RISCV][P-ext] Fold packed insert-into-zero to zero-extend (#208006)
An insert_subvector of a 32-bit packed type (v4i8/v2i16) into a zero-filled
64-bit packed vector at index 0 is a zero-extend. Fold it so RV64 emits a
single zext.w instead of scalarizing into a byte-wise repack; RV32
concatenates with a zero half into the GPRPair.
Commit: bdd15ffec5f1e14962f86cbdb82a03016c2c5924
https://github.com/llvm/llvm-project/commit/bdd15ffec5f1e14962f86cbdb82a03016c2c5924
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/srl64_reduce.ll
M llvm/test/CodeGen/AMDGPU/srl64_reduce_flags.ll
M llvm/test/CodeGen/AMDGPU/sroa-before-unroll.ll
M llvm/test/CodeGen/AMDGPU/sroa-phi-nodes.ll
M llvm/test/CodeGen/AMDGPU/ssubo.ll
M llvm/test/CodeGen/AMDGPU/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/stack-passed-subdword-arg-crash-issue157997.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll
M llvm/test/CodeGen/AMDGPU/stack-realign.ll
M llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
M llvm/test/CodeGen/AMDGPU/stackguard.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.invalid.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/stale-livevar-in-twoaddr-pass.mir
M llvm/test/CodeGen/AMDGPU/statepoint-asm-printer.mir
M llvm/test/CodeGen/AMDGPU/statepoint-insert-waitcnts.mir
M llvm/test/CodeGen/AMDGPU/store-atomic-flat.ll
M llvm/test/CodeGen/AMDGPU/store-atomic-global.ll
M llvm/test/CodeGen/AMDGPU/store-atomic-local.ll
M llvm/test/CodeGen/AMDGPU/store-barrier.ll
M llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll
M llvm/test/CodeGen/AMDGPU/store-global.ll
M llvm/test/CodeGen/AMDGPU/store-hi16.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-local.ll
M llvm/test/CodeGen/AMDGPU/store-private.ll
M llvm/test/CodeGen/AMDGPU/store-to-constant.ll
M llvm/test/CodeGen/AMDGPU/store-v3i64.ll
M llvm/test/CodeGen/AMDGPU/store-vector-ptrs.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/stress-calls.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fma.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fma.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f64.ll
M llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
M llvm/test/CodeGen/AMDGPU/structurize-hoist.ll
M llvm/test/CodeGen/AMDGPU/sub-zext-cc-zext-cc.ll
M llvm/test/CodeGen/AMDGPU/sub.i16.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/sub64-low-32-bits-known-zero.ll
M llvm/test/CodeGen/AMDGPU/sub_i1.ll
M llvm/test/CodeGen/AMDGPU/sub_u64.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
M llvm/test/CodeGen/AMDGPU/subreg-eliminate-dead.ll
M llvm/test/CodeGen/AMDGPU/subreg-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
M llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
M llvm/test/CodeGen/AMDGPU/subvector-test.mir
M llvm/test/CodeGen/AMDGPU/swdev-549940.ll
M llvm/test/CodeGen/AMDGPU/swdev282079.ll
M llvm/test/CodeGen/AMDGPU/swdev282079.mir
M llvm/test/CodeGen/AMDGPU/swdev373493.ll
M llvm/test/CodeGen/AMDGPU/swdev380865.ll
M llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
M llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll
M llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
M llvm/test/CodeGen/AMDGPU/switch-default-block-unreachable.ll
M llvm/test/CodeGen/AMDGPU/switch-unreachable.ll
M llvm/test/CodeGen/AMDGPU/swizzle.bit.extract.ll
M llvm/test/CodeGen/AMDGPU/syncscopes.ll
M llvm/test/CodeGen/AMDGPU/tail-call-amdgpu-gfx.ll
M llvm/test/CodeGen/AMDGPU/tail-call-cgp.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.waterfall.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.ll
M llvm/test/CodeGen/AMDGPU/tail-duplication-convergent.ll
M llvm/test/CodeGen/AMDGPU/target-mem-intrinsic-metadata.ll
M llvm/test/CodeGen/AMDGPU/tgsplit.ll
M llvm/test/CodeGen/AMDGPU/threeaddr-wmma.mir
M llvm/test/CodeGen/AMDGPU/tid-kd-xnack-any.ll
M llvm/test/CodeGen/AMDGPU/tid-kd-xnack-off.ll
M llvm/test/CodeGen/AMDGPU/tid-kd-xnack-on.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (34) (#209598)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping
the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 2af345af8dbffa975589b5f774ab006f372b4c00
https://github.com/llvm/llvm-project/commit/2af345af8dbffa975589b5f774ab006f372b4c00
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/include/lldb/Target/MemoryRegionInfo.h
M lldb/source/Plugins/Process/Utility/LinuxProcMaps.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
M lldb/unittests/Process/Utility/LinuxProcMapsTest.cpp
Log Message:
-----------
[lldb-server] Add type info for qMemoryinfo reponse (#209235)
Use the name of the memory region to report the known cases where an
address points to stack/heap: "[stack]" or "[heap"].
According to [1], the "[stack]" name is the main thread's stack region:
```
[stack]
The initial process's (also known as the main
thread's) stack.
```
For other threads, we can't know their stack region because this field
got removed in newer kernels:
```
[stack:tid] (from Linux 3.4 to Linux 4.4)
A thread's stack (where the tid is a thread ID). It
corresponds to the /proc/pid/task/tid/ path. This
field was removed in Linux 4.5, since providing this
information for a process with large numbers of
threads is expensive.
```
So we can only set "isStack" to Yes in some cases, and to "No" when the
name is "[heap]". If there is no name, or the name is something else, we
keep the "don't know" answer.
[1]: https://man7.org/linux/man-pages/man5/proc_pid_maps.5.html
Commit: 06bf4bfff830207da473c06f2d90f93d777b51bb
https://github.com/llvm/llvm-project/commit/06bf4bfff830207da473c06f2d90f93d777b51bb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
Log Message:
-----------
[X86] combineINSERT_SUBVECTOR - enable shuffle combining of concat(extractsub(shuffle),extractsub(shuffle)) patterns (#209510)
Reuse the peekThroughBitcastsAndExtracts helper that we already use for insertsub(shuffle,extractsub(shuffle)) patterns
Commit: 13bdd50540a5365f5f25b0fff7410d5d69157a51
https://github.com/llvm/llvm-project/commit/13bdd50540a5365f5f25b0fff7410d5d69157a51
Author: Harry Ramsey <harry.ramsey at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/scalable_masked_interleaved_stores.ll
Log Message:
-----------
[AArch64][ISel] Enable masked interleaved stores for splat values (#207950)
Enable masked interleaved store combine to recognise splat values and
split them into SVE component vectors. This allows the existing stN
lowering path to handle masked stores where the stored value is a splat
rather than an explicit vector.interleave result.
Commit: 67dabeefa6271d638f548a68b20ffdc8d457e312
https://github.com/llvm/llvm-project/commit/67dabeefa6271d638f548a68b20ffdc8d457e312
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/cxx11.cpp
Log Message:
-----------
[clang][bytecode] Fix "declared here" location of ... (#209696)
... "read outside its lifetime" diagnostics.
We should be pointing to the first decl.
Commit: 0d33149259ab717d48d8e34b6cb6eae87c28e631
https://github.com/llvm/llvm-project/commit/0d33149259ab717d48d8e34b6cb6eae87c28e631
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/sroa-phi-nodes.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-invalid-any-off-on.ll
M llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir
M llvm/test/CodeGen/AMDGPU/token-factor-inline-limit-test.ll
M llvm/test/CodeGen/AMDGPU/track-spilled-vgpr-liveness.mir
M llvm/test/CodeGen/AMDGPU/trans-coexecution-hazard.mir
M llvm/test/CodeGen/AMDGPU/trans-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/triton_regression_no_waterfall.ll
M llvm/test/CodeGen/AMDGPU/triton_regression_no_waterfall.mir
M llvm/test/CodeGen/AMDGPU/triv-disjoint-mem-access-neg-offset.mir
M llvm/test/CodeGen/AMDGPU/true16-fold.mir
M llvm/test/CodeGen/AMDGPU/true16-imm-folded-to-0-regression.ll
M llvm/test/CodeGen/AMDGPU/true16-ra-pre-gfx11-regression-test.mir
M llvm/test/CodeGen/AMDGPU/true16-saveexec.mir
M llvm/test/CodeGen/AMDGPU/trunc-bitcast-vector.ll
M llvm/test/CodeGen/AMDGPU/trunc-cmp-constant.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-i1.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-i64.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-vec-i16-to-i8.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/truncate-lshr-cast-build-vector-combine.ll
M llvm/test/CodeGen/AMDGPU/tti-unroll-prefs.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-bundle.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-fma-f64.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-mad.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-wmma.mir
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/udivrem24.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/umed3.ll
M llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
M llvm/test/CodeGen/AMDGPU/unaligned-buffer.ll
M llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
M llvm/test/CodeGen/AMDGPU/unallocatable-bundle-regression.mir
M llvm/test/CodeGen/AMDGPU/undef-build-vector.ll
M llvm/test/CodeGen/AMDGPU/undef-copy-propagation.mir
M llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
M llvm/test/CodeGen/AMDGPU/undef-subreg-use-after-coalesce.mir
M llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/unexpected-reg-unit-state.mir
M llvm/test/CodeGen/AMDGPU/unfold-masked-merge-scalar-variablemask.ll
M llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll
M llvm/test/CodeGen/AMDGPU/uniform-alignbit.ll
M llvm/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-crash.ll
M llvm/test/CodeGen/AMDGPU/uniform-intrin-combine-wqm-demote.ll
M llvm/test/CodeGen/AMDGPU/uniform-load-from-tid.ll
M llvm/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll
M llvm/test/CodeGen/AMDGPU/uniform-phi-with-undef.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
M llvm/test/CodeGen/AMDGPU/uniform-vgpr-to-sgpr-return.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-attribute-missing.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-multistep.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-nested-function-calls.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-prevent-attribute-propagation.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-propagate-attribute.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-recursion-test.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-test.ll
M llvm/test/CodeGen/AMDGPU/uniform_branch_with_floating_point_cond.ll
M llvm/test/CodeGen/AMDGPU/unnamed-function-resource-info.ll
M llvm/test/CodeGen/AMDGPU/unpack-half.ll
M llvm/test/CodeGen/AMDGPU/unroll.ll
M llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/unsupported-atomics.ll
M llvm/test/CodeGen/AMDGPU/unsupported-av-load.ll
M llvm/test/CodeGen/AMDGPU/unsupported-av-store.ll
M llvm/test/CodeGen/AMDGPU/unsupported-calling-conv-call.ll
M llvm/test/CodeGen/AMDGPU/unsupported-calling-conv-func.ll
M llvm/test/CodeGen/AMDGPU/unsupported-code-object-version.ll
M llvm/test/CodeGen/AMDGPU/unsupported-cs-chain.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-g16.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-sample.ll
M llvm/test/CodeGen/AMDGPU/update-lds-alignment.ll
M llvm/test/CodeGen/AMDGPU/update-phi.ll
M llvm/test/CodeGen/AMDGPU/urem.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (35) (#209599)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping
the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: ba9f8e448ecd6f99664ed6b15c8d193650197845
https://github.com/llvm/llvm-project/commit/ba9f8e448ecd6f99664ed6b15c8d193650197845
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/UndefinedAssignmentChecker.cpp
M clang/test/Analysis/operator-calls.cpp
Log Message:
-----------
[clang][analyzer] Improved message in uninitialized.Assign at default assignment (#208173)
Commit: 1a0ddbdff9eef0257445778f36dd19b74f018487
https://github.com/llvm/llvm-project/commit/1a0ddbdff9eef0257445778f36dd19b74f018487
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/Combiner.h
M llvm/lib/CodeGen/GlobalISel/Combiner.cpp
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
M llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
Log Message:
-----------
[GlobalISel] Filter combiner worklists (#197693)
This follows on from #196017 which added an opcode predicate for GICombiner
matchers and used it to return from tryCombineAll before executing the match
table.
The better approach is to not add opcodes with no combines to the worklist in
the first place. This is a further -0.35% CTMark geomean improvement on
aarch64-O0-g, sqlite is -0.67%.
https://llvm-compile-time-tracker.com/compare.php?from=35f5d7ea802eae78b26a5fb2a46f072acd15f49d&to=c356bec46b68b59f37b26347f93676c9102d810c&stat=instructions%3Au
I also measured O3 locally and it's positive:
```
stage1-aarch64-O3 -fglobal-isel
instructions:u diff
old new
7zip 203863583445 203865335443 0.00%
Bullet 103920943623 103917036315 -0.00%
ClamAV 53008970261 52971646424 -0.07%
SPASS 41843361245 41815471487 -0.07%
consumer-typeset 31848080935 31816255572 -0.10%
kimwitu++ 39779892082 39733563964 -0.12%
lencod 67158153709 67134337444 -0.04%
mafft 36689364945 36675438948 -0.04%
sqlite3 33436727535 33410098701 -0.08%
tramp3d-v4 76553056559 76569825676 0.02%
geomean 57208304686 57180409869 -0.05%
```
I am a bit worried about the incurred overhead of this for other opt levels as
we add more combines, but right now at least the data is positive.
Assisted-by: codex
Commit: 3e4160fdc3d5bb0ed86480604bdfcd3130e7dd37
https://github.com/llvm/llvm-project/commit/3e4160fdc3d5bb0ed86480604bdfcd3130e7dd37
Author: Krisitan Erik Olsen <kristian.erik at outlook.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86LowerTileCopy.cpp
A llvm/test/CodeGen/X86/AMX/pr209512.ll
Log Message:
-----------
[X86] Skip debug instructions in tile copy lowering (#209640)
X86LowerTileCopy iterates over instructions in reverse to track live
registers, calling LiveRegUnits::stepBackward on every instruction
unconditionally. Since commit 16b2ef32 added an assertion that
stepBackward must not receive debug instructions, functions containing
debug info hit the assertion during tile copy lowering.
This patch skips debug instructions early in the loop, matching the
guard pattern used in RegisterScavenging.cpp and X86FixupBWInsts.cpp.
Fixes #209512
Commit: 0e877fd1a637ec2964883d324600211a6907b7bd
https://github.com/llvm/llvm-project/commit/0e877fd1a637ec2964883d324600211a6907b7bd
Author: Kito Cheng <kito.cheng at sifive.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-f16.cl
M llvm/lib/Target/README.txt
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/tan.ll
M llvm/test/Transforms/InstCombine/fdiv-cos-sin.ll
M llvm/test/Transforms/InstCombine/fdiv-sin-cos.ll
M llvm/test/Transforms/InstCombine/may-alias-errno.ll
A llvm/test/Transforms/InstCombine/sincos-fpmath.ll
A llvm/test/Transforms/InstCombine/sincos.ll
Log Message:
-----------
Reland "[InstCombine] Combine llvm.sin/llvm.cos libcall pairs into llvm.sincos" (#194616)
This reland #184760
Fixed https://lab.llvm.org/buildbot/#/builders/123/builds/39337
The root cause is new created llvm.sincos is inserted into the right
after of the sin/cos's argument, however we didn't check if it's PHI, it
may cause it inserted into the middle of PHIs, and then fail the
verification.
Teach InstCombine to recognize pairs of `llvm.sin(x)` and `llvm.cos(x)`
intrinsic calls that share the same argument and replace them with a
single `llvm.sincos(x)` call, extracting the individual results.
The optimization works in two phases:
1. **SimplifyLibCalls**: Convert `sin`/`cos` C library calls (e.g.
`sinf`, `cosf`, `sin`, `cos`, `sinl`, `cosl`) into `llvm.sin` /
`llvm.cos` intrinsics when the call does not access memory (i.e. does
not set `errno`). This normalization step brings library calls into
the same form as compiler-generated intrinsics.
2. **InstCombineCalls**: When visiting an `llvm.sin` or `llvm.cos`
intrinsic, scan the users of the shared argument for a matching
counterpart. If found, emit a single `llvm.sincos` call placed right
after the argument definition, replace both original calls, and erase
the matched instruction.
Also remove the completed sincos TODO from Target/README.txt.
Commit: 4aa1590ad66a1bff9b3c74b4a2c7366473015b4c
https://github.com/llvm/llvm-project/commit/4aa1590ad66a1bff9b3c74b4a2c7366473015b4c
Author: Ella Ma <alansnape3058 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/StaticAnalyzer/Checkers/DeadStoresChecker.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineC.cpp
A clang/test/Analysis/issue-173210-self-assign-init.c
Log Message:
-----------
[analyzer] Ignoring `T v=v;` idiom for uninitialized variable checker and dead store checker (#187530)
Closing #173210
The self-assignment initialization `Type var = var;` is an idiom in C
code. The analyzer is expected to suppress the uninitialized assignment
reports and dead store reports for this idiom. Variables that are really
uninitialized will be reported until they are actually used. Since GCC
will not generate assembly code for such usage, even if under -O0
optimization (but Clang will), this patch resolves this problem by
ignoring such self-assigned `DeclStmt`s in the `ExprEngine`, as well as
in the `DeadStoreObs` of the dead store checker.
This ignorance will be applied to C variables and non-reference C++
variables. For record types in C++, since the constructors will always
be invoked, they will not be affected by this change.
Commit: 94ef4fce34ca8bbf79729814959c0d70b4a9ba3b
https://github.com/llvm/llvm-project/commit/94ef4fce34ca8bbf79729814959c0d70b4a9ba3b
Author: Victor Campos <victor.campos at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libc/test/UnitTest/CMakeLists.txt
A libc/test/UnitTest/ConstraintHandlerCheckingTest.h
Log Message:
-----------
[libc] Annex K: Add constraint handler unit test class (#197707)
This unit test class will be useful for the tests related to Annex K.
The functions in Annex K may call a constraint handler, so this new unit
test class will facilitate the checks that the constraint handling
mechanism is working as expected.
Commit: 4b455a91141d59ace3a29870c885f5f5e4ff0506
https://github.com/llvm/llvm-project/commit/4b455a91141d59ace3a29870c885f5f5e4ff0506
Author: Dan Liew <dan at su-root.co.uk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaBoundsSafety.cpp
M clang/test/Sema/attr-sized-by-late-parsed-struct-ptrs.c
M clang/test/Sema/attr-sized-by-or-null-late-parsed-struct-ptrs.c
M clang/test/Sema/attr-sized-by-or-null-struct-ptrs.c
M clang/test/Sema/attr-sized-by-struct-ptrs.c
Log Message:
-----------
[BoundsSafety][Sema] Allow `sized_by`/`sized_by_or_null` on pointers to structs with a flexible array member (#209603)
`Sema::CheckCountedByAttrOnField()` in `SemaBoundsSafety.cpp` rejects
the `counted_by` family of attributes when the pointee is a struct that
contains a flexible array member (FAM). For example:
```
struct has_unannotated_fam {
int count;
int buffer[];
};
struct on_member_pointer_struct_with_fam {
int size;
struct has_unannotated_fam *objects __counted_by(size);
};
```
This restriction makes sense for `counted_by`/`counted_by_or_null`
because the size of a struct with a FAM is not statically known, so the
count of elements cannot be used to compute the size of the buffer.
However, the same check was incorrectly applied to `sized_by` and
`sized_by_or_null`. Unlike `counted_by`, these attributes describe the
size of the buffer in *bytes* rather than in *elements*, so the pointee
size is irrelevant and there is no ambiguity. Previously the following
would be rejected:
```
struct on_member_pointer_struct_with_fam {
int size;
struct has_unannotated_fam *objects __sized_by(size);
};
```
with the diagnostic:
```
error: 'sized_by' cannot be applied to a pointer with pointee of unknown
size because 'struct has_unannotated_fam' is a struct type with a
flexible array member
```
This patch guards the FAM check with `!CountInBytes` so that it only
applies to `counted_by`/`counted_by_or_null`. `sized_by` and
`sized_by_or_null` on such pointers are now correctly accepted.
The obsolete `expected-error` directives in the affected `sized_by` and
`sized_by_or_null` Sema tests are removed, turning those cases into
positive tests.
Assisted-by: Claude Code
rdar://182226884
Commit: 3485d8591992a967553493c53f17d9f3e8a0fc8e
https://github.com/llvm/llvm-project/commit/3485d8591992a967553493c53f17d9f3e8a0fc8e
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/test/SemaCXX/constexpr-late-instantiation.cpp
Log Message:
-----------
[Clang] Ensure correct template parameter depth for abbreviated templates (#209693)
This fixes another case of member functions where we overlooked template
depths when only abbreviated template parameters are involved.
This mirrors previous fix cfb25203c25f, but I don't intend to put it in
ParseTrailingRequiresClause because we might want the similar fix for
e.g. noexcept expressions, so let's keep it inline for future refactor.
The example comes from #205557.
Commit: a208080eff277fc4829f3519e1f918aa4eb6adeb
https://github.com/llvm/llvm-project/commit/a208080eff277fc4829f3519e1f918aa4eb6adeb
Author: Valery Pykhtin <valery.pykhtin at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
Log Message:
-----------
[NFC][AMDGPU] Use SIInstrFlags predicates in MC layer (#206766)
Replace raw TSFlags accesses with SIInstrFlags predicate calls in
AMDGPUInstPrinter and AMDGPUMCCodeEmitter.
Part of a series following the introduction of SIInstrFlags predicates.
Commit: f48b09bbe0654fcd7ddf6b8a8aec807d8552a816
https://github.com/llvm/llvm-project/commit/f48b09bbe0654fcd7ddf6b8a8aec807d8552a816
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/dxc_debug.hlsl
M llvm/lib/Target/DirectX/DXContainerGlobals.cpp
M llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
M llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
A llvm/test/CodeGen/DirectX/ContainerData/SourceInfo-Strip.ll
M llvm/test/CodeGen/DirectX/embed-ildb.ll
Log Message:
-----------
[Driver][DirectX] Add `/Qsource_in_debug_module` flag (#204415)
Adds a flag that embeds the source code info into `dx.source` nodes in
bitcode, for both main DXContainer and PDB file output. For the PDB
file, it also removes the `SRCI` part from the output.
Commit: 17406f7e49d45808cb828d6bc225b6f6656938b1
https://github.com/llvm/llvm-project/commit/17406f7e49d45808cb828d6bc225b6f6656938b1
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libsycl/docs/index.rst
R libsycl/include/sycl/__impl/detail/default_async_handler.hpp
M libsycl/include/sycl/__impl/event.hpp
M libsycl/include/sycl/__impl/exception.hpp
A libsycl/include/sycl/__impl/info/event.hpp
M libsycl/include/sycl/__impl/queue.hpp
M libsycl/src/detail/event_impl.cpp
M libsycl/src/detail/event_impl.hpp
M libsycl/src/detail/global_objects.cpp
M libsycl/src/detail/global_objects.hpp
M libsycl/src/detail/queue_impl.cpp
M libsycl/src/detail/queue_impl.hpp
A libsycl/src/detail/spinlock.hpp
M libsycl/src/event.cpp
M libsycl/src/exception_list.cpp
M libsycl/src/queue.cpp
M libsycl/unittests/CMakeLists.txt
M libsycl/unittests/common/device_images.hpp
A libsycl/unittests/common/scoped_binary_registration.hpp
M libsycl/unittests/common/unittests_helper.hpp
M libsycl/unittests/device_selector/get_device_preference.cpp
A libsycl/unittests/event/CMakeLists.txt
A libsycl/unittests/event/async_handler.cpp
A libsycl/unittests/event/event.cpp
M libsycl/unittests/mock/helpers.cpp
M libsycl/unittests/mock/helpers.hpp
M libsycl/unittests/mock/mock.cpp
M libsycl/unittests/program_manager/register_and_unregister.cpp
M libsycl/unittests/queue/sycl_kernel_launch.cpp
Log Message:
-----------
[libsycl] implement methods of synchronization in event and queue classes (#205860)
Extends libsycl’s sycl::event API by adding default-constructed event
semantics, wait-list exposure and async exceptions handling. Async
exceptions handling is generic for event and queue APIs and though added
to sycl::queue API as well.
Introduces async-exception aggregation/flush infrastructure (global
associative container).
Adds/adjusts unit tests and unifies test binary registration utilities
(Scoped*Registration, namespace cleanup).
This PR was assisted by GH Copilot.
Signed-off-by: Tikhomirova, Kseniya
[kseniya.tikhomirova at intel.com](mailto:kseniya.tikhomirova at intel.com)
Commit: ffcc00a1418e623176f348830ab16ad0ececba72
https://github.com/llvm/llvm-project/commit/ffcc00a1418e623176f348830ab16ad0ececba72
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/source/Plugins/Platform/POSIX/PlatformPOSIX.cpp
M lldb/test/API/python_api/sbplatform/TestSBPlatform.py
Log Message:
-----------
[lldb][POSIX] Correctly report error copying from remote platform (#207365)
This fixes a bug I found where copying a file from a remote Linux
platform using the API would claim that it succeeded, but it had not.
The local file was read only so it was not updated. The host Linux
platform's copy did not have this bug.
There are two tests, one which will run if the testing platform is not
already a remote. This one spawns a "remote" platform, which is actually
still on the host, but it's enough to take the remote code path in the
POSIX platform implementation.
The second uses the testing platform. If that's a remote, use that, if
it's host then we use the host platform to check local copying
behaviour.
This test is not as specific as I'd like it to be, but I wanted
something that could run on many platforms. Even if the copy fails for a
reason other than permissions, at least we are checking that the failure
is propagated.
Commit: df1838f5d961f9587ca4f90d992bef81cc6155db
https://github.com/llvm/llvm-project/commit/df1838f5d961f9587ca4f90d992bef81cc6155db
Author: Karthika Devi C <kartc at qti.qualcomm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M polly/include/polly/CodeGen/LoopGenerators.h
M polly/lib/CodeGen/IslAst.cpp
M polly/lib/CodeGen/IslNodeBuilder.cpp
M polly/lib/CodeGen/LoopGenerators.cpp
M polly/test/CodeGen/Metadata/basic_vec_annotate.ll
A polly/test/CodeGen/Metadata/skip_vec_annotate_fp_dist1.ll
Log Message:
-----------
[Polly] Skip vectorize.enable for FP loops with dist=1 dependences (#205756)
When -polly-annotate-metadata-vectorize is active, Polly marks its
generated loops with llvm.loop.vectorize.enable=true. This is harmful
for loops with a loop-carried dependence of distance 1 that involve
floating-point operations: the Loop Vectorizer reorders FP operations
(e.g. scalar reduction like q = factor*q), producing results that differ
from the sequential scalar reference and causing correctness failures.
Two changes are made:
1. IslAst.cpp: add PollyVectorizeMetadata to the PerformParallelTest
gate so that dependence-distance computation is performed whenever
-polly-annotate-metadata-vectorize is passed, not only when
-polly-parallel or a vectorizer is active.
2. IslNodeBuilder.cpp / LoopGenerators.cpp: when a loop has a dist=1
dependence involving FP operations, omit the vectorize.enable annotation
entirely. This lets the Loop Vectorizer apply its own cost model and
legality checks decide.
Commit: f114107e67b967de450c0e5c0acf84e70d3d1208
https://github.com/llvm/llvm-project/commit/f114107e67b967de450c0e5c0acf84e70d3d1208
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/include/lldb/Utility/Log.h
M lldb/source/Commands/CommandObjectLog.cpp
M lldb/source/Utility/Log.cpp
M lldb/unittests/Utility/LogTest.cpp
Log Message:
-----------
[lldb] Return llvm::Expected from ListChannelCategories (#209468)
Expected<string> is equivalent to bool+stream, but harder to misuse.
Commit: edbf9e3096c027b61d72df6397c2963be56b2b7b
https://github.com/llvm/llvm-project/commit/edbf9e3096c027b61d72df6397c2963be56b2b7b
Author: Dan Liew <dan at su-root.co.uk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/Sema/SemaBoundsSafety.cpp
Log Message:
-----------
[NFC][BoundsSafety] Re-order some checks in `Sema::CheckCountedByAttrOnField` (#209713)
This is post-merge feedback for #209603
(4b455a91141d59ace3a29870c885f5f5e4ff0506).
Commit: d9b56d3e5e012a618f55318662e3e5c9ba2c4abf
https://github.com/llvm/llvm-project/commit/d9b56d3e5e012a618f55318662e3e5c9ba2c4abf
Author: Arendelle <Arendelle_ at outlook.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
M clang/test/AST/ByteCode/unions.cpp
M clang/test/SemaCXX/constant-expression-cxx2a.cpp
Log Message:
-----------
[clang][constexpr] Move anonymous-union check before getDestructor() in HandleDestructionImpl (#197416)
When HandleDestructionImpl destroys a class object during constant
evaluation, it attempts to look up the class's destructor via
getDestructor() before checking whether the record is an anonymous
union. Anonymous unions should not have their destructors invoked
directly during constant evaluation — their lifetime is managed by the
enclosing class's destructor. Move the anonymous-union short-circuit
before the getDestructor() call so anonymous unions are handled early,
regardless of whether getDestructor() returns null or not.
This fixes cases where an object with an implicitly-defined constexpr
destructor stored inside an anonymous union member was incorrectly
rejected during constant evaluation.
Commit: 083acc3c31fd4696bbc6d4b1c647c63ac976a7ec
https://github.com/llvm/llvm-project/commit/083acc3c31fd4696bbc6d4b1c647c63ac976a7ec
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/cxx2a.cpp
Log Message:
-----------
[clang][bytecode] Fix uninitialized diagnostics (#209702)
... if the pointer is also outside its lifetime. In that case, prefer to
diagnose it as outside its lifetime.
Commit: d0a85f53b9e6c3b7146736a6b19524d1e5f738ee
https://github.com/llvm/llvm-project/commit/d0a85f53b9e6c3b7146736a6b19524d1e5f738ee
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/use-after-free-after-cleanup-failed-vreg.ll
M llvm/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/usubsat.ll
M llvm/test/CodeGen/AMDGPU/v-cmp-cse-across-loop.mir
M llvm/test/CodeGen/AMDGPU/v1024.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll
M llvm/test/CodeGen/AMDGPU/v_mac.ll
M llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll
M llvm/test/CodeGen/AMDGPU/v_mac_f16.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_mov_b64_expand_and_shrink.mir
M llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
M llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-set-kill.mir
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-wrong-kill-flags.mir
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.ll
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard-sdwa.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-vgpr-msb-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane16var-hazard.mir
M llvm/test/CodeGen/AMDGPU/vector-alloca-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca-atomic.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca-limits.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
M llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir
M llvm/test/CodeGen/AMDGPU/vector_range_metadata.ll
M llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vectorize-buffer-fat-pointer.ll
M llvm/test/CodeGen/AMDGPU/vectorize-global-local.ll
M llvm/test/CodeGen/AMDGPU/vectorize-loads.ll
M llvm/test/CodeGen/AMDGPU/vectorize-unroll-metadata.ll
M llvm/test/CodeGen/AMDGPU/verifier-sdwa-cvt.mir
M llvm/test/CodeGen/AMDGPU/verify-constant-bus-violations.mir
M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
M llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx12-gds.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/verify-image-vaddr-align.mir
M llvm/test/CodeGen/AMDGPU/verify-image.mir
M llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir
M llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd.mir
M llvm/test/CodeGen/AMDGPU/vgpr-agpr-limit-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
M llvm/test/CodeGen/AMDGPU/vgpr-excess-threshold-percent-invalid.ll
M llvm/test/CodeGen/AMDGPU/vgpr-excess-threshold-percent.ll
M llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
M llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250-t16.mir
M llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.mir
M llvm/test/CodeGen/AMDGPU/vgpr-remat-v_pk_mov_b32.mir
M llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
M llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir
M llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill-dead-frame-in-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (36) (#209600)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: c58ba1cf51d2886994da7e667a05c1bfe4f4396b
https://github.com/llvm/llvm-project/commit/c58ba1cf51d2886994da7e667a05c1bfe4f4396b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
M llvm/test/CodeGen/AMDGPU/vi-removed-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/visit-physreg-vgpr-imm-folding-bug.ll
M llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
M llvm/test/CodeGen/AMDGPU/vmem-vcc-hazard.mir
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vop-shrink.ll
M llvm/test/CodeGen/AMDGPU/vopc-remat.mir
M llvm/test/CodeGen/AMDGPU/vopc_dpp-true16.mir
M llvm/test/CodeGen/AMDGPU/vopc_dpp.ll
M llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
M llvm/test/CodeGen/AMDGPU/vopd-combine-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/vopd-combine.mir
M llvm/test/CodeGen/AMDGPU/vopd-gfx12-f64-relaxed.mir
M llvm/test/CodeGen/AMDGPU/vopd-src2acc-delay.mir
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.mir
M llvm/test/CodeGen/AMDGPU/wait-xcnt-atomic-rmw-optimization.ll
M llvm/test/CodeGen/AMDGPU/wait-xcnt-drain.mir
M llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
M llvm/test/CodeGen/AMDGPU/wait.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-agpr.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-debug-output-crash.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-flat.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-func-global-inv.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-global-inv-wb.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-kmcnt-scc-different-block.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-flushed.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-flushed.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-pattern.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-store-barrier.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-irreducible.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-opt.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-single-basic-block.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-looptest.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-meta-instructions.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-multiple-funcs.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-overflow.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-permute.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting-vscnt.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-sample-out-order.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-sample-waw.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-skip-meta.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-unscoped.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-vinterp.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-vmcnt-loop.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-vmem-waw.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-wbl2.ll
M llvm/test/CodeGen/AMDGPU/waitcnt.mir
M llvm/test/CodeGen/AMDGPU/waterfall-call-inreg-agpr.ll
M llvm/test/CodeGen/AMDGPU/waterfall-call-inreg-agpr.mir
M llvm/test/CodeGen/AMDGPU/waterfall-call-target-av-register-failure.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
M llvm/test/CodeGen/AMDGPU/while-break.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/widen_extending_scalar_loads.ll
M llvm/test/CodeGen/AMDGPU/wmma-coexecution-valu-hazards.mir
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx12-w32.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx12-w64.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1251-w32.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards.mir
M llvm/test/CodeGen/AMDGPU/wmma-nop-hoisting.mir
M llvm/test/CodeGen/AMDGPU/wmma_modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_32.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_64.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
M llvm/test/CodeGen/AMDGPU/wqm-debug-instr-terminator.mir
M llvm/test/CodeGen/AMDGPU/wqm-gfx11.ll
M llvm/test/CodeGen/AMDGPU/wqm-propagate-for-execz-side-effect.mir
M llvm/test/CodeGen/AMDGPU/wqm-terminators.mir
M llvm/test/CodeGen/AMDGPU/wqm.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (37) (#209601)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 6b3b6a88905cfb7e098d3c4a790ae8a196cfeab2
https://github.com/llvm/llvm-project/commit/6b3b6a88905cfb7e098d3c4a790ae8a196cfeab2
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/include/lldb/Target/StackID.h
M lldb/source/Target/StackFrameList.cpp
M lldb/source/Target/StackID.cpp
M lldb/source/Target/ThreadPlanStepInstruction.cpp
M lldb/source/Target/ThreadPlanStepOut.cpp
M lldb/source/Target/ThreadPlanStepRange.cpp
M lldb/source/Target/ThreadPlanStepUntil.cpp
Log Message:
-----------
[lldb][NFC] Create StackID::IsYounger (#209402)
Currently, StackIDs are compared with a custom operator <. There are
some issues with that:
1. It's not clear what "<" means in this context. It really is a test of
"frame A is on top of frame B or not comparable". But this notion is not
expressed through "<".
2. This is not a real operator "<" in the sense that if "!<" does not
imply ">=". In particular, frames may not always be comparable (i.e.
(they are not part of the same stack).
To address these issues, this commit replaces `<` with a custom function
"IsYounger", which makes explicit what is being tested.
Commit: 0f24969ade9df74b11ff70a2c0b1f49ff49e92fd
https://github.com/llvm/llvm-project/commit/0f24969ade9df74b11ff70a2c0b1f49ff49e92fd
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaAMDGPU.cpp
A clang/test/SemaOpenCL/builtins-amdgcn-cmp-deprecated.cl
Log Message:
-----------
[Clang][AMDGPU] Deprecate icmp/fcmp builtins in favor of ballot (#209416)
Deprecate these builtins with a warning recommending
__builtin_amdgcn_ballot_w32 or __builtin_amdgcn_ballot_w64 instead:
__builtin_amdgcn_uicmp
__builtin_amdgcn_uicmpl
__builtin_amdgcn_sicmp
__builtin_amdgcn_sicmpl
__builtin_amdgcn_fcmp
__builtin_amdgcn_fcmpf
Assisted-by: Claude Opus 4.8
Commit: f96628d9cab6c840ef836f3046d5d566dc620596
https://github.com/llvm/llvm-project/commit/f96628d9cab6c840ef836f3046d5d566dc620596
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/Driver/OffloadBundler.cpp
Log Message:
-----------
clang-offload-bundler: Reduce include of Cuda.h to OffloadArch.h (#209723)
This was only using OffloadArch, so use that header directly.
Commit: 11cc8d876e2bb696fef7079eed0a1ff574c0770f
https://github.com/llvm/llvm-project/commit/11cc8d876e2bb696fef7079eed0a1ff574c0770f
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/transfer-signed-facts-to-unsigned.ll
Log Message:
-----------
[ConstraintElim] Transfer SLE facts to unsigned (#209623)
Handle SLE analogous to SLT via getUnsignedPredicate.
Alive2 Proof: https://alive2.llvm.org/ce/z/yNjmL8
PR: https://github.com/llvm/llvm-project/pull/209623
Commit: ca71592c415c2c1e6fe8289d4bcff934279d8315
https://github.com/llvm/llvm-project/commit/ca71592c415c2c1e6fe8289d4bcff934279d8315
Author: Kaviya Rajendiran <67495422+kaviya2510 at users.noreply.github.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Analysis/ArraySectionAnalyzer.h
M flang/include/flang/Optimizer/Builder/FIRBuilder.h
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
A flang/test/HLFIR/inline-hlfir-assign-pointer-overlap.fir
A flang/test/HLFIR/inline-hlfir-assign-scalar-index.fir
A flang/test/HLFIR/inline-hlfir-assign-self-copy-runtime-stride.fir
A flang/test/HLFIR/inline-hlfir-assign-self-copy.fir
A flang/test/Lower/inline-hlfir-assign-forall-threadprivate.f90
A flang/test/Lower/inline-hlfir-assign-pointer-omp.f90
Log Message:
-----------
Reland "[Flang]Add support for inlining hlfir.assign operation where both LHS and RHS are slices of the same array #204532" (#208159)
Added support for inlining hlfir.assign when both LHS and RHS are slices
of the same array. When overlap between the slices cannot be determined,
the pass introduces a disjointness check:
- genIndexBasedDisjointnessCheck(..) is used when both sides are
sections of the same array.
- genAddressBasedDisjointnessCheck(..) used as a fallback for more
complex cases.
At runtime:
- If the slices are disjoint, a direct element-wise copy is performed
without allocating a temporary buffer.
- If overlap is possible, a temporary buffer is allocated, the RHS is
first copied into it and then the data is copied from the temporary
buffer to the LHS.
Fixes https://github.com/llvm/llvm-project/issues/203228
Commit: 1d4148821bf96bef23ea77952031e3e7bec26d3a
https://github.com/llvm/llvm-project/commit/1d4148821bf96bef23ea77952031e3e7bec26d3a
Author: Mel Chen <mel.chen at sifive.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-unroll.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
Log Message:
-----------
[VPlan] Fix nowrap flags for strided access pointers from SCEV (#209453)
This patch addresses two things. First, the offset calculation
(canonical IV * stride) should not reuse the NSW flag of the add
recurrence. The NSW property from SCEV for the original scalar
recurrence does not necessarily hold for the reconstructed
multiplication using the vector canonical IV. The NUW flag, however, can
still be safely propagated.
Second, because vputils::getGEPFlagsForPtr currently doesn't support
recipes other than VPInstruction, and to avoid relying on LLVM IR
function (like calling stripPointerCasts()), we change
VPVectorPointerRecipe's GEP flags to use the add recurrence's flags to
prevent propagating unprovable GEP flags like inbounds.
Commit: 54e36d6ba68c3c5f91bd36c1c9bf8d8af6f8940b
https://github.com/llvm/llvm-project/commit/54e36d6ba68c3c5f91bd36c1c9bf8d8af6f8940b
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/vk-ext-builtin-input.ll
Log Message:
-----------
[SPIR-V] Emit UniformId decoration as OpDecorateId with a Scope id operand (#207958)
Per spec, UniformId operand is a Scope `<id>`, not a literal
Previously it was printed via `printSymbolicOperand<ScopeOperand>`,
which asserts on a real id operand, and never emitted correctly
Commit: dadccf8e6ddb9d87f5b48431a0417dc7b39d9742
https://github.com/llvm/llvm-project/commit/dadccf8e6ddb9d87f5b48431a0417dc7b39d9742
Author: Utkarsh Saxena <usx at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/test/Sema/LifetimeSafety/dangling-field.cpp
Log Message:
-----------
[LifetimeSafety] Suppress false field-escape warnings in destructors (#209614)
Commit: 96a53b1c5356754b4708c0fee8517fd0d69cb1fd
https://github.com/llvm/llvm-project/commit/96a53b1c5356754b4708c0fee8517fd0d69cb1fd
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
M llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
Log Message:
-----------
[SLP] Support memory runtime alias checks
Vectorize straight-line code blocked by runtime-checkable may-alias
dependencies by versioning the block. Drop the deps, and if the tree is
profitable, emit base-object address-range overlap checks branching to a
vector fast path or an original-order scalar fallback.
Fixes #201534
Original Pull Request: https://github.com/llvm/llvm-project/pull/203631
Recommit after revert in a9ba4d3fd27a05b31adfeaab5dcd42d8e43c1931,
related to late commit before the release and small after-commit change
request
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209305
Commit: 0dccfdc051a5865f4f0ef0e988084e70d317727e
https://github.com/llvm/llvm-project/commit/0dccfdc051a5865f4f0ef0e988084e70d317727e
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/Driver/SanitizerArgs.cpp
Log Message:
-----------
[clang][Driver] Remove duplicate KernelAddress sanitizer kind. NFC. (#209079)
Remove the duplicate `SanitizerKind::KernelAddress` entry from the list
of sanitizers incompatible with `TypeSanitizer`.
Found using clang-tidy, with check `misc-redundant-expression`
Commit: d3f58ce0cc1c3533a3085671978ded2e0e867e16
https://github.com/llvm/llvm-project/commit/d3f58ce0cc1c3533a3085671978ded2e0e867e16
Author: jeanPerier <jperier at nvidia.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCTypeInterfaces.cpp
Log Message:
-----------
[flang][openacc][NFC] remove useAccReductionCombine cl switch (#208756)
Follow-up of https://github.com/llvm/llvm-project/pull/208473 to remove
the switch altogether to simplify the compiler code.
Commit: 8c9a6fd876677a69b3a08ce8d868f21730dd6915
https://github.com/llvm/llvm-project/commit/8c9a6fd876677a69b3a08ce8d868f21730dd6915
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDowngrade1p1To1p0.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Tosa/Utils/QuantUtils.cpp
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-downgrade-1-1-to-1-0.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
Log Message:
-----------
[mlir][tosa] Add support for block scaled types in matmul_t (#207851)
Builds on https://github.com/llvm/llvm-project/pull/203894 to enable
MXFP block scaled fotmats within matmul_t.
Commit: 5b3b76e77386b6e91c7627edb3beab64077e379f
https://github.com/llvm/llvm-project/commit/5b3b76e77386b6e91c7627edb3beab64077e379f
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M libcxx/docs/ReleaseNotes.rst
A libcxx/docs/ReleaseNotes/24.rst
Log Message:
-----------
[libc++] Create libc++ 24 release notes (#208814)
Now that the LLVM 23 branch has been created, this adds LLVM 24 release
notes. The release notes contain a few TODOs which will be easy to
address in separate PRs.
Commit: eb2163a5d116a2834844b035684a43c8ee765fc1
https://github.com/llvm/llvm-project/commit/eb2163a5d116a2834844b035684a43c8ee765fc1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/wqm.mir
M llvm/test/CodeGen/AMDGPU/write-register-invalid-register.ll
M llvm/test/CodeGen/AMDGPU/write-register-vgpr-into-sgpr.ll
M llvm/test/CodeGen/AMDGPU/write_register.ll
M llvm/test/CodeGen/AMDGPU/wwm-reg-shift-down-gfx11plus.mir
M llvm/test/CodeGen/AMDGPU/wwm-regalloc-error.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/wwm-spill-superclass-pseudo.mir
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-any.ll
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-disabled.ll
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-enabled.ll
M llvm/test/CodeGen/AMDGPU/xnor.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/xor3-i1-const.ll
M llvm/test/CodeGen/AMDGPU/xor3.ll
M llvm/test/CodeGen/AMDGPU/xor_add.ll
M llvm/test/CodeGen/AMDGPU/zero_extend.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (38) (#209602)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: c8c0877e60c847ec81a4e469ec25a30fcf1aa46e
https://github.com/llvm/llvm-project/commit/c8c0877e60c847ec81a4e469ec25a30fcf1aa46e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-prelegalizer-combiner-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/and.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-concat-vectors.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-cse-leaves-dead-cast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_store_local.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-add-sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-and.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-xchg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-xor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_minmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/br-constant-invalid-sgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/bug_shuffle_vector_to_scalar.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-to-ptradd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fdiv-sqrt-to-rsq.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-pre-legalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fpneg-one-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-s64-s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-trunc-sextinreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.prelegal.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-urem-pow-2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-zext-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combiner-crash.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/compute-num-sign-bits-med3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (39) (#209729)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping
the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: f10eda428d5c4d21e57b5809805a5554922f851d
https://github.com/llvm/llvm-project/commit/f10eda428d5c4d21e57b5809805a5554922f851d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/test/Driver/clang-offload-bundler-multi-compress.c
M clang/test/OffloadTools/clang-offload-bundler/asserts-on.c
M clang/test/OffloadTools/clang-offload-bundler/basic.c
M clang/test/OffloadTools/clang-offload-bundler/fat-archive-unbundle-ext.c
M clang/test/OffloadTools/clang-offload-bundler/standardize.c
M clang/test/OffloadTools/clang-offload-bundler/zlib.c
M clang/test/OffloadTools/clang-offload-bundler/zstd.c
Log Message:
-----------
clang-offload-bundler: Fix host dependency of tests (#209720)
Use an explicit linux triple for the host target instead of using the
default/host target and marking most every other system as unsupported.
Fixes not running these tests on macos.
Co-authored-by: Claude (Opus 4.8)
Commit: e41f5aa4d656ed16b8f9890ee7f30fb1845d4a03
https://github.com/llvm/llvm-project/commit/e41f5aa4d656ed16b8f9890ee7f30fb1845d4a03
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/runtimes/CMakeLists.txt
Log Message:
-----------
[runtimes] Add explicit offload arch tool dependencies (#206076)
Needed for the offload unittests which detect the target arch at
configure time if not forced by OFFLOAD_TESTS_FORCE_AMDGPU_ARCH. Bug had
been masked by the dependency on flang, which we recently removed in
https://github.com/llvm/llvm-project/pull/198205.
Claude assisted with this patch.
Commit: 1980283edd2155bb058b58fbc97fb02d3e78c301
https://github.com/llvm/llvm-project/commit/1980283edd2155bb058b58fbc97fb02d3e78c301
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.v2i65.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value-addrspaces.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.illegal.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/hip.extern.shared.array.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/i1-copy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/icmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.i16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.u16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.i16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.u16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ds.swizzle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.groupstaticsize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mbcnt.lo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mulhi.i24.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mulhi.u24.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (40) (#209730)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: f48200029bf6277d4fe3915b480a5c87c8f172c9
https://github.com/llvm/llvm-project/commit/f48200029bf6277d4fe3915b480a5c87c8f172c9
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
M clang/test/Driver/print-enabled-extensions/aarch64-ampere1c.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-m5.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.7-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.8-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.9-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.2-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.3-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.4-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.5-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
M clang/test/Driver/print-enabled-extensions/aarch64-c1-premium.c
M clang/test/Driver/print-enabled-extensions/aarch64-c1-pro.c
M clang/test/Driver/print-enabled-extensions/aarch64-c1-ultra.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a320.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720ae.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a725.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-x4.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-x925.c
M clang/test/Driver/print-enabled-extensions/aarch64-fujitsu-monaka.c
M clang/test/Driver/print-enabled-extensions/aarch64-gb10.c
M clang/test/Driver/print-enabled-extensions/aarch64-hip12.c
M clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n3.c
M clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3.c
M clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3ae.c
M clang/test/Driver/print-enabled-extensions/aarch64-olympus.c
M clang/test/Driver/print-enabled-extensions/aarch64-rigel.c
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64Processors.td
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/test/MC/AArch64/armv8.7a-hcx.s
M llvm/test/MC/Disassembler/AArch64/armv8.7a-hcx.txt
Log Message:
-----------
[AArch64] Remove HCX feature flag from backend (#209477)
This patch removes +hcx option from the llvm and removes guarding of
HCRX_EL2 system register on it.
Commit: cceae35fc91ad84baaa046e65961bd49de89a6e6
https://github.com/llvm/llvm-project/commit/cceae35fc91ad84baaa046e65961bd49de89a6e6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.readfirstlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.reloc.constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sffbh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-wave-address.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-region.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-region.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-region.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus-fake16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fconstant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-i1-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-old-legalization.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.s96.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (41) (#209731)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 52eb0512237be5b1a58a82cad84caaddab4e04aa
https://github.com/llvm/llvm-project/commit/52eb0512237be5b1a58a82cad84caaddab4e04aa
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
A clang/test/Driver/openmp-invalid-target-id.c
Log Message:
-----------
clang: Add OpenMP driver test for invalid target IDs (#209740)
Submit test that already exists in the rocm fork. This stresses
the error cases when using the legacy OpenMP -march target specifier,
which appears to be missing upstream.
Commit: 9744b475e28e180599fd1a42d956f74b0a1aaed8
https://github.com/llvm/llvm-project/commit/9744b475e28e180599fd1a42d956f74b0a1aaed8
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
Log Message:
-----------
[CIR][AMDGPU] Add support for AMDGCN rsq and rsq_clamp builtins (#197349)
Adds codegen for the following AMDGCN reciprocal square root builtins:
- __builtin_amdgcn_rsq (double)
- __builtin_amdgcn_rsqf (float)
- __builtin_amdgcn_rsqh (half)
- __builtin_amdgcn_rsq_bf16 (bfloat16)
- __builtin_amdgcn_rsq_clamp (double)
- __builtin_amdgcn_rsq_clampf (float)
These are lowered to the corresponding `llvm.amdgcn.rsq` and
`llvm.amdgcn.rsq.clamp` intrinsic calls.
Commit: 567c6a7589fe9f29882d60ac2ddedc2f33bd80c1
https://github.com/llvm/llvm-project/commit/567c6a7589fe9f29882d60ac2ddedc2f33bd80c1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pseudo-scalar-transcendental.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-returnaddress.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sopc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-packed.xfail.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sextload-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax-64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin-64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.invalid.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.gfx10.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax-64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin-64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.gfx10.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zextload-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fast-math-flags.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-metadata.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/known-bits-sbfe.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/known-fpclass-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-relocs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if-invalid.mir
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (42) (#209732)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 2746fc6981516c9e26dbdaa7ba254279d391b534
https://github.com/llvm/llvm-project/commit/2746fc6981516c9e26dbdaa7ba254279d391b534
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if.xfail.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.rsq.clamp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.workitem.id.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg-with-success.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-max.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-min.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-splat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctls.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-divrem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp-s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fconstant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaximum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminimum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
Log Message:
-----------
AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (43) (#209733)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 42605e7b341ccbc6b2486e2ced82386f099c476a
https://github.com/llvm/llvm-project/commit/42605e7b341ccbc6b2486e2ced82386f099c476a
Author: ioana ghiban <ioana.ghiban at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/lib/Dialect/MemRef/Transforms/ElideReinterpretCast.cpp
M mlir/test/Dialect/MemRef/elide-reinterpret-cast.mlir
Log Message:
-----------
[mlir][memref] Support truncating copied dims to non-unit in reinterpret_cast elision (#209536)
Relax the `memref.copy`through `memref.reinterpret_cast` rewrite to
support same-dimension slices where strictly one non-unit source
dimension size is truncated to a smaller non-unit result dimension.
Previously, the rewrite only supported truncating to unit size:
```mlir
memref<1xMxNxf32>
to memref<1xMx1xf32, strided<[M*N, N, 1], offset: OFF>>
```
This change relaxes constraints to also support:
```mlir
memref<1xMxNxf32>
to memref<1xMxKxf32, strided<[M*N, N, 1], offset: OFF>>
```
where `K < N`.
The rewrite remains conservative:
* source must have identity layout,
* result strides must match the source identity strides,
* offset must be static for non-scalar results, and
* copied slice must be in bounds.
Assisted-by: Codex (refine PR description).
Commit: 0350a23a8bbc091e646406a2aaeafa35dc0216d3
https://github.com/llvm/llvm-project/commit/0350a23a8bbc091e646406a2aaeafa35dc0216d3
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt-c/WrapperFunction.h
M orc-rt/test/unit/WrapperFunctionBufferTest.cpp
Log Message:
-----------
[orc-rt] Fix WrapperFunctionBuffer empty range construction (#209751)
orc_rt_CreateWrapperFunctionBufferFromRange(const char *, size_t) left
the constructed buffer's data member uninitialized when the size
argument was zero. This could result in the returned buffer having a
non-null data field and a zero size field, which is a (malformed)
out-of-band error value, not an empty buffer.
Update orc_rt_CreateWrapperFunctionBufferFromRange to zero-initialize
the data field so that the size == 0 case yields a correctly formed
empty buffer.
Commit: 653c1dab3774d0cf02bb9fc8c469bbd356aff885
https://github.com/llvm/llvm-project/commit/653c1dab3774d0cf02bb9fc8c469bbd356aff885
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll
M llvm/test/CodeGen/X86/x86-interleaved-access.ll
Log Message:
-----------
[X86] combineINSERT_SUBVECTOR - enable shuffle combining of insertsub(extractsub(shuffle),extractsub(shuffle)) patterns (#209735)
Allows combineX86ShuffleChainWithExtract to more consistently fold
patterns from wider sources
Commit: 4b66bacd1fdf02803509b744034f3ab09945157c
https://github.com/llvm/llvm-project/commit/4b66bacd1fdf02803509b744034f3ab09945157c
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/APValue.h
M clang/include/clang/AST/PropertiesBase.td
M clang/lib/AST/APValue.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/EvaluationResult.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Record.cpp
M clang/lib/AST/ByteCode/Record.h
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/CodeGen/CGExprConstant.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaType.cpp
A clang/test/AST/ByteCode/virtual-bases-codegen.cpp
A clang/test/AST/ByteCode/virtual-bases.cpp
M clang/test/CXX/drs/cwg16xx.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg6xx.cpp
M clang/www/cxx_status.html
Log Message:
-----------
[clang][ExprConst] Support virtual bases in C++26 (#204289)
Add support for virtual bases in constant expressions (P3533R2) to both the current constant interpreter as well as the bytecode interpreter.
Commit: 706db1e0959f45d6392edd2ad196a4ea38bb99d3
https://github.com/llvm/llvm-project/commit/706db1e0959f45d6392edd2ad196a4ea38bb99d3
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
Log Message:
-----------
[mlir][tosa] Add support for MXFP row_gather (#207933)
Adds profile compliance support for MXFP row_gather.
Commit: 4584a6489341b4fe7762991e65f98467ffe4c699
https://github.com/llvm/llvm-project/commit/4584a6489341b4fe7762991e65f98467ffe4c699
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.cpp
Log Message:
-----------
[lldb][AArch64][NFC] Make watchpoint adjustment more clear (#209483)
NativeRegisterContextDBReg_arm64::AdjustWatchpoint has a way of
adjusting the range of a watchpoint but it took me a while to figure out
how it worked. I've rewritten it in a way I think is easier to follow,
with more explanatory comments.
It turns out that this adjustment results in us only using a subset of
what the hardware allows.
* You don't have to select a continuous range of bytes (1, 2, 3). You
can select (1, 4) for example.
* The address can be 4 byte aligned, in which case only 4 bits of the
byte select apply (though you can set up an equivalent watch with 8 byte
alignment and a different 8 bit BAS value).
Commit: 2c978fa06d19095c0003508b8dac084689b12e78
https://github.com/llvm/llvm-project/commit/2c978fa06d19095c0003508b8dac084689b12e78
Author: Caroline Newcombe <caroline.newcombe at hpe.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M flang/lib/Lower/Support/Utils.cpp
M flang/test/Integration/OpenMP/copyprivate.f90
M flang/test/Integration/OpenMP/private-global.f90
M flang/test/Lower/OpenMP/DelayedPrivatization/target-teams-distribute-private-adjustable-array.f90
M flang/test/Lower/OpenMP/copyprivate.f90
M flang/test/Lower/OpenMP/delayed-privatization-array.f90
M flang/test/Lower/OpenMP/lastprivate-equivalence.f90
M flang/test/Lower/OpenMP/loop-directive.f90
M flang/test/Lower/OpenMP/parallel-private-clause.f90
A flang/test/Lower/OpenMP/private-array-boxing.f90
M flang/test/Lower/OpenMP/private-commonblock.f90
M flang/test/Lower/do_concurrent_local_assoc_entity.f90
Log Message:
-----------
[flang][OpenMP] Avoid boxing constant-size trivial private arrays (#208315)
Part of #208086. `privatizeSymbol` (used for both OpenMP privatization
and `do concurrent` locals) currently boxes every array as a workaround
for `fir.array` not being directly `alloca`-able in the OpenMP→LLVMIR
translation. This PR carves out the common case: a constant-shape array
of trivial intrinsic elements (e.g. `real(8) :: xx(3)`) is now
privatized unboxed, as a plain `fir.array`.
Commit: 2975dac23e684748ae1051e6c1112aa53d7aea2c
https://github.com/llvm/llvm-project/commit/2975dac23e684748ae1051e6c1112aa53d7aea2c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M lldb/test/Shell/helper/toolchain.py
M lldb/test/Shell/lit.cfg.py
Log Message:
-----------
[lldb] Drop support for using the external shell
The lit external shell is going to be removed soon, so drop support for
using it to run the LLDB tests.
Reviewers: DavidSpickett, JDevlieghere, petrhosek, ilovepi
Pull Request: https://github.com/llvm/llvm-project/pull/209627
Commit: d9d8502ecaa9a5b8dc59fe010c13d0780fac22ea
https://github.com/llvm/llvm-project/commit/d9d8502ecaa9a5b8dc59fe010c13d0780fac22ea
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-15 (Wed, 15 Jul 2026)
Changed paths:
M clang-tools-extra/clangd/ConfigYAML.cpp
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/APValue.h
M clang/include/clang/AST/PropertiesBase.td
M clang/include/clang/Options/Options.td
M clang/lib/AST/APValue.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/EvaluationResult.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ByteCode/Record.cpp
M clang/lib/AST/ByteCode/Record.h
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/lib/CodeGen/CGExprConstant.cpp
M clang/lib/Driver/OffloadBundler.cpp
M clang/lib/Driver/SanitizerArgs.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/SemaAMDGPU.cpp
M clang/lib/Sema/SemaBoundsSafety.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/StaticAnalyzer/Checkers/DeadStoresChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/UndefinedAssignmentChecker.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineC.cpp
M clang/test/AST/ByteCode/cxx11.cpp
M clang/test/AST/ByteCode/cxx2a.cpp
M clang/test/AST/ByteCode/unions.cpp
A clang/test/AST/ByteCode/virtual-bases-codegen.cpp
A clang/test/AST/ByteCode/virtual-bases.cpp
A clang/test/Analysis/issue-173210-self-assign-init.c
M clang/test/Analysis/operator-calls.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
M clang/test/CXX/drs/cwg16xx.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg6xx.cpp
M clang/test/CodeGenOpenCL/builtins-f16.cl
M clang/test/Driver/clang-offload-bundler-multi-compress.c
M clang/test/Driver/dxc_debug.hlsl
A clang/test/Driver/openmp-invalid-target-id.c
M clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
M clang/test/Driver/print-enabled-extensions/aarch64-ampere1c.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-m5.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.7-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.8-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.9-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.2-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.3-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.4-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.5-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
M clang/test/Driver/print-enabled-extensions/aarch64-c1-premium.c
M clang/test/Driver/print-enabled-extensions/aarch64-c1-pro.c
M clang/test/Driver/print-enabled-extensions/aarch64-c1-ultra.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a320.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720ae.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a725.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-x4.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-x925.c
M clang/test/Driver/print-enabled-extensions/aarch64-fujitsu-monaka.c
M clang/test/Driver/print-enabled-extensions/aarch64-gb10.c
M clang/test/Driver/print-enabled-extensions/aarch64-hip12.c
M clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n3.c
M clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3.c
M clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3ae.c
M clang/test/Driver/print-enabled-extensions/aarch64-olympus.c
M clang/test/Driver/print-enabled-extensions/aarch64-rigel.c
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
M clang/test/OffloadTools/clang-offload-bundler/asserts-on.c
M clang/test/OffloadTools/clang-offload-bundler/basic.c
M clang/test/OffloadTools/clang-offload-bundler/fat-archive-unbundle-ext.c
M clang/test/OffloadTools/clang-offload-bundler/standardize.c
M clang/test/OffloadTools/clang-offload-bundler/zlib.c
M clang/test/OffloadTools/clang-offload-bundler/zstd.c
M clang/test/Sema/LifetimeSafety/dangling-field.cpp
M clang/test/Sema/attr-sized-by-late-parsed-struct-ptrs.c
M clang/test/Sema/attr-sized-by-or-null-late-parsed-struct-ptrs.c
M clang/test/Sema/attr-sized-by-or-null-struct-ptrs.c
M clang/test/Sema/attr-sized-by-struct-ptrs.c
M clang/test/SemaCXX/constant-expression-cxx2a.cpp
M clang/test/SemaCXX/constexpr-late-instantiation.cpp
M clang/test/SemaCXX/cxx2b-deducing-this.cpp
A clang/test/SemaOpenCL/builtins-amdgcn-cmp-deprecated.cl
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/www/cxx_status.html
M flang/include/flang/Optimizer/Analysis/ArraySectionAnalyzer.h
M flang/include/flang/Optimizer/Builder/FIRBuilder.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/Support/Utils.cpp
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCTypeInterfaces.cpp
A flang/test/HLFIR/inline-hlfir-assign-pointer-overlap.fir
A flang/test/HLFIR/inline-hlfir-assign-scalar-index.fir
A flang/test/HLFIR/inline-hlfir-assign-self-copy-runtime-stride.fir
A flang/test/HLFIR/inline-hlfir-assign-self-copy.fir
M flang/test/Integration/OpenMP/copyprivate.f90
M flang/test/Integration/OpenMP/private-global.f90
A flang/test/Integration/OpenMP/target-inreduction-llvmir.f90
M flang/test/Lower/OpenMP/DelayedPrivatization/target-teams-distribute-private-adjustable-array.f90
A flang/test/Lower/OpenMP/Todo/target-inreduction-common.f90
A flang/test/Lower/OpenMP/Todo/target-inreduction-equivalence.f90
A flang/test/Lower/OpenMP/Todo/target-inreduction-firstprivate.f90
R flang/test/Lower/OpenMP/Todo/target-inreduction.f90
M flang/test/Lower/OpenMP/copyprivate.f90
M flang/test/Lower/OpenMP/delayed-privatization-array.f90
M flang/test/Lower/OpenMP/lastprivate-equivalence.f90
M flang/test/Lower/OpenMP/loop-directive.f90
M flang/test/Lower/OpenMP/parallel-private-clause.f90
A flang/test/Lower/OpenMP/private-array-boxing.f90
M flang/test/Lower/OpenMP/private-commonblock.f90
A flang/test/Lower/OpenMP/target-inreduction-unused.f90
A flang/test/Lower/OpenMP/target-inreduction.f90
M flang/test/Lower/do_concurrent_local_assoc_entity.f90
A flang/test/Lower/inline-hlfir-assign-forall-threadprivate.f90
A flang/test/Lower/inline-hlfir-assign-pointer-omp.f90
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/arpa/inet.yaml
M libc/src/__support/File/linux/CMakeLists.txt
M libc/src/__support/File/linux/file.cpp
M libc/src/__support/StringUtil/CMakeLists.txt
M libc/src/__support/StringUtil/signal_to_string.cpp
M libc/src/__support/StringUtil/tables/CMakeLists.txt
M libc/src/__support/StringUtil/tables/linux_extension_signals.h
M libc/src/__support/StringUtil/tables/posix_signals.h
M libc/src/__support/StringUtil/tables/stdc_signals.h
M libc/src/arpa/inet/CMakeLists.txt
A libc/src/arpa/inet/inet_ntoa.cpp
A libc/src/arpa/inet/inet_ntoa.h
M libc/src/pthread/CMakeLists.txt
M libc/src/pthread/pthread_condattr_getclock.cpp
M libc/src/pthread/pthread_condattr_getclock.h
M libc/src/pthread/pthread_condattr_setclock.cpp
M libc/src/pthread/pthread_condattr_setclock.h
M libc/src/signal/kill.h
M libc/src/signal/linux/CMakeLists.txt
M libc/src/signal/linux/kill.cpp
M libc/src/signal/linux/sigemptyset.cpp
M libc/src/signal/raise.h
M libc/src/spawn/linux/CMakeLists.txt
M libc/src/spawn/linux/posix_spawn.cpp
M libc/src/sys/prctl/linux/CMakeLists.txt
M libc/src/sys/prctl/prctl.h
M libc/src/sys/random/getrandom.h
M libc/src/sys/random/linux/CMakeLists.txt
M libc/src/sys/resource/getrlimit.h
M libc/src/sys/resource/linux/CMakeLists.txt
M libc/src/sys/resource/setrlimit.h
M libc/src/sys/sendfile/linux/CMakeLists.txt
M libc/src/sys/sendfile/linux/sendfile.cpp
M libc/src/sys/sendfile/sendfile.h
M libc/src/sys/socket/linux/CMakeLists.txt
M libc/src/sys/socket/recv.h
M libc/src/sys/socket/send.h
M libc/src/sys/wait/linux/CMakeLists.txt
M libc/src/sys/wait/wait.h
M libc/src/sys/wait/wait4Impl.h
M libc/src/sys/wait/waitpid.h
M libc/src/unistd/linux/CMakeLists.txt
M libc/src/unistd/linux/fork.cpp
M libc/src/unistd/linux/isatty.cpp
M libc/startup/linux/CMakeLists.txt
M libc/startup/linux/do_start.cpp
M libc/test/UnitTest/CMakeLists.txt
A libc/test/UnitTest/ConstraintHandlerCheckingTest.h
M libc/test/integration/src/sys/ptrace/linux/ptrace_test.cpp
M libc/test/src/arpa/inet/CMakeLists.txt
A libc/test/src/arpa/inet/inet_ntoa_test.cpp
M libc/test/src/fcntl/CMakeLists.txt
M libc/test/src/fcntl/creat_test.cpp
M libc/test/src/fcntl/fcntl_test.cpp
M libc/test/src/fenv/enabled_exceptions_test.cpp
M libc/test/src/signal/kill_test.cpp
M libc/test/src/signal/pthread_sigmask_test.cpp
M libc/test/src/signal/raise_test.cpp
M libc/test/src/signal/sigaddset_test.cpp
M libc/test/src/signal/sigdelset_test.cpp
M libc/test/src/signal/sigfillset_test.cpp
M libc/test/src/signal/signal_test.cpp
M libc/test/src/signal/sigprocmask_test.cpp
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/fdopen_test.cpp
M libc/test/src/stdlib/abort_test.cpp
M libc/test/src/string/memory_utils/protected_pages.h
M libc/test/src/string/strsignal_test.cpp
M libc/test/src/sys/auxv/linux/CMakeLists.txt
M libc/test/src/sys/auxv/linux/getauxval_test.cpp
M libc/test/src/sys/mman/linux/CMakeLists.txt
M libc/test/src/sys/mman/linux/mlock_test.cpp
M libc/test/src/sys/mman/linux/mprotect_test.cpp
M libc/test/src/sys/mman/linux/posix_madvise_test.cpp
M libc/test/src/sys/mman/linux/remap_file_pages_test.cpp
M libc/test/src/sys/resource/CMakeLists.txt
M libc/test/src/sys/resource/getrlimit_setrlimit_test.cpp
M libc/test/src/sys/sendfile/CMakeLists.txt
M libc/test/src/sys/sendfile/sendfile_test.cpp
M libc/test/src/sys/socket/linux/CMakeLists.txt
M libc/test/src/sys/socket/linux/sendto_recvfrom_test.cpp
M libc/test/src/sys/socket/linux/socket_test.cpp
M libc/test/src/sys/socket/linux/socketopt_test.cpp
M libc/test/src/sys/socket/linux/socketpair_test.cpp
M libc/test/src/sys/stat/CMakeLists.txt
M libc/test/src/sys/stat/chmod_test.cpp
M libc/test/src/sys/stat/fchmod_test.cpp
M libc/test/src/sys/stat/fchmodat_test.cpp
M libc/test/src/sys/stat/fstat_test.cpp
M libc/test/src/sys/stat/lstat_test.cpp
M libc/test/src/sys/stat/stat_test.cpp
M libc/test/src/unistd/CMakeLists.txt
M libc/test/src/unistd/access_test.cpp
M libc/test/src/unistd/chown_test.cpp
M libc/test/src/unistd/dup2_test.cpp
M libc/test/src/unistd/dup3_test.cpp
M libc/test/src/unistd/dup_test.cpp
M libc/test/src/unistd/faccessat_test.cpp
M libc/test/src/unistd/fchown_test.cpp
M libc/test/src/unistd/ftruncate_test.cpp
M libc/test/src/unistd/isatty_test.cpp
M libc/test/src/unistd/link_test.cpp
M libc/test/src/unistd/linkat_test.cpp
M libc/test/src/unistd/pread_pwrite_test.cpp
M libc/test/src/unistd/read_write_test.cpp
M libc/test/src/unistd/symlink_test.cpp
M libc/test/src/unistd/symlinkat_test.cpp
M libc/test/src/unistd/syscall_test.cpp
M libc/test/src/unistd/truncate_test.cpp
M libc/test/src/unistd/unlink_test.cpp
M libc/test/src/unistd/unlinkat_test.cpp
M libcxx/docs/ReleaseNotes.rst
A libcxx/docs/ReleaseNotes/24.rst
M libsycl/docs/index.rst
R libsycl/include/sycl/__impl/detail/default_async_handler.hpp
M libsycl/include/sycl/__impl/event.hpp
M libsycl/include/sycl/__impl/exception.hpp
A libsycl/include/sycl/__impl/info/event.hpp
M libsycl/include/sycl/__impl/queue.hpp
M libsycl/src/detail/event_impl.cpp
M libsycl/src/detail/event_impl.hpp
M libsycl/src/detail/global_objects.cpp
M libsycl/src/detail/global_objects.hpp
M libsycl/src/detail/queue_impl.cpp
M libsycl/src/detail/queue_impl.hpp
A libsycl/src/detail/spinlock.hpp
M libsycl/src/event.cpp
M libsycl/src/exception_list.cpp
M libsycl/src/queue.cpp
M libsycl/unittests/CMakeLists.txt
M libsycl/unittests/common/device_images.hpp
A libsycl/unittests/common/scoped_binary_registration.hpp
M libsycl/unittests/common/unittests_helper.hpp
M libsycl/unittests/device_selector/get_device_preference.cpp
A libsycl/unittests/event/CMakeLists.txt
A libsycl/unittests/event/async_handler.cpp
A libsycl/unittests/event/event.cpp
M libsycl/unittests/mock/helpers.cpp
M libsycl/unittests/mock/helpers.hpp
M libsycl/unittests/mock/mock.cpp
M libsycl/unittests/program_manager/register_and_unregister.cpp
M libsycl/unittests/queue/sycl_kernel_launch.cpp
M lldb/include/lldb/Target/MemoryRegionInfo.h
M lldb/include/lldb/Target/StackID.h
M lldb/include/lldb/Utility/Log.h
M lldb/source/Commands/CommandObjectLog.cpp
M lldb/source/Plugins/Platform/POSIX/PlatformPOSIX.cpp
M lldb/source/Plugins/Process/Utility/LinuxProcMaps.cpp
M lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
M lldb/source/Target/StackFrameList.cpp
M lldb/source/Target/StackID.cpp
M lldb/source/Target/ThreadPlanStepInstruction.cpp
M lldb/source/Target/ThreadPlanStepOut.cpp
M lldb/source/Target/ThreadPlanStepRange.cpp
M lldb/source/Target/ThreadPlanStepUntil.cpp
M lldb/source/Utility/Log.cpp
M lldb/test/API/python_api/sbplatform/TestSBPlatform.py
M lldb/unittests/Process/Utility/LinuxProcMapsTest.cpp
M lldb/unittests/Utility/LogTest.cpp
M llvm/docs/QualGroup.rst
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/GenericCycleInfo.h
M llvm/include/llvm/CodeGen/GlobalISel/Combiner.h
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/include/llvm/Object/OffloadBinary.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/lib/CodeGen/GlobalISel/Combiner.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/Object/OffloadBinary.cpp
M llvm/lib/Support/raw_ostream.cpp
M llvm/lib/TableGen/TGParser.cpp
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64Processors.td
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/DirectX/DXContainerGlobals.cpp
M llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
M llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
M llvm/lib/Target/README.txt
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86LowerTileCopy.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/runtimes/CMakeLists.txt
M llvm/test/CodeGen/AArch64/scalable_masked_interleaved_stores.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-prelegalizer-combiner-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/and.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-concat-vectors.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-cse-leaves-dead-cast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_store_local.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-add-sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-and.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-xchg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-xor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_minmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/br-constant-invalid-sgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/bug_shuffle_vector_to_scalar.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-to-ptradd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fdiv-sqrt-to-rsq.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-pre-legalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fpneg-one-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-s64-s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-trunc-sextinreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.prelegal.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-urem-pow-2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-zext-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combiner-crash.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/compute-num-sign-bits-med3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.v2i65.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value-addrspaces.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.illegal.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/hip.extern.shared.array.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/i1-copy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/icmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.i16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.u16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.i16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.u16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ds.swizzle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.groupstaticsize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mbcnt.lo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mulhi.i24.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mulhi.u24.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.readfirstlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.reloc.constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sffbh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-wave-address.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-region.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-region.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-region.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-poison.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
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M llvm/test/CodeGen/AMDGPU/verify-gfx12-gds.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/verify-image-vaddr-align.mir
M llvm/test/CodeGen/AMDGPU/verify-image.mir
M llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir
M llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd.mir
M llvm/test/CodeGen/AMDGPU/vgpr-agpr-limit-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
M llvm/test/CodeGen/AMDGPU/vgpr-excess-threshold-percent-invalid.ll
M llvm/test/CodeGen/AMDGPU/vgpr-excess-threshold-percent.ll
M llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
M llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250-t16.mir
M llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.mir
M llvm/test/CodeGen/AMDGPU/vgpr-remat-v_pk_mov_b32.mir
M llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
M llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir
M llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill-dead-frame-in-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
M llvm/test/CodeGen/AMDGPU/vi-removed-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/visit-physreg-vgpr-imm-folding-bug.ll
M llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
M llvm/test/CodeGen/AMDGPU/vmem-vcc-hazard.mir
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vop-shrink.ll
M llvm/test/CodeGen/AMDGPU/vopc-remat.mir
M llvm/test/CodeGen/AMDGPU/vopc_dpp-true16.mir
M llvm/test/CodeGen/AMDGPU/vopc_dpp.ll
M llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
M llvm/test/CodeGen/AMDGPU/vopd-combine-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/vopd-combine.mir
M llvm/test/CodeGen/AMDGPU/vopd-gfx12-f64-relaxed.mir
M llvm/test/CodeGen/AMDGPU/vopd-src2acc-delay.mir
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.mir
M llvm/test/CodeGen/AMDGPU/wait-xcnt-atomic-rmw-optimization.ll
M llvm/test/CodeGen/AMDGPU/wait-xcnt-drain.mir
M llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
M llvm/test/CodeGen/AMDGPU/wait.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-agpr.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-debug-output-crash.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-flat.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-func-global-inv.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-global-inv-wb.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-kmcnt-scc-different-block.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-flushed.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-flushed.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-pattern.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-store-barrier.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-irreducible.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-opt.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-single-basic-block.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-looptest.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-meta-instructions.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-multiple-funcs.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-overflow.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-permute.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting-vscnt.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-sample-out-order.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-sample-waw.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-skip-meta.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-unscoped.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-vinterp.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-vmcnt-loop.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-vmem-waw.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-wbl2.ll
M llvm/test/CodeGen/AMDGPU/waitcnt.mir
M llvm/test/CodeGen/AMDGPU/waterfall-call-inreg-agpr.ll
M llvm/test/CodeGen/AMDGPU/waterfall-call-inreg-agpr.mir
M llvm/test/CodeGen/AMDGPU/waterfall-call-target-av-register-failure.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
M llvm/test/CodeGen/AMDGPU/while-break.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/widen_extending_scalar_loads.ll
M llvm/test/CodeGen/AMDGPU/wmma-coexecution-valu-hazards.mir
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx12-w32.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx12-w64.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1251-w32.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards.mir
M llvm/test/CodeGen/AMDGPU/wmma-nop-hoisting.mir
M llvm/test/CodeGen/AMDGPU/wmma_modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_32.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_64.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
M llvm/test/CodeGen/AMDGPU/wqm-debug-instr-terminator.mir
M llvm/test/CodeGen/AMDGPU/wqm-gfx11.ll
M llvm/test/CodeGen/AMDGPU/wqm-propagate-for-execz-side-effect.mir
M llvm/test/CodeGen/AMDGPU/wqm-terminators.mir
M llvm/test/CodeGen/AMDGPU/wqm.ll
M llvm/test/CodeGen/AMDGPU/wqm.mir
M llvm/test/CodeGen/AMDGPU/write-register-invalid-register.ll
M llvm/test/CodeGen/AMDGPU/write-register-vgpr-into-sgpr.ll
M llvm/test/CodeGen/AMDGPU/write_register.ll
M llvm/test/CodeGen/AMDGPU/wwm-reg-shift-down-gfx11plus.mir
M llvm/test/CodeGen/AMDGPU/wwm-regalloc-error.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/wwm-spill-superclass-pseudo.mir
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-any.ll
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-disabled.ll
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-enabled.ll
M llvm/test/CodeGen/AMDGPU/xnor.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/xor3-i1-const.ll
M llvm/test/CodeGen/AMDGPU/xor3.ll
M llvm/test/CodeGen/AMDGPU/xor_add.ll
M llvm/test/CodeGen/AMDGPU/zero_extend.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
A llvm/test/CodeGen/DirectX/ContainerData/SourceInfo-Strip.ll
M llvm/test/CodeGen/DirectX/embed-ildb.ll
A llvm/test/CodeGen/RISCV/rvp-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/vk-ext-builtin-input.ll
M llvm/test/CodeGen/SPIRV/passes/SPIRVLegalizePointerCast.ll
A llvm/test/CodeGen/X86/AMX/pr209512.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
M llvm/test/CodeGen/X86/x86-interleaved-access.ll
M llvm/test/MC/AArch64/armv8.7a-hcx.s
M llvm/test/MC/Disassembler/AArch64/armv8.7a-hcx.txt
M llvm/test/MC/RISCV/corev/XCValu-invalid.s
M llvm/test/MC/RISCV/corev/XCVbi-invalid.s
M llvm/test/MC/RISCV/corev/XCVbitmanip-invalid.s
M llvm/test/MC/RISCV/corev/XCVelw-invalid.s
M llvm/test/MC/RISCV/corev/XCVmac-invalid.s
M llvm/test/MC/RISCV/corev/XCVmem-invalid.s
M llvm/test/MC/RISCV/corev/XCVsimd-invalid.s
M llvm/test/MC/RISCV/function-call-invalid.s
M llvm/test/MC/RISCV/priv-invalid.s
M llvm/test/MC/RISCV/rv32d-invalid.s
M llvm/test/MC/RISCV/rv32f-invalid.s
M llvm/test/MC/RISCV/rv32i-aliases-invalid.s
M llvm/test/MC/RISCV/rv32i-invalid.s
M llvm/test/MC/RISCV/rv32q-invalid.s
M llvm/test/MC/RISCV/rv32xqccmp-invalid.s
M llvm/test/MC/RISCV/rv32zcmp-invalid.s
M llvm/test/MC/RISCV/rv32zdinx-invalid.s
M llvm/test/MC/RISCV/rv32zfh-invalid.s
M llvm/test/MC/RISCV/rv32zhinx-invalid.s
M llvm/test/MC/RISCV/rv64d-invalid.s
M llvm/test/MC/RISCV/rv64f-invalid.s
M llvm/test/MC/RISCV/rv64i-aliases-invalid.s
M llvm/test/MC/RISCV/rv64q-invalid.s
M llvm/test/MC/RISCV/rv64xqccmp-invalid.s
M llvm/test/MC/RISCV/rv64xtheadfmemidx-invalid.s
M llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s
M llvm/test/MC/RISCV/rv64zcmp-invalid.s
M llvm/test/MC/RISCV/rv64zdinx-invalid.s
M llvm/test/MC/RISCV/rv64zfh-invalid.s
M llvm/test/MC/RISCV/rv64zfinx-invalid.s
M llvm/test/MC/RISCV/rv64zhinx-invalid.s
M llvm/test/MC/RISCV/rve-invalid.s
M llvm/test/MC/RISCV/rvzfbfmin-invalid.s
M llvm/test/MC/RISCV/rvzfhmin-invalid.s
M llvm/test/MC/RISCV/rvzicond-invalid.s
M llvm/test/MC/RISCV/tlsdesc.s
M llvm/test/MC/RISCV/xmips-invalid.s
M llvm/test/MC/RISCV/xqcibm-invalid.s
M llvm/test/MC/RISCV/xqcili-invalid.s
M llvm/test/MC/RISCV/xqcilo-invalid.s
M llvm/test/MC/RISCV/xqcisim-invalid.s
M llvm/test/MC/RISCV/xqcisls-invalid.s
M llvm/test/MC/RISCV/xtheadcondmov-invalid.s
M llvm/test/MC/RISCV/xtheadmac-invalid.s
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
M llvm/test/Transforms/ConstraintElimination/transfer-signed-facts-to-unsigned.ll
M llvm/test/Transforms/InstCombine/AMDGPU/tan.ll
M llvm/test/Transforms/InstCombine/fdiv-cos-sin.ll
M llvm/test/Transforms/InstCombine/fdiv-sin-cos.ll
M llvm/test/Transforms/InstCombine/may-alias-errno.ll
A llvm/test/Transforms/InstCombine/sincos-fpmath.ll
A llvm/test/Transforms/InstCombine/sincos.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-unroll.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
M llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
M llvm/test/lit.cfg.py
M llvm/unittests/Support/raw_ostream_test.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Dialect/Linalg/Transforms/PackAndUnpackPatterns.cpp
M mlir/lib/Dialect/MemRef/Transforms/ElideReinterpretCast.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDowngrade1p1To1p0.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Tosa/Utils/QuantUtils.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Dialect/Linalg/simplify-pack-unpack.mlir
M mlir/test/Dialect/MemRef/elide-reinterpret-cast.mlir
M mlir/test/Dialect/OpenMP/host-op-filtering.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-downgrade-1-1-to-1-0.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
A mlir/test/Target/LLVMIR/openmp-target-in-reduction-device.mlir
A mlir/test/Target/LLVMIR/openmp-target-in-reduction-multi.mlir
A mlir/test/Target/LLVMIR/openmp-target-in-reduction.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
M orc-rt/include/CMakeLists.txt
M orc-rt/include/orc-rt-c/WrapperFunction.h
M orc-rt/lib/executor/CMakeLists.txt
M orc-rt/test/unit/WrapperFunctionBufferTest.cpp
M polly/include/polly/CodeGen/LoopGenerators.h
M polly/lib/CodeGen/IslAst.cpp
M polly/lib/CodeGen/IslNodeBuilder.cpp
M polly/lib/CodeGen/LoopGenerators.cpp
M polly/test/CodeGen/Metadata/basic_vec_annotate.ll
A polly/test/CodeGen/Metadata/skip_vec_annotate_fp_dist1.ll
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/socket/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.7
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/e0f43b0b6610...d9d8502ecaa9
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