[all-commits] [llvm/llvm-project] db427e: [RFC][AMDGPU] Add BARRIER address space

[Pierre van Houtryve via All-commits]

  Branch: refs/heads/users/pierre-vh/barrier-as-impl
  Home:   https://github.com/llvm/llvm-project
  Commit: db427ea39bb08c6aeb58324ce92e6271dfde714c
      https://github.com/llvm/llvm-project/commit/db427ea39bb08c6aeb58324ce92e6271dfde714c
  Author: pvanhout <pierre.vanhoutryve at amd.com>
  Date:   2026-07-15 (Wed, 15 Jul 2026)

  Changed paths:
    M clang/lib/Basic/Targets/AMDGPU.cpp
    M clang/test/CodeGen/target-data.c
    M clang/test/CodeGenHIP/amdgpu-barrier-type.hip
    M clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl
    M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
    M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
    M lld/test/ELF/lto/amdgcn-oses.ll
    M lld/test/ELF/lto/amdgcn.ll
    M llvm/docs/AMDGPUUsage.rst
    M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
    M llvm/include/llvm/Support/AMDGPUAddrSpace.h
    M llvm/lib/Target/AMDGPU/AMDGPU.h
    M llvm/lib/Target/AMDGPU/AMDGPU.td
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULowerExecSync.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.h
    M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
    M llvm/lib/Target/AMDGPU/SIDefines.h
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/lib/TargetParser/TargetDataLayout.cpp
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/always_uniform.ll
    A llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-module-lds.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-sw-lds.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync.ll
    M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
    M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll
    M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
    M llvm/test/CodeGen/AMDGPU/attributor-noalias-addrspace.ll
    A llvm/test/CodeGen/AMDGPU/barrier-addrspace-dereference.ll
    M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-named-barrier.ll
    M llvm/test/CodeGen/AMDGPU/lds-link-time-named-barrier.ll
    A llvm/test/CodeGen/AMDGPU/null-named-barrier-gv.ll
    M llvm/test/CodeGen/AMDGPU/s-barrier-id-allocation.ll
    A llvm/test/CodeGen/AMDGPU/s-barrier-lowering-bad-absolute-symbol.ll
    A llvm/test/CodeGen/AMDGPU/s-barrier-lowering-wrong-gv-signature.ll
    M llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
    M llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
    M llvm/test/CodeGen/AMDGPU/s-barrier.ll
    M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
    M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
    M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
    M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
    M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
    M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
    M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-barriers-gfx12.mlir
    M mlir/test/Dialect/LLVMIR/rocdl.mlir
    M mlir/test/Target/LLVMIR/rocdl.mlir

  Log Message:
  -----------
  [RFC][AMDGPU] Add BARRIER address space

Add a new BARRIER address space that is used for global variables that are used to represent the barrier IDs in GFX12.5.

These barrier addresses just have values corresponding 1-1 to barrier IDs. They are still implemented on top of LDS, but the offsetting happens during an addrspacecast to generic, not whenever the barrier GV is used.

The motivation for this is to make the relation between LDS and barrier GVs explicit in the compiler. It does add a bit more complexity, but that complexity was already there, just hidden by pretending barrier GVs were actual LDS.



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