[all-commits] [llvm/llvm-project] 72a7b7: AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Wed Jul 15 04:25:41 PDT 2026 

  Branch: refs/heads/users/arsenm/llvm/amdgpu-migrate-tests-subarch-43
  Home:   https://github.com/llvm/llvm-project
  Commit: 72a7b7af9f99e6875883df01cac3ecbb9dcdaa29
      https://github.com/llvm/llvm-project/commit/72a7b7af9f99e6875883df01cac3ecbb9dcdaa29
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-15 (Wed, 15 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-store-s16-true16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptr-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrmask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sadde.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-constant-32bit.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-s16-true16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssube.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-strict_fsub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap-gfx11.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uadde.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usube.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-constant-32bit.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.frexp.mant.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll

  Log Message:
  -----------
  AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (44)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



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