[all-commits] [llvm/llvm-project] 11ebc0: [AMDGPU][GlobalISel] Select s16 G_MERGE_VALUES in...

[Keshav Vinayak Jha via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 11ebc0e6645c8c53c75bca93e9fddf0053507cc1
      https://github.com/llvm/llvm-project/commit/11ebc0e6645c8c53c75bca93e9fddf0053507cc1
  Author: Keshav Vinayak Jha <31160700+keshavvinayak01 at users.noreply.github.com>
  Date:   2026-07-15 (Wed, 15 Jul 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
    A llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/select-merge-values-build-vector-s16.mir

  Log Message:
  -----------
   [AMDGPU][GlobalISel] Select s16 G_MERGE_VALUES into wider scalars (#207999)

With real-true16 (default on `gfx11`/`gfx12`), a scalar `s16` is a
register type, so the `G_MERGE_VALUES` legality rule started accepting
scalar merges built from `s16` pieces, e.g. `s64 = G_MERGE_VALUES(4 x
s16)`. The instruction selector has no pattern for that shape. So this
aborts with `cannot select` on something like:

```mlir
define amdgpu_kernel void @k(ptr %p) {
    store i136 0, ptr %p, align 8
    ret void
}
```

Make it selectable rather than restricting legalization: Pack pairs of
`s16` with `S_PACK_LL_B32_B16` then `REG_SEQUENCE`.

Assisted-by: Claude

Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>



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