[all-commits] [llvm/llvm-project] e824f1: [RISCV] Rename VLSU_MEM_LATENCY to Andes45VLSU_MEM...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e824f1ab372f09e4e9dbae9a19cd9245772b381c
      https://github.com/llvm/llvm-project/commit/e824f1ab372f09e4e9dbae9a19cd9245772b381c
  Author: Jim Lin <jim at andestech.com>
  Date:   2026-07-15 (Wed, 15 Jul 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedAndes45.td

  Log Message:
  -----------
  [RISCV] Rename VLSU_MEM_LATENCY to Andes45VLSU_MEM_LATENCY in RISCVSchedAndes45.td (#209388)

Prefix the defvar with the Andes45 scheduler name to match the other
Andes45-local defvars (e.g. Andes45DLEN) and avoid a bare, generic name
in the shared RISC-V TableGen namespace.

Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>



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