[all-commits] [llvm/llvm-project] c5022b: [SystemZ] Add support for strict_pseudo_fmin/fmax ...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Tue Jul 14 13:57:54 PDT 2026
Branch: refs/heads/users/alexey-bataev/spr/slpadd-umaxuminsmaxsmin-as-main-opcodes-for-copyables
Home: https://github.com/llvm/llvm-project
Commit: c5022b53e409f68de0a21039f536d0119bb666c9
https://github.com/llvm/llvm-project/commit/c5022b53e409f68de0a21039f536d0119bb666c9
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZInstrVector.td
A llvm/test/CodeGen/SystemZ/vec-strict-pseudo-max.ll
A llvm/test/CodeGen/SystemZ/vec-strict-pseudo-min.ll
Log Message:
-----------
[SystemZ] Add support for strict_pseudo_fmin/fmax (#209434)
Mode 2 of vfmin/vfmax is also compatible with strict semantics
(producing invalid operation exception for both qNaN and sNaN and
returning RHS if masked.)
Commit: 6d12cf1389fa3ef57f880b8c0b25e66f0caa2f32
https://github.com/llvm/llvm-project/commit/6d12cf1389fa3ef57f880b8c0b25e66f0caa2f32
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/Analysis/CGSCCPassManager.h
M llvm/include/llvm/CodeGen/MachinePassManager.h
M llvm/include/llvm/IR/PassManager.h
M llvm/include/llvm/IR/PassManagerInternal.h
M llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
Log Message:
-----------
Reapply "[IR][NFC] Drop vtable from PassConcept/PassModel" (#208168) (#209414)
The PassConcept/PassModel vtable has a size of 64 bytes (offset to top,
RTTI pointer, complete object destructor, deleting destructor, run,
printPipeline, name, isRequired), which add up to 53kiB (all
targets)/44 kiB (single-target). As more back-end passes get ported to
the new pass manager, this size will increase.
Remove the vtables by replacing the virtual dispatch with explicit
function pointers, initialized when adding the pass to the pass manager.
While this very slightly increases the cost of adding a pass, there's
also a very slight win from avoiding the vtable indirection when
running/destructing the pass.
Use a unique_ptr with a custom deleter to store PassConcept instances.
This avoids new/delete size mismatches.
This reverts commit 6ae5965f26e53d7338a779a73725a597a4d136e5.
Commit: b1a6a90dff53b60d66f49516938ef47344a45699
https://github.com/llvm/llvm-project/commit/b1a6a90dff53b60d66f49516938ef47344a45699
Author: Vachan <vachanvy05 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/test/CodeGen/X86/bitcnt-load-with-cmov.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt-i64.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt-i64.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt.ll
Log Message:
-----------
[X86] Remove redundant `cmp` before `adc` after `lzcnt` or `tzcnt` (#208392)
fixes #193178
Commit: 3205689645eea30c9d7fde2474bdeff52629210d
https://github.com/llvm/llvm-project/commit/3205689645eea30c9d7fde2474bdeff52629210d
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/test/unit/ErrorTest.cpp
Log Message:
-----------
[orc-rt] Move ErrorTest death tests to an ErrorDeathTest suite. (#209476)
GoogleTest recommends putting death tests in a suite whose name ends in
"DeathTest": it runs those suites before all others, which avoids the
fork-after-threads hazard that can make death tests flaky.
Move the nine EXPECT_DEATH tests in ErrorTest.cpp from the ErrorTest
suite to a new ErrorDeathTest suite. Only the suite name changes; the
test bodies are untouched.
Commit: 1b10cd91d12d783fe8754c100a3afaacfee3bf9f
https://github.com/llvm/llvm-project/commit/1b10cd91d12d783fe8754c100a3afaacfee3bf9f
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/non-power-of-2-with-adjusted-gathers.ll
M llvm/test/Transforms/SLPVectorizer/X86/control-deps-schedule-data-recalculate.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-root-multiuse-same-opcode.ll
Log Message:
-----------
[SLP]Do not blacklist ordered-reduction operands on failed root attempt
An ordered reduction pulls its leaf operands into ReductionOps via the
fallback in matchAssociativeReduction. When such a reduction fails to
vectorize, marking every reduction op as analyzed also blocks those leaves,
which may still be valid reduction roots on their own.
Fixes https://github.com/llvm/llvm-project/pull/185320#issuecomment-4925949343
Reviewers: hiraditya, bababuck, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/208511
Commit: db63c56a4f985426a0c44de4da215eb06cd5a278
https://github.com/llvm/llvm-project/commit/db63c56a4f985426a0c44de4da215eb06cd5a278
Author: Midhunesh <midhunesh.p at ibm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M compiler-rt/lib/asan/AIX/asan.link_with_main_exec.txt
M compiler-rt/lib/asan/asan_malloc_linux.cpp
M compiler-rt/test/asan/TestCases/AIX/vec_malloc_calloc.cpp
Log Message:
-----------
[ASan][AIX] Intercept __linux_vec_malloc/__linux_vec_calloc/__linux_realloc (#209359)
On AIX PASE, when `__VEC__` and `_ALL_SOURCE` are defined, the XL
compiler frontend lowers calls to vec_malloc/vec_calloc/realloc to
internal symbols named `__linux_vec_malloc`, `__linux_vec_calloc`, and
`__linux_realloc` instead of the standard
`vec_malloc`/`vec_calloc`/`realloc` names. These symbols were not
intercepted, so allocations made through them bypassed ASan entirely, no
redzone poisoning, no use-after-free or overflow detection.
This adds interceptors for `__linux_vec_malloc`, `__linux_vec_calloc`,
and `__linux_realloc`, following the same pattern as the existing
`vec_malloc`/`vec_calloc` interceptors (#175584): `__linux_vec_malloc`
and `__linux_vec_calloc` route through
`asan_vec_malloc`/`asan_vec_calloc` (16-byte aligned), and
`__linux_realloc` routes through the existing `asan_realloc`.
---------
Co-authored-by: Midhunesh <midhuensh.p at ibm.com>
Commit: e731908c4f84e04a5bfbe2784231f072aac90fe6
https://github.com/llvm/llvm-project/commit/e731908c4f84e04a5bfbe2784231f072aac90fe6
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaConcept.cpp
M clang/test/SemaCXX/concepts-subsumption.cpp
Log Message:
-----------
[Clang] Adjust NTTP depths in IsAtLeastAsConstrained (#209445)
The default transform for NTTP, which is no-op, doesn't help if we need
to adjust their depths when comparing constraints.
Fixes https://github.com/llvm/llvm-project/issues/182671
Commit: 53da348e107f8e6a52625ceab355c6d200a9709a
https://github.com/llvm/llvm-project/commit/53da348e107f8e6a52625ceab355c6d200a9709a
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll
Log Message:
-----------
[LV] Add test showing incorrect trip count materialization (NFC) (#209460)
Add test case showing mis-compile for
https://github.com/llvm/llvm-project/issues/209159.
Commit: 0a5793ba557fb31ea1f847aa353397bb9b88cb18
https://github.com/llvm/llvm-project/commit/0a5793ba557fb31ea1f847aa353397bb9b88cb18
Author: ayrai-gb <ayrai at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
A llvm/test/Transforms/InstCombine/shuffle-cmp-cast-preserve-flags.ll
Log Message:
-----------
[InstCombine] Preserve IR flags when reordering icmp/fcmp/cast through a shuffle (#208627)
InstCombine's `evaluateInDifferentElementOrder` pushes a lane-reordering
`shufflevector` *through* the instruction that produced its input,
rebuilding that instruction on the reordered operands via the `buildNew`
helper — a `switch` with one case per opcode. The binary-operator case
carefully re-applies the original's poison-generating flags
(`nuw`/`nsw`, `exact`, FMF), and the `GetElementPtr` case passes through
its `getNoWrapFlags()`.
The `ICmp`, `FCmp`, and cast cases are the odd ones out. Each is a terse
`return Builder.CreateICmp/CreateFCmp/CreateCast(...)` that copies only
the predicate/opcode, returning the rebuilt instruction with default
flags. As a result a reordered `icmp samesign`, `fcmp nnan ninf`, `zext
nneg`, or `trunc nuw`/`nsw` silently loses its flag, even though the
flag held on the original.
Route each rebuilt instruction through `copyIRFlags(I)`, bringing these
cases in line with the binary-op and GEP cases. `copyIRFlags` transfers
only the flags the source instruction actually carried, so this can
never introduce an unsound promise. This is a missed-optimization fix,
not a miscompile — dropping these flags only makes later passes more
conservative.
Added
`llvm/test/Transforms/InstCombine/shuffle-cmp-cast-preserve-flags.ll`
(`icmp_samesign`, `fcmp_fmf`, `zext_nneg`), which feed the compare/cast
from `insertelement` chains so that `canEvaluateShuffled` permits the
reorder and `buildNew` actually runs, and check that the flag survives
on the rebuilt instruction after the reversing shuffle.
Found via jlebar's X86 LLVM bug-hunt / FuzzX effort:
https://github.com/SemiAnalysisAI/FuzzX/tree/master/x86/bugs/241-instcombine-buildNew-shuffle-reorder-drops-cmp-cast-flags
---------
Co-authored-by: Ayush Rai <ayrai at amd.com>
Commit: 2a1200e08cd1cb0e6744e38a7ec4611d983fb44f
https://github.com/llvm/llvm-project/commit/2a1200e08cd1cb0e6744e38a7ec4611d983fb44f
Author: Akash Banerjee <akash.banerjee at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/lib/Optimizer/OpenMP/AutomapToTargetData.cpp
A flang/test/Lower/OpenMP/declare-target-automap.f90
M flang/test/Transforms/omp-automap-to-target-data.fir
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-host.mlir
M offload/test/offloading/fortran/declare-target-automap.f90
Log Message:
-----------
[Flang][OpenMP] Fix Fortran automap handling (#162501)
This fixes Fortran `declare target enter(automap:...)` handling for
allocatable
descriptors.
- Replace the previous `has_device_addr` target-region rewrite with
explicit
target data operations around allocation/deallocation.
- On allocation, emit:
- descriptor `map(always,to)` to keep the Fortran descriptor present
- storage `map(storage)` for the allocated array data
- `map(attach)` to update the device descriptor base address to the
device data
- On deallocation, delete both the mapped storage and descriptor.
- Add a weak visible offload-entry alias for local/hidden `declare
target to/enter`
globals so libomptarget can associate the host descriptor with the real
device
global without changing the original symbol linkage.
This fixes `offload/test/offloading/fortran/declare-target-automap.f90`
reported broken in #161265.
Co-authored-by: Codex <codex at openai.com>
Commit: e1d7480aabee9ea5b06be8f7902ff2ab23f50647
https://github.com/llvm/llvm-project/commit/e1d7480aabee9ea5b06be8f7902ff2ab23f50647
Author: Benedek Kaibas <82393336+benedekaibas at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
M clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.h
A clang/lib/StaticAnalyzer/Checkers/ReportDanglingPtrDeref.cpp
A clang/test/Analysis/dangling-ptr-deref.cpp
Log Message:
-----------
[analyzer] Implemented the DanglingPtrDeref checker to detect use-after-scope lifetime errors (#209278)
Commit: 8b7b61f099616a3fbeca563b7a1da34279142797
https://github.com/llvm/llvm-project/commit/8b7b61f099616a3fbeca563b7a1da34279142797
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
A llvm/test/tools/llvm-reduce/reduce-instructions-x86-amx.ll
A llvm/test/tools/llvm-reduce/reduce-operands-x86-amx.ll
M llvm/tools/llvm-reduce/deltas/ReduceInstructions.cpp
M llvm/tools/llvm-reduce/deltas/ReduceOperands.cpp
Log Message:
-----------
[llvm-reduce] Avoid invalid replacements with x86_amx type (#209506)
It's not possible to create zero constants of this type, and even
poison constants result in a verifier error when used as an intrinsic
argument.
Commit: d6349588f34bc2f087ba6440049473ecd97853e0
https://github.com/llvm/llvm-project/commit/d6349588f34bc2f087ba6440049473ecd97853e0
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[lldb][Windows] add release notes for the Python private API removal (#209456)
The official lldb releases set `LLDB_EMBED_PYTHON_HOME` to `OFF`
https://github.com/llvm/llvm-project/blob/9582f71a3b5f71e871bee0062e641f3587e0ae23/llvm/utils/release/build_llvm_release.bat#L213
meaning that lldb on Windows does not use the private Python API by
default. Users are free to use any Python version they want. Add a
release note for this.
Commit: de4bb53abe61dec8482f91b39ce3dac6ab0d5cd9
https://github.com/llvm/llvm-project/commit/de4bb53abe61dec8482f91b39ce3dac6ab0d5cd9
Author: lntue <lntue at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libc/test/src/sys/mman/linux/posix_madvise_test.cpp
Log Message:
-----------
[libc] Fix posix_madvise_test for riscv32 bot. (#209504)
Commit: e217dcb8de5dd83b307fe8b95b43de11a7d894ab
https://github.com/llvm/llvm-project/commit/e217dcb8de5dd83b307fe8b95b43de11a7d894ab
Author: George Burgess IV <george.burgess.iv at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
Log Message:
-----------
[mlir] fix builders by moving var into assert (#209494)
non-asserts builders are failing since `vecTy` is unused aside from this
one assertion: https://lab.llvm.org/buildbot/#/builders/228/builds/4754
Since side-effects here are uninteresting, move the entire expr into the
assert, per CodingStandards.md
Fix-forward for #199700
Commit: 05aba69f4d8ee34179b0658c57280064a724f039
https://github.com/llvm/llvm-project/commit/05aba69f4d8ee34179b0658c57280064a724f039
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
A llvm/test/tools/llvm-reduce/reduce-operands-to-args-x86-amx.ll
M llvm/tools/llvm-reduce/deltas/ReduceOperandsToArgs.cpp
Log Message:
-----------
[llvm-reduce] Avoid another invalid x86_amx replacement (#209509)
Commit: 7cd1a8361376525a6094b0b365d5e726f014cde6
https://github.com/llvm/llvm-project/commit/7cd1a8361376525a6094b0b365d5e726f014cde6
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/tools/lldb-dap/DAPSessionManager.cpp
Log Message:
-----------
[lldb-dap] Simplify DAPSessionManager GetInstance (#209264)
We don't need the `std::call_once` as this guaranteed to be [thread safe
and initialised
once](https://en.cppreference.com/cpp/language/storage_duration#Static_block_variables)
since c++11.
Commit: 2ff357b2e1b9aed337a50478af2469fd9fd7442d
https://github.com/llvm/llvm-project/commit/2ff357b2e1b9aed337a50478af2469fd9fd7442d
Author: Joel Walker <theagingboy05 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Support/KnownBits.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sdiv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-udiv.mir
M llvm/test/CodeGen/X86/udiv_fix.ll
M llvm/test/CodeGen/X86/udiv_fix_sat.ll
M llvm/test/Transforms/InstCombine/known-bits.ll
Log Message:
-----------
[KnownBits] Use min non-zero divisor and quotient lower bound in udiv (#209360)
`KnownBits::udiv` was discarding information in two cases. This tightens
both:
- A zero divisor is UB, so when the divisor's known bits permit zero,
use the smallest non-zero value as the minimum divisor instead of
bailing out.
- Compute a lower bound on the quotient (`MinNum / MaxDenom`) and keep
the leading bits it shares with the upper bound, the same way
`ConstantRange::toKnownBits` does.
Both follow from the quotient being monotonic in each operand, with all
four operand bounds attainable.
`KnownBitsTest.BinaryExhaustive` passes with no unsound results, and an
exhaustive width-4 check drops suboptimal outputs from 1790 to 864.
Regenerated the affected MIR and InstCombine tests; two X86 fixed-point
tests lose now-redundant instructions.
Assisted by Claude (Anthropic).
Commit: 132ba0d21e9f53671906af6b0a8343245b4c5021
https://github.com/llvm/llvm-project/commit/132ba0d21e9f53671906af6b0a8343245b4c5021
Author: lianjinfeng2003 <101249452+mygitljf at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
Log Message:
-----------
[CIR][NFC] Update fpclass mask checks (#208975)
I updated the CIR checks to match the formatted `llvm.is.fpclass` masks
introduced by #207653. This fixes the three CIR test failures that
became visible after #208919 restored the CIR build.
Commit: 0530817558e92a99ad3a37372dc42eb165f5f69e
https://github.com/llvm/llvm-project/commit/0530817558e92a99ad3a37372dc42eb165f5f69e
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/__init__.py
R lldb/packages/Python/lldbsuite/test/tools/lldb_dap/dap_types.py
R lldb/packages/Python/lldbsuite/test/tools/lldb_dap/lldb_dap_testcase.py
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session.py
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
A lldb/packages/Python/lldbsuite/test/tools/lldb_dap/testcase.py
A lldb/packages/Python/lldbsuite/test/tools/lldb_dap/types.py
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/utils.py
M lldb/test/API/tools/lldb-dap/exception/TestDAP_exception.py
M lldb/test/API/tools/lldb-dap/exception/asan/TestDAP_asan.py
M lldb/test/API/tools/lldb-dap/exception/cpp/TestDAP_exception_cpp.py
M lldb/test/API/tools/lldb-dap/exception/objc/TestDAP_exception_objc.py
M lldb/test/API/tools/lldb-dap/exception/ubsan/TestDAP_ubsan.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_args.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_basic.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_cwd.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_debuggerRoot.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_disableSTDIO.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_environment_with_array.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_environment_with_object.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_extra_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_failing_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_failing_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_invalid_launch_commands_and_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_invalid_program.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_no_lldbinit_flag.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_shellExpandArguments_disabled.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_shellExpandArguments_enabled.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_sourcePath.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection_and_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stopOnEntry.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_terminate_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_termination.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_version.py
M lldb/test/API/tools/lldb-dap/module-event/TestDAP_module_event.py
M lldb/test/API/tools/lldb-dap/module/TestDAP_module.py
M lldb/test/API/tools/lldb-dap/moduleSymbols/TestDAP_moduleSymbols.py
M lldb/test/API/tools/lldb-dap/stackTrace/TestDAP_stackTrace.py
M lldb/test/API/tools/lldb-dap/stackTraceCompilerGeneratedCode/TestDAP_stackTraceCompilerGeneratedCode.py
M lldb/test/API/tools/lldb-dap/stackTraceDisassemblyDisplay/TestDAP_stackTraceDisassemblyDisplay.py
M lldb/test/API/tools/lldb-dap/stackTraceMissingFunctionName/TestDAP_stackTraceMissingFunctionName.py
M lldb/test/API/tools/lldb-dap/stackTraceMissingModule/TestDAP_stackTraceMissingModule.py
M lldb/test/API/tools/lldb-dap/utils/TestDAPUtils_DAPConnection.py
M lldb/test/API/tools/lldb-dap/utils/TestDAPUtils_EventHistory.py
M lldb/test/API/tools/lldb-dap/utils/TestDAPUtils_Types.py
M lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py
M lldb/test/API/tools/lldb-dap/variables/children/TestDAP_variables_children.py
Log Message:
-----------
[NFC][lldb-dap] Simplify DAP imports. (#209442)
Expose commonly used classes in the lldb_dap package and avoid repeating
the lldb_dap namespace.
Commit: 921361839666196d5b60fc6e57836570ec86665a
https://github.com/llvm/llvm-project/commit/921361839666196d5b60fc6e57836570ec86665a
Author: Nerixyz <nerixdev at outlook.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/source/Plugins/SymbolLocator/SymStore/CMakeLists.txt
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[lldb] Add release note for SymStore and generate settings docs (#209469)
We didn't have a release note for the symstore symbol locator and the
settings weren't included on https://lldb.llvm.org/use/settings.html.
The second part is probably because both were landing at the same time,
so I missed the JSON output there.
Commit: ce72145fd034cdb8abe5d14c5f9e73b8b47a8e6b
https://github.com/llvm/llvm-project/commit/ce72145fd034cdb8abe5d14c5f9e73b8b47a8e6b
Author: Usman Nadeem <mnadeem at qti.qualcomm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AArch64/fold-sext-in-reg-predicate-fixed-length.ll
M llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
Log Message:
-----------
[SelectionDAG] Add GET_ACTIVE_LANE_MASK to ComputeNumSignBits (#208977)
`GET_ACTIVE_LANE_MASK ` acts like `icmp ult` so code is similar to
`SETCC`.
Commit: fdc884f5a5f0921a191bfec3bdf2ac9aae21687a
https://github.com/llvm/llvm-project/commit/fdc884f5a5f0921a191bfec3bdf2ac9aae21687a
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M .github/workflows/containers/github-action-ci-windows/Dockerfile
Log Message:
-----------
[docker][Windows] install libxml2 using vcpkg (#209422)
Since https://github.com/llvm/llvm-project/pull/209258, lldb uses
`lldb-server.exe` by default if libxml2 is available at build time. This
means that lldb-server requires installing libxml2 in the CI
environments to test it.
This patch adds a step to install libxml2 in the docker container used
for lldb pre-merge testing on Windows.
Commit: 7b54498f07642eb8f243664079211528d6a3b0a6
https://github.com/llvm/llvm-project/commit/7b54498f07642eb8f243664079211528d6a3b0a6
Author: Nicolas Miller <nicolas.pierre.miller at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/Hexagon/HexagonPatterns.td
M llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
M llvm/test/CodeGen/Hexagon/fminmax-v67.ll
M llvm/test/CodeGen/Hexagon/fminmax.ll
Log Message:
-----------
[Hexagon] Add lowering for `{max,min}num` (#202938)
Since the floating point requirements for `{max,min}num` are less strict
than the ones for `{max,min}imumnum`, it is fine to lower them to the
same instructions that already meet the requirements for the latter.
This is similar to what the RISC-V backend does for example.
This is also a lot better than generating a standard library call.
Commit: 48c259847d186c4d773407c63393e28d0170666b
https://github.com/llvm/llvm-project/commit/48c259847d186c4d773407c63393e28d0170666b
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll
Log Message:
-----------
[VPlan] Use VPlan::hasTailFolded in materializeConstantVectorTC. (#209502)
The current checks in materializeConstantVectorTripCount miss
tail-folded cases when vectorizing loops with fmax without fast-math
flags. Use recently added hasTailFolded helper to ensure we always bail
out on tail-folded loops.
Fixes https://github.com/llvm/llvm-project/issues/209159.
Commit: a80e98e15a6188f2eed31a70a8834264a2319f81
https://github.com/llvm/llvm-project/commit/a80e98e15a6188f2eed31a70a8834264a2319f81
Author: Mircea Trofin <mtrofin at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/test/CodeGenCUDA/device-stub.cu
Log Message:
-----------
[clang][cuda] Use the source filename for module ID (#209239)
Prior to
[#184065](vscode-file://vscode-app/Applications/Visual%20Studio%20Code.app/Contents/Resources/app/out/vs/code/electron-browser/workbench/workbench.html
"https://github.com/llvm/llvm-project/issues/184065") (relanded in
[#201849](vscode-file://vscode-app/Applications/Visual%20Studio%20Code.app/Contents/Resources/app/out/vs/code/electron-browser/workbench/workbench.html
"https://github.com/llvm/llvm-project/issues/201849")), the code
introduced in https://reviews.llvm.org/D42922 was using the GUID of an
internal linkage GlobalValue to create a module id, which would then be
used in a few cuda-specific places (including creating a symbol name
suffix).
[#184065](vscode-file://vscode-app/Applications/Visual%20Studio%20Code.app/Contents/Resources/app/out/vs/code/electron-browser/workbench/workbench.html
"https://github.com/llvm/llvm-project/issues/184065") assumed the
linkage of that symbol is external - which it isn't - and, thus, all
module IDs computed for this would be identical.
The fix is to not rely on GlobalValue GUIDs in the first place. What is
needed here is a hash that's specific to this module. So we're creating
that and explicitly decoupling that calculation from GlobalValue's
notion of GUIDs.
The change should be safe wrt uniqueness / hash collisions: the old
behavior was computing a hash where the only distinguishing component
was the module's `getSourceFileName`.
FWIW, there's a stronger module ID we could compute, with
`llvm::getUniqueModuleId` (or with a trivial refactoring of it, because
it prepends a ".").
Commit: 97f76580cdb0893d0b4edc7adf703162a23c0a67
https://github.com/llvm/llvm-project/commit/97f76580cdb0893d0b4edc7adf703162a23c0a67
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
M clang/test/CodeGen/memcpy-inline-builtin.c
M clang/test/CodeGen/pr9614.c
Log Message:
-----------
[Clang] Require x86 target for some tests (#209532)
These tests assert behavior about the always-inliner which now requires
a target to be present to check function attribute compatibility for
inlining.
Fix forward for 37b8e765ce4837a7577e6f762bcdffe4b232759c.
Commit: 7d511e4c9dfeed9884bc3e0b76f720e6cc1ad437
https://github.com/llvm/llvm-project/commit/7d511e4c9dfeed9884bc3e0b76f720e6cc1ad437
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-doc/BUILD.gn
R llvm/utils/gn/secondary/clang-tools-extra/clang-doc/markdown/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/unittests/clang-doc/BUILD.gn
Log Message:
-----------
[gn] port 7633d1e7a0f336 (no more clangDocMarkdown) (#209546)
Commit: 1f066996b7cc3715300ee9841e4000cd546d6135
https://github.com/llvm/llvm-project/commit/1f066996b7cc3715300ee9841e4000cd546d6135
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-doc/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/unittests/clang-doc/BUILD.gn
Log Message:
-----------
[gn build] Port 1bd46015ea4e (#209543)
Commit: 6f2cffb15640809fb86e27c807b366c08e790c54
https://github.com/llvm/llvm-project/commit/6f2cffb15640809fb86e27c807b366c08e790c54
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Passes/BUILD.gn
Log Message:
-----------
[gn build] Port 5d5dd83a547e (#209544)
Commit: 2eac996946092e7dc11ef4027c9202734b7e600e
https://github.com/llvm/llvm-project/commit/2eac996946092e7dc11ef4027c9202734b7e600e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/lo16-lo16-physreg-copy-sgpr.mir
M llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
M llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-f64.ll
M llvm/test/CodeGen/AMDGPU/load-global-i1.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i64.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-invariant.ll
M llvm/test/CodeGen/AMDGPU/load-hi16.ll
M llvm/test/CodeGen/AMDGPU/load-lo16.ll
M llvm/test/CodeGen/AMDGPU/load-local-f32-no-ds128.ll
M llvm/test/CodeGen/AMDGPU/load-local-f32.ll
M llvm/test/CodeGen/AMDGPU/load-local-f64.ll
M llvm/test/CodeGen/AMDGPU/load-local-i1.ll
M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
M llvm/test/CodeGen/AMDGPU/load-local-i32.ll
M llvm/test/CodeGen/AMDGPU/load-local-i64.ll
M llvm/test/CodeGen/AMDGPU/load-local-i8.ll
M llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
M llvm/test/CodeGen/AMDGPU/load-local.128.ll
M llvm/test/CodeGen/AMDGPU/load-local.96.ll
M llvm/test/CodeGen/AMDGPU/load-range-metadata-assert.ll
M llvm/test/CodeGen/AMDGPU/load-range-metadata-sign-bits.ll
M llvm/test/CodeGen/AMDGPU/load-saddr-offset-imm.ll
M llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
M llvm/test/CodeGen/AMDGPU/load-store-cnt.ll
M llvm/test/CodeGen/AMDGPU/load-store-opt-addc0.mir
M llvm/test/CodeGen/AMDGPU/load-store-opt-dlc.mir
M llvm/test/CodeGen/AMDGPU/load-store-opt-ds-regclass-constrain.mir
M llvm/test/CodeGen/AMDGPU/load-store-opt-scale-offset.mir
M llvm/test/CodeGen/AMDGPU/load-store-opt-scc.mir
M llvm/test/CodeGen/AMDGPU/load-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/local-64.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/local-atomics.ll
M llvm/test/CodeGen/AMDGPU/local-atomics64.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-memory.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-sort-framerefs.mir
M llvm/test/CodeGen/AMDGPU/local-stack-slot-offset.ll
M llvm/test/CodeGen/AMDGPU/loop-header-align-gfx950.mir
M llvm/test/CodeGen/AMDGPU/loop-idiom.ll
M llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll
M llvm/test/CodeGen/AMDGPU/loop-on-function-argument.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
M llvm/test/CodeGen/AMDGPU/loop_header_nopred.mir
M llvm/test/CodeGen/AMDGPU/lower-brcond-with-xor.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-dead-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-lastuse-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-declaration.ll
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-existing.ll
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll
M llvm/test/CodeGen/AMDGPU/lower-empty-ctor-dtor.ll
M llvm/test/CodeGen/AMDGPU/lower-i1-copies-clear-kills.mir
M llvm/test/CodeGen/AMDGPU/lower-i1-copies-implicit-def-unstructured-loop.mir
M llvm/test/CodeGen/AMDGPU/lower-indirect-lds-references.ll
M llvm/test/CodeGen/AMDGPU/lower-intrinsics-noalias-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-and-module-lds.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-arguments-noalias-call-no-ptr-args.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-lds-constexpr.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-lds-super-align.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-lds.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-merge.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-with-alias-scope.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-with-noalias.ll
M llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics-threshold.ll
M llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (23) (#209214)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: c8c3c30d5b986450618e77ed1069232a2063a0ae
https://github.com/llvm/llvm-project/commit/c8c3c30d5b986450618e77ed1069232a2063a0ae
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysis/Analyses/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/ScalableStaticAnalysis/BUILD.gn
Log Message:
-----------
[gn build] Port 612e7ca85c53 (#209545)
Commit: c8e2abb23d252da15fc16fcd6f43f9ab7543e02d
https://github.com/llvm/llvm-project/commit/c8e2abb23d252da15fc16fcd6f43f9ab7543e02d
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn
Log Message:
-----------
[gn build] Port a718d2ad092b (#209547)
Commit: 61853bac070678debbd80acf891dd681ceb0c1eb
https://github.com/llvm/llvm-project/commit/61853bac070678debbd80acf891dd681ceb0c1eb
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-doc/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/unittests/clang-doc/BUILD.gn
Log Message:
-----------
[gn build] Port c6ebd7a2ced7 (#209548)
Commit: 26e2b0980e10001174405d4412abd0d86f2e0ff5
https://github.com/llvm/llvm-project/commit/26e2b0980e10001174405d4412abd0d86f2e0ff5
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn
Log Message:
-----------
[gn build] Port e1d7480aabee (#209549)
Commit: 77ff300cdfdbafc1abf60a79c32da497616afc1a
https://github.com/llvm/llvm-project/commit/77ff300cdfdbafc1abf60a79c32da497616afc1a
Author: lntue <lntue at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libc/test/src/sys/mman/linux/posix_madvise_test.cpp
Log Message:
-----------
[libc] Fix a typo in posix_madvise_test. (#209523)
Commit: cb83c6a8ba2f17cfb8d01d10722b9c1aa9743328
https://github.com/llvm/llvm-project/commit/cb83c6a8ba2f17cfb8d01d10722b9c1aa9743328
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/test/benchmarks/algorithms/min.bench.cpp
M libcxx/test/benchmarks/algorithms/minmax.bench.cpp
M libcxx/test/benchmarks/algorithms/nonmodifying/search_n.bench.cpp
Log Message:
-----------
[libc++][NFC] Remove unused <cassert> from algorithm benchmarks (#209492)
A few benchmark files were including <cassert> but didn't use it.
Commit: 1a072b5f008321f22e61f744b7474fe52f0ee48c
https://github.com/llvm/llvm-project/commit/1a072b5f008321f22e61f744b7474fe52f0ee48c
Author: Douglas Yung <douglas.yung at sony.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/SystemZ/zos-ppa2.ll
Log Message:
-----------
Fix test that had a check embedded which depended on the current LLVM version number. (#209530)
When the test was refactored, it embedded the current LLVM version
number in one of the check strings so that when I bumped the LLVM
version to 24, the test failed since it was expecting 23 but the
compiler was now generating 23.
Fix this issue by changing the check to a regex so it doesn't need
updating after every LLVM version change.
Commit: 83dc9c6c9a56bc90faa810512e0577e59dc46033
https://github.com/llvm/llvm-project/commit/83dc9c6c9a56bc90faa810512e0577e59dc46033
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Support/CMakeLists.txt
M flang/lib/Optimizer/Support/InitFIR.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
M mlir/include/mlir/Target/LLVMIR/Dialect/All.h
R mlir/include/mlir/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.h
M mlir/lib/Target/LLVMIR/CMakeLists.txt
M mlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt
R mlir/lib/Target/LLVMIR/Dialect/OpenACC/CMakeLists.txt
R mlir/lib/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.cpp
R mlir/test/Target/LLVMIR/openacc-llvm.mlir
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/Support/BUILD.bazel
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/Transforms/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][openacc] Remove OpenACCToLLVMIRTranslation (#209295)
OpenACCToLLVMIRTranslation was designed more than 5 years ago and does
not align with the current upstreaming effort. OpenACC will be converted
to LLVM IR dialect before the translation to LLVM IR so this translation
is obsolete. Remove it to avoid confusion.
Commit: 4697832bae3f891c474fba3c58e852585bd1ff5f
https://github.com/llvm/llvm-project/commit/4697832bae3f891c474fba3c58e852585bd1ff5f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/lower-module-lds-all-indirect-accesses.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr-phi.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-inactive.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-indirect-extern-uses-max-reachable-alignment.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-classify.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-global-scope.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-internal-func.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-internal-multi-user.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-offsets.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-precise-allocate-to-module-struct.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-ambiguous.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-unambiguous.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-used-list.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-zero-size-arr.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds.ll
M llvm/test/CodeGen/AMDGPU/lower-multiple-ctor-dtor.ll
M llvm/test/CodeGen/AMDGPU/lower-noalias-kernargs.ll
M llvm/test/CodeGen/AMDGPU/lower-term-opcodes.mir
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-opt.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/lrint.ll
M llvm/test/CodeGen/AMDGPU/lro-coerce-v4i8-phi-loop.ll
M llvm/test/CodeGen/AMDGPU/lro-phi-samebb-nonlookthrough-store.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/lsr-cost-model-vector-iv.ll
M llvm/test/CodeGen/AMDGPU/lto-lower-module-lds.ll
M llvm/test/CodeGen/AMDGPU/machine-cp-propagation.mir
M llvm/test/CodeGen/AMDGPU/machine-cse-commute-target-flags.mir
M llvm/test/CodeGen/AMDGPU/machine-cse-ssa.mir
M llvm/test/CodeGen/AMDGPU/machine-function-info-cwsr.ll
M llvm/test/CodeGen/AMDGPU/machine-scheduler-rematerialization-scoring.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-revert-slot-monotonicity.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-cycle.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-fence.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-ignorable-exec-use.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-lane-mask.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
M llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir
M llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
M llvm/test/CodeGen/AMDGPU/mad-combine.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/mad_int24.ll
M llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
M llvm/test/CodeGen/AMDGPU/mad_uint24.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-mfma-scale.gfx950.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards.mir
M llvm/test/CodeGen/AMDGPU/mai-inline.ll
M llvm/test/CodeGen/AMDGPU/make-buffer-rsrc-lds-fails.ll
M llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/max3.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/mcexpr-knownbits-assign-crash-gh-issue-110930.ll
M llvm/test/CodeGen/AMDGPU/mcp-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/mcp-implicit-clobber.mir
M llvm/test/CodeGen/AMDGPU/mcp-overlap-after-propagation.mir
M llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
M llvm/test/CodeGen/AMDGPU/med3-knownbits.ll
M llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll
M llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
M llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scoped-aa.ll
M llvm/test/CodeGen/AMDGPU/memcpy_const_compare.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/memmove-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (24) (#209485)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: e255003ae9a942d0d62c5c8405dc45de97f31ca4
https://github.com/llvm/llvm-project/commit/e255003ae9a942d0d62c5c8405dc45de97f31ca4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/memory-legalizer-av-none.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-av-unknown.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-barriers-mmra.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-barriers.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-global.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-local.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-addrspace.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-syncscope.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-lds-dma-volatile-and-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.mir
M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/merge-buffer-gfx12.mir
M llvm/test/CodeGen/AMDGPU/merge-buffer.mir
M llvm/test/CodeGen/AMDGPU/merge-consecutive-wait-alus.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-saddr-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-image-load-gfx10.mir
M llvm/test/CodeGen/AMDGPU/merge-image-load-gfx11.mir
M llvm/test/CodeGen/AMDGPU/merge-image-load-gfx12.mir
M llvm/test/CodeGen/AMDGPU/merge-image-load.mir
M llvm/test/CodeGen/AMDGPU/merge-image-sample-gfx10.mir
M llvm/test/CodeGen/AMDGPU/merge-image-sample-gfx11.mir
M llvm/test/CodeGen/AMDGPU/merge-image-sample-gfx12.mir
M llvm/test/CodeGen/AMDGPU/merge-image-sample.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir
M llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll
M llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.mir
M llvm/test/CodeGen/AMDGPU/merge-s-load.mir
M llvm/test/CodeGen/AMDGPU/merge-sbuffer-load.mir
M llvm/test/CodeGen/AMDGPU/merge-store-crash.ll
M llvm/test/CodeGen/AMDGPU/merge-store-usedef.ll
M llvm/test/CodeGen/AMDGPU/merge-stores.ll
M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx10.mir
M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx11.mir
M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx12.mir
M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx9.mir
M llvm/test/CodeGen/AMDGPU/merged-bfx-opt.ll
M llvm/test/CodeGen/AMDGPU/mesa3d.ll
M llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-convergent.mir
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select-gfx942.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/min-waves-per-eu-not-respected.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/min3.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (25) (#209486)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 4a2cfd73fdb55b32c3f341b0db589cf1f22c3a70
https://github.com/llvm/llvm-project/commit/4a2cfd73fdb55b32c3f341b0db589cf1f22c3a70
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll
M llvm/test/Transforms/LoopVectorize/AArch64/alias-mask-uniforms.ll
M llvm/test/Transforms/LoopVectorize/AArch64/alias-mask.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-incomplete-chains.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/pr41179.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing-alias-mask.ll
M llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-alias-mask.ll
M llvm/test/Transforms/LoopVectorize/WebAssembly/induction-branch-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/fold-tail-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-opaque-pointers.ll
M llvm/test/Transforms/LoopVectorize/X86/optsize.ll
M llvm/test/Transforms/LoopVectorize/X86/pr48340.ll
M llvm/test/Transforms/LoopVectorize/X86/pr72969.ll
M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/alias-mask-data-tail-folding-style.ll
M llvm/test/Transforms/LoopVectorize/alias-mask-needs-freeze.ll
M llvm/test/Transforms/LoopVectorize/alias-mask-small-index.ll
M llvm/test/Transforms/LoopVectorize/alias-mask.ll
M llvm/test/Transforms/LoopVectorize/hoist-and-sink-mem-ops-with-invariant-pointers.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-different-insert-position.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
M llvm/test/Transforms/LoopVectorize/metadata.ll
M llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/pr45259.ll
M llvm/test/Transforms/LoopVectorize/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll
M llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll
Log Message:
-----------
[VPlan] Expand SCEV ptrtoint/ptrtoaddr casts in VPSCEVExpander. (#209172)
Extend the cast handling in VPSCEVExpander::tryToExpand to also expand
scPtrToInt and scPtrToAddr SCEV expressions to PtrToInt/PtrToAddr
VPInstructions.
This allows pointer-distance expressions (e.g. the runtime-check
difference between two pointers, which contains ptrtoint of each
pointer) to be expanded directly to VPInstructions instead of falling
back to a VPExpandSCEVRecipe.
PR: https://github.com/llvm/llvm-project/pull/209172
Commit: 194f7a360c475fd7da253248a6aade878b52318c
https://github.com/llvm/llvm-project/commit/194f7a360c475fd7da253248a6aade878b52318c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-014bb.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-cfg-with-self-loop.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-phi-merge-distances.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-acyclic-cfg-with-4-self-loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-11blocks.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-15blocks.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop-a.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/if_else_with_loops_nested_in_2_outer_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/inner_cfg_in_2_nested_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/loop_nested_in_3_outer_loops_complex_cfg.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/nested-loops-with-side-exits-a.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/sequence_2_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/simple-loop-3blocks.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_basic_case.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_do_not_spill_restore_inside_loop.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_common_dominator.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader1.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader2.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader3.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader4.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_keep_spilled_reg_live.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_nested_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_in_common_dominator_and_optimize_restores.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_livethrough_reg.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_value_in_exit_block.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/three-tier-ranking-nested-loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/triple-nested-loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/two-sequential-loops.mir
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
M llvm/test/CodeGen/AMDGPU/mir-dynamic-vgpr-block-size-roundtrip.mir
M llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir
M llvm/test/CodeGen/AMDGPU/misched-into-wmma-hazard-shadow.mir
M llvm/test/CodeGen/AMDGPU/misched-killflags.mir
M llvm/test/CodeGen/AMDGPU/missing-store.ll
M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
M llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll
M llvm/test/CodeGen/AMDGPU/mixed_wave32_wave64.ll
M llvm/test/CodeGen/AMDGPU/mmo-target-flags-folding.ll
M llvm/test/CodeGen/AMDGPU/mmra.ll
M llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus.mir
M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/mode-register.mir
M llvm/test/CodeGen/AMDGPU/modf-constant-fold.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll
M llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu-flat.mir
M llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-absdiff.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-lshl_add.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-lshlrev.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll
M llvm/test/CodeGen/AMDGPU/movreld-bug.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
M llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
M llvm/test/CodeGen/AMDGPU/mubuf.ll
M llvm/test/CodeGen/AMDGPU/mul.i16.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multi-call-resource-usage-mcexpr.ll
M llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
M llvm/test/CodeGen/AMDGPU/multi-dword-vgpr-spill.ll
M llvm/test/CodeGen/AMDGPU/multi-use-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/naked-fn-with-frame-pointer.ll
M llvm/test/CodeGen/AMDGPU/nand.ll
M llvm/test/CodeGen/AMDGPU/narrow_math_for_and.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/neg_ashr64_reduce.ll
M llvm/test/CodeGen/AMDGPU/neighboring-mfma-padding.mir
M llvm/test/CodeGen/AMDGPU/nested-calls.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/no-bundle-asm.ll
M llvm/test/CodeGen/AMDGPU/no-corresponding-integer-type.ll
M llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (26) (#209487)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 27dce1908288eb57ce90b7c42fb7046260f39731
https://github.com/llvm/llvm-project/commit/27dce1908288eb57ce90b7c42fb7046260f39731
Author: Caroline Newcombe <caroline.newcombe at hpe.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
A flang/test/Analysis/AliasAnalysis/alias-analysis-omp-private-boxed-wsloop.mlir
A flang/test/Analysis/AliasAnalysis/alias-analysis-omp-private-unboxed-wsloop.mlir
Log Message:
-----------
[flang][OpenMP] Resolve private array source from block-arg owner in alias analysis (#208227)
Part of #208086. `fir::AliasAnalysis::getSource` fails to recognize an
OpenMP private array as an `Allocate` source when its `hlfir.declare` is
nested inside an omp.loop_nest, and conservatively returns `MayAlias`.
This changes `getSource` to resolve the clause-carrying OpenMP op from
the private block argument's owner region, so the private is correctly
classified and does not spuriously alias other objects. Assisted-by: Copilot
Commit: 9c7d1d2fe0d607b0cd5cfca1b8bb9ea6eee374ec
https://github.com/llvm/llvm-project/commit/9c7d1d2fe0d607b0cd5cfca1b8bb9ea6eee374ec
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/test/std/ranges/range.utility/view.interface/view.interface.pass.cpp
Log Message:
-----------
[libc++][ranges][NFC] Format `view.interface.pass.cpp` (#209391)
A prerequisite to #205012
Commit: 4264f9154c9ee153392cce6c90827fa4544bff7e
https://github.com/llvm/llvm-project/commit/4264f9154c9ee153392cce6c90827fa4544bff7e
Author: void_17 <61356189+void2012 at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Support/Windows/DynamicLibrary.inc
Log Message:
-----------
[NFC] Rename misleading `msvcrt` comment in `Windows/DynamicLibrary.inc` (#208884)
The comment in function `DynamicLibrary::HandleSet::DLSym` referred to
the mysterious `msvc.dll` windows standard dynamic library which simply
doesn't exist and `msvcrt.dll` was likely meant, so fix the comments.
Commit: 7618426138aae95561da676a1d1e10ee0392bf78
https://github.com/llvm/llvm-project/commit/7618426138aae95561da676a1d1e10ee0392bf78
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/include/__functional/function.h
Log Message:
-----------
Revert "[libc++][NFC] Inline std::function members into the class body" (#209555)
Reverts llvm/llvm-project#209461
This is breaking LLDB testing bots and it also failed pre-merge CI.
Commit: d454522b4140d7baa9d1be5d0ce2da327104c0d1
https://github.com/llvm/llvm-project/commit/d454522b4140d7baa9d1be5d0ce2da327104c0d1
Author: Usman Nadeem <mnadeem at qti.qualcomm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/CodeGen/AArch64/active_lane_mask.ll
M llvm/test/CodeGen/AArch64/sve-mask-partition.ll
Log Message:
-----------
[AArch64] Tighten conditions for expanding GET_ACTIVE_LANE_MASK (#208962)
Lower to whilelo in more cases.
For fixed-width even if the operands are <32 bits, expanding is going to
be more expensive compared to promoting the operands from a smaller
type.
For SVE I also added lowering for nxv1i1 type as: `nxv2i1 -> extract
nxv1i1.`
Commit: 84199dde7198eabc924e93750063a20ceef26ef2
https://github.com/llvm/llvm-project/commit/84199dde7198eabc924e93750063a20ceef26ef2
Author: Hubert Tong <hubert.reinterpretcast at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
A libunwind/test/.clang-format
Log Message:
-----------
[libunwind][test] Add .clang-format (#209364)
Borrow from `libcxx/test/.clang-format` to avoid `clang-format`
suggestions that are incompatible with `FileCheck`.
Commit: a56f9cefd75cd12802e37a66425b1a57d761a0af
https://github.com/llvm/llvm-project/commit/a56f9cefd75cd12802e37a66425b1a57d761a0af
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir
Log Message:
-----------
[AMDGPU][CodeGen] Pre-commit test for gfx1250 Setreg hazard violation (#209524)
Co-issue optimizations during placement of `S_SET_VGPR_MSB` instructions
can create a situation where a `S_SET_VGPR_MSB` appears directly after a
`S_SETREG_IMM32_B32(MODE)`, silently dropping the former and causing a
hazard violation on gfx1250.
Commit: 79d1db7e00932407c4aa1028632f2c188d14cac8
https://github.com/llvm/llvm-project/commit/79d1db7e00932407c4aa1028632f2c188d14cac8
Author: Garvit Gupta <garvgupt at qti.qualcomm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrPredicates.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
A llvm/test/CodeGen/RISCV/xqcilo-xqcilia-frame-index.ll
Log Message:
-----------
[RISCV] Fold 26-bit frame-index offsets into Xqcilo/Xqcilia load/store/addi (#209315)
Extend frame-index addressing such that the sp-relative offset resolved for a stack access that fits within 26-bit and not 12-bits; folds directly into the wide Xqcilo/Xqcilia instructions. This is achieved by adding the support for the following:
- Adding support for stack accesses to complex pattern `SelectAddrRegImm26` for 26-bit loads and stores
- Adding support for frame index operand to qc.e.addi instruction
- Allowing 26-bit offsets to fold into the loads and store instructions from qcilo/qcilia extension
Commit: 8410006af686f3fb5e8af2705c8aab28c374c13a
https://github.com/llvm/llvm-project/commit/8410006af686f3fb5e8af2705c8aab28c374c13a
Author: Alex Kuleshov <0xAX at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/tools/llvm-mc/Disassembler.cpp
M llvm/tools/llvm-mc/Disassembler.h
M llvm/tools/llvm-mc/llvm-mc.cpp
Log Message:
-----------
[llvm-mc] Remove unused MCRegisterInfo/MCAsmInfo in Disassembler (NFC) (#208483)
Disassembler::disassemble() creates MCRegisterInfo and MCAsmInfo
instances that are no longer used.
Initially, they were introduced in a1bc0f5 to construct MCContext after
MCDisassembler began requiring one, but became dead in 2cb2707.
llvm-mc's main() already creates both objects and passes them into the
MCContext that disassemble() receives, so the error paths here are
unreachable.
Removing these objects also makes the MCTargetOptions parameter unused,
so drop it as well.
Commit: c7a0afe5049a3d4789f34a8d746c6a45d73557b4
https://github.com/llvm/llvm-project/commit/c7a0afe5049a3d4789f34a8d746c6a45d73557b4
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/source/Utility/Policy.cpp
Log Message:
-----------
[lldb] Gate `PolicyStack::Current()` log behind verbose (#209527)
`Process::GetState()` calls `PolicyStack::Get().Current()` on every
prompt redraw, so the previous unconditional LLDB_LOG at the read site
fired on every keypress once `log enable lldb process` was on, drowning
out any other process log output. Keep the dump for when it's actually
wanted, but only fire it if the log is set to verbose.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 4471a0be22e8784a7487e1ce01e9083b50c47116
https://github.com/llvm/llvm-project/commit/4471a0be22e8784a7487e1ce01e9083b50c47116
Author: David Young <davidayoung at meta.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[lldb][bazel] Generate SafeAutoloadPaths.inc in the Bazel overlay (#209454)
The auto-load-paths mechanism added in #187031 generates
SafeAutoloadPaths.inc via a CMake configure_file() of
SafeAutoloadPaths.inc.in (lldb/source/Core/CMakeLists.txt), gated by the
LLDB_SAFE_AUTO_LOAD_PATHS cache variable which defaults to empty.
Debugger.cpp #includes SafeAutoloadPaths.inc, but the Bazel overlay
never modeled the configure_file(), so the header is missing from the
Bazel build of lldb Core.
Reproduce the generation with expand_template (substituting
@SAFE_PATH_ENTRIES@ with "" to match the empty default). Emit the header
under include/ and expose it via includes = ["include"] so the bare
#include resolves, matching how Config.h and Version.inc are handled in
this overlay.
assisted with: claude
I ensured this is valid bazel that Meta can translate into valid BUCK
and build lldb with internally via buck2. This appears to match a few
other template/library pairs.
Commit: 666b87dd01d31cc80f356315c1c2d03974759138
https://github.com/llvm/llvm-project/commit/666b87dd01d31cc80f356315c1c2d03974759138
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
M llvm/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll
M llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir
M llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
M llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
M llvm/test/CodeGen/AMDGPU/nofpclass-call.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/noop-shader-O0.ll
M llvm/test/CodeGen/AMDGPU/nop-data.ll
M llvm/test/CodeGen/AMDGPU/nor-divergent-lanemask.ll
M llvm/test/CodeGen/AMDGPU/nor.ll
M llvm/test/CodeGen/AMDGPU/nsa-reassign.ll
M llvm/test/CodeGen/AMDGPU/nsa-reassign.mir
M llvm/test/CodeGen/AMDGPU/nsa-vmem-hazard.mir
M llvm/test/CodeGen/AMDGPU/object-linking-local-resources.ll
M llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-and-hostcall.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-pipeline.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-unsupported.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf.ll
M llvm/test/CodeGen/AMDGPU/operand-folding.ll
M llvm/test/CodeGen/AMDGPU/operand-spacing.ll
M llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness-wave32.mir
M llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness.mir
M llvm/test/CodeGen/AMDGPU/opt-vgpr-live-range-verifier-error.mir
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.mir
M llvm/test/CodeGen/AMDGPU/optimize-ds-bvh-stack-pre-ra.ll
M llvm/test/CodeGen/AMDGPU/optimize-exec-copies-extra-insts-after-copy.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-alloc-failure.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-no-fold-exec-copy.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-masking-strip-terminator-bits.mir
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/or3.ll
M llvm/test/CodeGen/AMDGPU/overlapping-tuple-copy-implicit-op-failure.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/packed-dependencies.mir
M llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-bf16.ll
M llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/packed-op-sel.ll
M llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable-dvgpr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-dvgpr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx950.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.6-dvgpr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.6.ll
M llvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/pal-userdata-regs.ll
M llvm/test/CodeGen/AMDGPU/partial-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/peephole-fold-imm-multi-use.mir
M llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
M llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir
M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir
M llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
M llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir
M llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
M llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
M llvm/test/CodeGen/AMDGPU/perfhint.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permlane16_opsel.ll
M llvm/test/CodeGen/AMDGPU/permlane16_var-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/phi-av-pressure.ll
M llvm/test/CodeGen/AMDGPU/phi-elim-mli-available.mir
M llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
M llvm/test/CodeGen/AMDGPU/phys-partial-liveness.mir
M llvm/test/CodeGen/AMDGPU/pk-lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/pk_max_f16_literal.ll
M llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
M llvm/test/CodeGen/AMDGPU/post-ra-sched-reset.mir
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
M llvm/test/CodeGen/AMDGPU/postra-bundle-vimage-vsample-gfx12.mir
M llvm/test/CodeGen/AMDGPU/postra-machine-sink-livein-subrange.mir
M llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir
M llvm/test/CodeGen/AMDGPU/postra-norename.mir
M llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
M llvm/test/CodeGen/AMDGPU/postra-sink-update-dependency.mir
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (27) (#209488)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 4473e5fb88c3f222e6042d0c181a113a2d92b8a0
https://github.com/llvm/llvm-project/commit/4473e5fb88c3f222e6042d0c181a113a2d92b8a0
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
M mlir/test/Dialect/XeGPU/propagate-layout.mlir
M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F4.mlir
Log Message:
-----------
[MLIR][XeGPU] Prefer the nearer consumer's layout in LayoutInfo::meet (#208365)
**Summary**
During backward layout propagation a value can be demanded by multiple
consumers with conflicting
layouts. Previously LayoutInfo::meet kept whichever demand was assigned
first, so the winner depended on
the dataflow worklist's visitation order — nondeterministic and often
not what we want.
This changes meet to prefer the layout demanded by the consumer nearer
to the producer in program order.
This tends to preserve a consumer's layout as far up the def chain as
possible, reducing layout
conversions. It is a heuristic hint, not a proven optimum.
- Each op gets a program-order index from a pre-order walk (matching
printed-IR order), so a use inside
an scf.for body is nearer than a use after the loop.
- LayoutInfo carries the demanding op's index in a new programOrder
field. visitOperation sets a
file-scoped currentProgramOrder, and the single-arg LayoutInfo
constructor stamps it automatically.
- meet keeps the smaller programOrder; ties keep lhs.
- Removes a dead LayoutInfo::transpose declaration.
- Adds truncf_prefers_nearer_user in propagate-layout-inst-data.mlir.
- Updates the multiple-use tests in propagate-layout.mlir
(scatter_ops_preserve_load_perm_layout,
binary_op_multiple_uses, if_multiple_uses) to reflect that the nearer
consumer's layout now wins.
- a minor layout fix for simple_mxfp_gemm_quantizeA_F4.mlir
---------
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: 681cc1b9f87b355c8c5f95ee35d6521e62531ceb
https://github.com/llvm/llvm-project/commit/681cc1b9f87b355c8c5f95ee35d6521e62531ceb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir
M llvm/test/CodeGen/AMDGPU/pr51516.mir
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-IR-lowering.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs-IR-lowering.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
M llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/print-pipeline-passes.ll
M llvm/test/CodeGen/AMDGPU/printf-defined.ll
M llvm/test/CodeGen/AMDGPU/printf-existing-format-strings.ll
M llvm/test/CodeGen/AMDGPU/private-access-no-objects.ll
M llvm/test/CodeGen/AMDGPU/private-function.ll
M llvm/test/CodeGen/AMDGPU/prologue-epilogue-markers.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-allocation.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-bitcast-function.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-cfg.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-globals.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-invariant-markers.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-lifetime.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-loadstores.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-max-regs.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-mem-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-multidim.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-negative-index.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-non-byte-sizes.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-non-constant-index.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-placeholder-replacement.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-pointer-array.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-proper-value-replacement.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-scoring.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-strip-abi-opt-attributes.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-subvecs.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-constantexpr-use.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-icmp.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-phi.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-unhandled-intrinsic.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-use-after-erase.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-user-mult.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep-of-gep.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vgpr-ratio.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-volatile.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx10.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx90a.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir
M llvm/test/CodeGen/AMDGPU/promote-vect3-load.ll
M llvm/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll
M llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
M llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag-mubuf.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag-undef-poison.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
M llvm/test/CodeGen/AMDGPU/ptrmask.ll
M llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-register.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll
M llvm/test/CodeGen/AMDGPU/read-write-register-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/read_register.ll
M llvm/test/CodeGen/AMDGPU/readcyclecounter.ll
M llvm/test/CodeGen/AMDGPU/readlane_exec0.mir
M llvm/test/CodeGen/AMDGPU/readsteadycounter.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll
M llvm/test/CodeGen/AMDGPU/recursion.ll
M llvm/test/CodeGen/AMDGPU/recursive-resource-usage-mcexpr.ll
M llvm/test/CodeGen/AMDGPU/recursive_global_initializer.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (28) (#209489)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: b14bf6e583da3e35054bac26c5eef74ff4e717d2
https://github.com/llvm/llvm-project/commit/b14bf6e583da3e35054bac26c5eef74ff4e717d2
Author: AZero13 <gfunni234 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
A llvm/test/Transforms/InstCombine/udiv-isknownnegative.ll
Log Message:
-----------
[InstCombine] Generalize udiv by negative constant fold to handle non-constant values (#209322)
Use isKnownNegative() to catch non constant divisors.
Commit: 6e80f6733abb83ddc0a5447829a050b0497e0fb5
https://github.com/llvm/llvm-project/commit/6e80f6733abb83ddc0a5447829a050b0497e0fb5
Author: Usman Nadeem <mnadeem at qti.qualcomm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/fold-sext-in-reg-predicate-fixed-length.ll
M llvm/test/CodeGen/AArch64/get-active-lane-mask-extract.ll
Log Message:
-----------
[DAGCombiner] Fold extract_vector(get_active_lane_mask(),0) to get_active_lane_mask (#208978)
If we are extracting from the start of the vector, then we can just
rewrite to `get_active_lane_mask` with a new type and the same operands.
Depends on https://github.com/llvm/llvm-project/pull/208962 and
https://github.com/llvm/llvm-project/pull/208977
Commit: 3d7535a03c1a036204a5347a79e9f66eb96ce4bc
https://github.com/llvm/llvm-project/commit/3d7535a03c1a036204a5347a79e9f66eb96ce4bc
Author: Gábor Horváth <xazax.hun at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LiveOrigins.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LoanPropagation.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/MovedLoans.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/Utils.h
M clang/include/clang/Analysis/Analyses/LiveVariables.h
M clang/lib/Analysis/LiveVariables.cpp
M llvm/benchmarks/ImmutableSetBuildBM.cpp
M llvm/benchmarks/ImmutableSetIteratorBM.cpp
M llvm/include/llvm/ADT/ImmutableMap.h
M llvm/include/llvm/ADT/ImmutableSet.h
M llvm/unittests/ADT/ImmutableSetTest.cpp
Log Message:
-----------
[ADT] Make canonicalization a compile-time parameter of ImmutableSet/Map (#209300)
ImmutableSet and ImmutableMap always carried the machinery needed for
tree canonicalization -- a per-node `prev`/`next` cache chain and cached
`digest`, plus the factory-side cache and a runtime `canonicalize` flag
-- even for the many clients that disable it (the Clang dataflow
analyses, e.g. lifetime safety and LiveVariables, for which
canonicalization is a large performance loss). Those clients paid for
state and code paths they never used.
Add a `bool Canonicalize` template parameter (defaulting to true, so
existing users are unaffected) that moves the decision to compile time:
* When disabled, the `prev`/`next` links (empty base) and `digest`
(LLVM_NO_UNIQUE_ADDRESS member) vanish, shrinking a set node from 56 to
40 bytes and a map node from 64 to 40 on 64-bit; `getCanonicalTree`, the
factory cache, and the `destroy()` unlink branch are `if constexpr`-ed
away. Node fields are ordered so the traversal-hot members come first.
* When enabled, the node layout is unchanged, and `operator==`/`!=`
become O(1) pointer comparisons (equal canonical trees share a root, as
with ImmutableList) instead of a structural walk.
The runtime `canonicalize` factory argument is now redundant and
removed; the in-tree non-canonicalizing users are switched to the
template argument.
Node microbenchmark (ImmutableSetBuildBM, non-canonicalizing, -O2):
| Benchmark | Before | After | Speedup |
|--------------------|---------:|---------:|:-------:|
| Build/256 | 20.3 us | 18.3 us | 1.11x |
| Build/4096 | 790 us | 731 us | 1.08x |
| Build/65536 | 18.8 ms | 18.4 ms | 1.02x |
| BuildRemove/256 | 40.7 us | 35.0 us | 1.16x |
| BuildRemove/4096 | 1.46 ms | 1.39 ms | 1.05x |
| BuildRemove/65536 | 34.6 ms | 33.8 ms | 1.02x |
End to end, the smaller node cuts the lifetime-safety analysis peak RSS
by up to ~23% on allocation-dense inputs with neutral-to-positive run
time, and the O(1) equality speeds up a Clang static analyzer run on
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp by ~1.3% (95.1s -> 93.9s).
Assisted by: Claude Opus 4.8
---------
Co-authored-by: Gabor Horvath <gaborh at apple.com>
Commit: 266c25684b32bd43d846f8de1c3a9f358066ffc4
https://github.com/llvm/llvm-project/commit/266c25684b32bd43d846f8de1c3a9f358066ffc4
Author: Mikhail Gudim <mgudim at qti.qualcomm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetFrameLowering.h
M llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
Log Message:
-----------
[CodeGen] Split determineCalleeSaves into smaller functions. (#203981)
The function `getMustPreserveRegisters` - returns the list of registers
that must be preserved by the function.
The function `determineUncondPrologCalleeSaves` - determines which of
the registers reported by `getMustPreserveRegisters` must be saved in
prolog and reloaded in epilog regardless of whether or not they were
modified by the function.
Commit: 3e706075dc1857e88a293b8104c81b31a08f4cd5
https://github.com/llvm/llvm-project/commit/3e706075dc1857e88a293b8104c81b31a08f4cd5
Author: Liza Burakova <liza at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/include/__pstl/backends/libdispatch.h
Log Message:
-----------
[libc++][pstl] Add missing #pragma GCC system_header to libdispatch.h (#209579)
This adds `#pragma GCC system_header` to libdispatch.h, as removing the
`[system]` attributes in the modulemap surfaced this gap.
Commit: e4a959ffebe24abae49fc93a4f84c58625dabbea
https://github.com/llvm/llvm-project/commit/e4a959ffebe24abae49fc93a4f84c58625dabbea
Author: Florian Mayer <fmayer at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/utils/generate-test-checks.py
Log Message:
-----------
[NFC] [MLIR] fix typo in argument desc (#209587)
Commit: 995b7229bc4a9614669fb57b76c2cddc9fb4db52
https://github.com/llvm/llvm-project/commit/995b7229bc4a9614669fb57b76c2cddc9fb4db52
Author: Scott Linder <scott.linder at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
Log Message:
-----------
[AMDGPU] Fix type for DWARF register number in SIFrameLowering (#209535)
It so happened that using MCRegister here happened to work, but
the encoded dwarf number is definitely not an MCRegister.
Commit: b43a0072fa011ec50c29b683da057730b2682ae2
https://github.com/llvm/llvm-project/commit/b43a0072fa011ec50c29b683da057730b2682ae2
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
Log Message:
-----------
[VPlan] Introduce VPIRFlags::getNWFlagsOrNone (NFC) (#207176)
Similar to getFMFOrNone. Also introduce a default WrapFlagsTy
constructor to go along with it.
Commit: 527396dd7c7370b1649ade49ceb48e48f6f26de1
https://github.com/llvm/llvm-project/commit/527396dd7c7370b1649ade49ceb48e48f6f26de1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/reduce-build-vec-ext-to-ext-build-vec.ll
M llvm/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll
M llvm/test/CodeGen/AMDGPU/reduction.ll
M llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
M llvm/test/CodeGen/AMDGPU/reg-coalescer-subreg-liveness.mir
M llvm/test/CodeGen/AMDGPU/reg-sequence-like-v-pk-mov-b32.mir
M llvm/test/CodeGen/AMDGPU/regalloc-fail-unsatisfiable-overlapping-tuple-hints.mir
M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
M llvm/test/CodeGen/AMDGPU/regalloc-fast-dont-drop-subreg-index-issue61134.mir
M llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.mir
M llvm/test/CodeGen/AMDGPU/regalloc-illegal-eviction-assert.ll
M llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir
M llvm/test/CodeGen/AMDGPU/regalloc-sgpr128-partial-def.mir
M llvm/test/CodeGen/AMDGPU/regalloc-spill-wmma-scale.ll
M llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-64-bit-only-regs.mir
M llvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir
M llvm/test/CodeGen/AMDGPU/register-coalescer--set-undef-full-reg-use-implicit-def-erase-issue109249.mir
M llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
M llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll
M llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
M llvm/test/CodeGen/AMDGPU/reject-agpr-usage-before-gfx908.ll
M llvm/test/CodeGen/AMDGPU/rel32.ll
M llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir
M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12-dvgpr.mir
M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12.mir
M llvm/test/CodeGen/AMDGPU/release-vgprs-spill.ll
M llvm/test/CodeGen/AMDGPU/release-vgprs.mir
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
M llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll
M llvm/test/CodeGen/AMDGPU/remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir
M llvm/test/CodeGen/AMDGPU/remat-smrd.mir
M llvm/test/CodeGen/AMDGPU/remat-sop.mir
M llvm/test/CodeGen/AMDGPU/remat-through-copy.mir
M llvm/test/CodeGen/AMDGPU/remat-vop.mir
M llvm/test/CodeGen/AMDGPU/remove-incompatible-extended-image-insts.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-functions.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-gws.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-s-time.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave32-feature.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave64-feature.ll
M llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
M llvm/test/CodeGen/AMDGPU/remove-not-short-exec-branch-on-unconditional-jump.mir
M llvm/test/CodeGen/AMDGPU/remove-register-flags.mir
M llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-gpr-idx-mode.mir
M llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-special-instructions.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-unused-lanes.ll
M llvm/test/CodeGen/AMDGPU/reorder-stores.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/replace-store-of-insert-load.ll
M llvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/required-export-priority.ll
M llvm/test/CodeGen/AMDGPU/required-export-priority.mir
M llvm/test/CodeGen/AMDGPU/reserved-reg-in-clause.mir
M llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
M llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir
M llvm/test/CodeGen/AMDGPU/resource-usage-dead-function.ll
M llvm/test/CodeGen/AMDGPU/resource-usage-pal.ll
M llvm/test/CodeGen/AMDGPU/ret.ll
M llvm/test/CodeGen/AMDGPU/ret_jump.ll
M llvm/test/CodeGen/AMDGPU/return-with-successors.mir
M llvm/test/CodeGen/AMDGPU/returnaddress.ll
M llvm/test/CodeGen/AMDGPU/rewrite-mfma-form-spill-cost-reset.ll
M llvm/test/CodeGen/AMDGPU/rewrite-out-arguments-address-space.ll
M llvm/test/CodeGen/AMDGPU/rewrite-out-arguments.ll
M llvm/test/CodeGen/AMDGPU/rewrite-undef-for-phi.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-scale-to-agpr.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store-mir.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
M llvm/test/CodeGen/AMDGPU/rotate-add.ll
M llvm/test/CodeGen/AMDGPU/rotl.i64.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.i64.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32-safe.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-id-allocation.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-buffer-load-mmo-offsets.ll
M llvm/test/CodeGen/AMDGPU/s-cluster-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir
M llvm/test/CodeGen/AMDGPU/s_addk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_cmp_0.ll
M llvm/test/CodeGen/AMDGPU/s_code_end.ll
M llvm/test/CodeGen/AMDGPU/s_movk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_or_b32_transformation.ll
M llvm/test/CodeGen/AMDGPU/s_or_saveexec_xor_combine.mir
M llvm/test/CodeGen/AMDGPU/s_uaddo_usubo_pseudo.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/saddsat.ll
M llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (29) (#209558)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: ea56bc30bdabf00e401422f49e9588f1b5ff5e73
https://github.com/llvm/llvm-project/commit/ea56bc30bdabf00e401422f49e9588f1b5ff5e73
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/same-lds-variable-multiple-use-in-one-phi-node.ll
M llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir
M llvm/test/CodeGen/AMDGPU/save-fp.ll
M llvm/test/CodeGen/AMDGPU/scalar-branch-missing-and-exec.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
M llvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll
M llvm/test/CodeGen/AMDGPU/scalarize-insert-subvector.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-scratch.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-post-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-pre-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-dead-def-join.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/sched-image-sample-post-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-ldsdma-mask.mir
M llvm/test/CodeGen/AMDGPU/sched-no-schedmodel.mir
M llvm/test/CodeGen/AMDGPU/sched-prefer-non-mfma.mir
M llvm/test/CodeGen/AMDGPU/sched-setprio.ll
M llvm/test/CodeGen/AMDGPU/sched.group.classification.mir
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_diff_types.mir
M llvm/test/CodeGen/AMDGPU/schedmodel-dummywrite.mir
M llvm/test/CodeGen/AMDGPU/schedule-addrspaces.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg-crash.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/schedule-avoid-spills.ll
M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier-latency.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
M llvm/test/CodeGen/AMDGPU/schedule-ilp-liveness-tracking.mir
M llvm/test/CodeGen/AMDGPU/schedule-ilp.ll
M llvm/test/CodeGen/AMDGPU/schedule-ilp.mir
M llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll
M llvm/test/CodeGen/AMDGPU/schedule-pending-queue.mir
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-lds.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit-clustering.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit2.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit3.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-misched-max-waves.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-no-unclustered-regions.mir
M llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll
M llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll
M llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll
M llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
M llvm/test/CodeGen/AMDGPU/scheduler-rp-calc-one-successor-two-predecessors-bug.ll
M llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll
M llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
M llvm/test/CodeGen/AMDGPU/scratch-pointer-sink.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdivrem24.ll
M llvm/test/CodeGen/AMDGPU/sdwa-commute.ll
M llvm/test/CodeGen/AMDGPU/sdwa-cse.mir
M llvm/test/CodeGen/AMDGPU/sdwa-gfx9.mir
M llvm/test/CodeGen/AMDGPU/sdwa-op64-test.ll
M llvm/test/CodeGen/AMDGPU/sdwa-ops.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-fail.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-sext.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-wave32.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-wave64.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel-dst.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel-src.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
M llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir
M llvm/test/CodeGen/AMDGPU/sdwa-stack.mir
M llvm/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir
M llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll
M llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-int.ll
M llvm/test/CodeGen/AMDGPU/select-constant-xor.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract-legacy.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.legal.f16.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (30) (#209559)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 9035d06155596c1214f302bef2e60b631d38e73a
https://github.com/llvm/llvm-project/commit/9035d06155596c1214f302bef2e60b631d38e73a
Author: Vijay Kandiah <vkandiah at nvidia.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
A flang/test/Fir/CUDA/cuda-managed-descriptor-component.fir
Log Message:
-----------
[flang][cuda] Size managed globals with descriptor components via LLVM Type (#209577)
When we do `-cuda -gpu=unified` (or `managed`) on a derived type with an
allocatable/pointer component, recent change
https://github.com/llvm/llvm-project/pull/209292 implicitly
attributed the component making lowering place the enclosing
derived-type global
in CUF managed memory. `CUFAddConstructor` then sizes that global via
`getTypeSizeAndAlignmentOrCrash`, which has no case for the descriptor
component
(`!fir.box<...>`) and aborts.
With this change, instead of aborting, we fall back to converting the
global to its LLVM type which
inlines the fixed-size descriptors, and query the data layout.
Commit: e3227da7cdb8173c2df465e443a1dc73c71f017b
https://github.com/llvm/llvm-project/commit/e3227da7cdb8173c2df465e443a1dc73c71f017b
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/crash_scatter_load_reorder.ll
Log Message:
-----------
[SLP] Fix ScatterVectorize reorder desyncing scalars from operands
Record the reorder in ReorderIndices instead of permuting the scatter node's
Scalars, keeping them aligned with the per-lane operand list the scheduler
reads.
Fixes #209444
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209594
Commit: 42b67e529c59b77c6dfac9cc5d2b263e752851f6
https://github.com/llvm/llvm-project/commit/42b67e529c59b77c6dfac9cc5d2b263e752851f6
Author: David Young <davidayoung at meta.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/lit/lit/LitConfig.py
A llvm/utils/lit/tests/unit/LitConfig.py
Log Message:
-----------
[lit] Don't crash in _write_message when getsourcefile() returns None (#206957)
LitConfig._write_message currently derives the file to report a
note()/warning()/ error() against with:
file = os.path.abspath(inspect.getsourcefile(f))
inspect.getsourcefile(f) returns None when the calling frame's source is
not on disk and not in linecache -- for example when lit is packaged
into a zip archive, or when a config is exec'd from a synthetic
filename. In that case os.path.abspath(None) raises TypeError: expected
str, bytes or os.PathLike object, not NoneType, which turns an
informational diagnostic into a fatal config-parse crash.
Fall back to inspect.getfile(f), which returns the frame's co_filename
and is always a str, so the diagnostic is emitted (tagged with
co_filename) instead of crashing. Since all tests normally pass
currently on build bots, this new code should never trigger and only
works as a backup in the case I'm running into on a different test infra
running lit tests.
Add a lit unit test covering the None case.
Assisted with- claude
Commit: e0b4701f2621d2542405830008797e3cf319a3f0
https://github.com/llvm/llvm-project/commit/e0b4701f2621d2542405830008797e3cf319a3f0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/select-i1.ll
M llvm/test/CodeGen/AMDGPU/select-load-to-load-select-ptr-combine.ll
M llvm/test/CodeGen/AMDGPU/select-nsz-known-values-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll
M llvm/test/CodeGen/AMDGPU/select-undef.ll
M llvm/test/CodeGen/AMDGPU/select-vectors.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/select64.ll
M llvm/test/CodeGen/AMDGPU/selectcc-opt.ll
M llvm/test/CodeGen/AMDGPU/selectcc.ll
M llvm/test/CodeGen/AMDGPU/sema-v-unsched-bundle.ll
M llvm/test/CodeGen/AMDGPU/sendmsg-m0-hazard.mir
M llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/AMDGPU/set_kill_i1_for_floation_point_comparison.ll
M llvm/test/CodeGen/AMDGPU/setcc-f64-hi32mask.ll
M llvm/test/CodeGen/AMDGPU/setcc-fneg-constant.ll
M llvm/test/CodeGen/AMDGPU/setcc-limit-load-shrink.ll
M llvm/test/CodeGen/AMDGPU/setcc-multiple-use.ll
M llvm/test/CodeGen/AMDGPU/setcc-opt.ll
M llvm/test/CodeGen/AMDGPU/setcc64.ll
M llvm/test/CodeGen/AMDGPU/seto.ll
M llvm/test/CodeGen/AMDGPU/setuo.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/sgpr-count-graphics.ll
M llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
M llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-incorrect-fi-bookkeeping-bug.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spills-empty-prolog-block.mir
M llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.ll
M llvm/test/CodeGen/AMDGPU/shader-addr64-nonuniform.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll
M llvm/test/CodeGen/AMDGPU/shift-select.ll
M llvm/test/CodeGen/AMDGPU/shl-add-to-add-shl.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shl64_reduce.ll
M llvm/test/CodeGen/AMDGPU/shl64_reduce_flags.ll
M llvm/test/CodeGen/AMDGPU/shlN_add.ll
M llvm/test/CodeGen/AMDGPU/shl_add.ll
M llvm/test/CodeGen/AMDGPU/shl_add_constant.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr_csub.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr_global.ll
M llvm/test/CodeGen/AMDGPU/shl_or.ll
M llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/shrink-carry.mir
M llvm/test/CodeGen/AMDGPU/shrink-fma-f64.mir
M llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-implicit-vcclo.mir
M llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
M llvm/test/CodeGen/AMDGPU/shrink-mad-fma-fake16.mir
M llvm/test/CodeGen/AMDGPU/shrink-mad-fma-gfx10.mir
M llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir
M llvm/test/CodeGen/AMDGPU/shrink-true16.mir
M llvm/test/CodeGen/AMDGPU/shrink-v-cmp-wave32-dead-vcc-lo.mir
M llvm/test/CodeGen/AMDGPU/shufflevector-physreg-copy.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v3i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v4i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (31) (#209560)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 4e092a826f53be3e1948dcf47ad8b56633043b4d
https://github.com/llvm/llvm-project/commit/4e092a826f53be3e1948dcf47ad8b56633043b4d
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M .github/workflows/containers/github-action-ci-windows/Dockerfile
M clang/docs/ReleaseNotes.md
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LiveOrigins.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LoanPropagation.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/MovedLoans.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/Utils.h
M clang/include/clang/Analysis/Analyses/LiveVariables.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/Analysis/LiveVariables.cpp
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
M clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.h
A clang/lib/StaticAnalyzer/Checkers/ReportDanglingPtrDeref.cpp
A clang/test/Analysis/dangling-ptr-deref.cpp
M clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
M clang/test/CodeGen/memcpy-inline-builtin.c
M clang/test/CodeGen/pr9614.c
M clang/test/CodeGenCUDA/device-stub.cu
M clang/test/SemaCXX/concepts-subsumption.cpp
M compiler-rt/lib/asan/AIX/asan.link_with_main_exec.txt
M compiler-rt/lib/asan/asan_malloc_linux.cpp
M compiler-rt/test/asan/TestCases/AIX/vec_malloc_calloc.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/OpenMP/AutomapToTargetData.cpp
M flang/lib/Optimizer/Support/CMakeLists.txt
M flang/lib/Optimizer/Support/InitFIR.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
A flang/test/Analysis/AliasAnalysis/alias-analysis-omp-private-boxed-wsloop.mlir
A flang/test/Analysis/AliasAnalysis/alias-analysis-omp-private-unboxed-wsloop.mlir
A flang/test/Fir/CUDA/cuda-managed-descriptor-component.fir
A flang/test/Lower/OpenMP/declare-target-automap.f90
M flang/test/Transforms/omp-automap-to-target-data.fir
M libc/test/src/sys/mman/linux/posix_madvise_test.cpp
M libcxx/include/__functional/function.h
M libcxx/include/__pstl/backends/libdispatch.h
M libcxx/test/benchmarks/algorithms/min.bench.cpp
M libcxx/test/benchmarks/algorithms/minmax.bench.cpp
M libcxx/test/benchmarks/algorithms/nonmodifying/search_n.bench.cpp
M libcxx/test/std/ranges/range.utility/view.interface/view.interface.pass.cpp
A libunwind/test/.clang-format
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/__init__.py
R lldb/packages/Python/lldbsuite/test/tools/lldb_dap/dap_types.py
R lldb/packages/Python/lldbsuite/test/tools/lldb_dap/lldb_dap_testcase.py
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session.py
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
A lldb/packages/Python/lldbsuite/test/tools/lldb_dap/testcase.py
A lldb/packages/Python/lldbsuite/test/tools/lldb_dap/types.py
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/utils.py
M lldb/source/Plugins/SymbolLocator/SymStore/CMakeLists.txt
M lldb/source/Utility/Policy.cpp
M lldb/test/API/tools/lldb-dap/exception/TestDAP_exception.py
M lldb/test/API/tools/lldb-dap/exception/asan/TestDAP_asan.py
M lldb/test/API/tools/lldb-dap/exception/cpp/TestDAP_exception_cpp.py
M lldb/test/API/tools/lldb-dap/exception/objc/TestDAP_exception_objc.py
M lldb/test/API/tools/lldb-dap/exception/ubsan/TestDAP_ubsan.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_args.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_basic.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_cwd.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_debuggerRoot.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_disableSTDIO.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_environment_with_array.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_environment_with_object.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_extra_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_failing_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_failing_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_invalid_launch_commands_and_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_invalid_program.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_no_lldbinit_flag.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_shellExpandArguments_disabled.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_shellExpandArguments_enabled.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_sourcePath.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection_and_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stopOnEntry.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_terminate_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_termination.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_version.py
M lldb/test/API/tools/lldb-dap/module-event/TestDAP_module_event.py
M lldb/test/API/tools/lldb-dap/module/TestDAP_module.py
M lldb/test/API/tools/lldb-dap/moduleSymbols/TestDAP_moduleSymbols.py
M lldb/test/API/tools/lldb-dap/stackTrace/TestDAP_stackTrace.py
M lldb/test/API/tools/lldb-dap/stackTraceCompilerGeneratedCode/TestDAP_stackTraceCompilerGeneratedCode.py
M lldb/test/API/tools/lldb-dap/stackTraceDisassemblyDisplay/TestDAP_stackTraceDisassemblyDisplay.py
M lldb/test/API/tools/lldb-dap/stackTraceMissingFunctionName/TestDAP_stackTraceMissingFunctionName.py
M lldb/test/API/tools/lldb-dap/stackTraceMissingModule/TestDAP_stackTraceMissingModule.py
M lldb/test/API/tools/lldb-dap/utils/TestDAPUtils_DAPConnection.py
M lldb/test/API/tools/lldb-dap/utils/TestDAPUtils_EventHistory.py
M lldb/test/API/tools/lldb-dap/utils/TestDAPUtils_Types.py
M lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py
M lldb/test/API/tools/lldb-dap/variables/children/TestDAP_variables_children.py
M lldb/tools/lldb-dap/DAPSessionManager.cpp
M llvm/benchmarks/ImmutableSetBuildBM.cpp
M llvm/benchmarks/ImmutableSetIteratorBM.cpp
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/ADT/ImmutableMap.h
M llvm/include/llvm/ADT/ImmutableSet.h
M llvm/include/llvm/Analysis/CGSCCPassManager.h
M llvm/include/llvm/CodeGen/MachinePassManager.h
M llvm/include/llvm/CodeGen/TargetFrameLowering.h
M llvm/include/llvm/IR/PassManager.h
M llvm/include/llvm/IR/PassManagerInternal.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
M llvm/lib/Support/KnownBits.cpp
M llvm/lib/Support/Windows/DynamicLibrary.inc
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/Hexagon/HexagonPatterns.td
M llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrPredicates.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZInstrVector.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sdiv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-udiv.mir
M llvm/test/CodeGen/AArch64/active_lane_mask.ll
M llvm/test/CodeGen/AArch64/fold-sext-in-reg-predicate-fixed-length.ll
M llvm/test/CodeGen/AArch64/get-active-lane-mask-extract.ll
M llvm/test/CodeGen/AArch64/sve-mask-partition.ll
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-014bb.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-cfg-with-self-loop.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-phi-merge-distances.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-acyclic-cfg-with-4-self-loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-11blocks.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-15blocks.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop-a.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/if_else_with_loops_nested_in_2_outer_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/inner_cfg_in_2_nested_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/loop_nested_in_3_outer_loops_complex_cfg.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/nested-loops-with-side-exits-a.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/sequence_2_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/simple-loop-3blocks.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_basic_case.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_do_not_spill_restore_inside_loop.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_common_dominator.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader1.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader2.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader3.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader4.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_keep_spilled_reg_live.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_nested_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_in_common_dominator_and_optimize_restores.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_livethrough_reg.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_value_in_exit_block.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/three-tier-ranking-nested-loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/triple-nested-loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/two-sequential-loops.mir
M llvm/test/CodeGen/AMDGPU/lo16-lo16-physreg-copy-sgpr.mir
M llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
M llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-f64.ll
M llvm/test/CodeGen/AMDGPU/load-global-i1.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i64.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-invariant.ll
M llvm/test/CodeGen/AMDGPU/load-hi16.ll
M llvm/test/CodeGen/AMDGPU/load-lo16.ll
M llvm/test/CodeGen/AMDGPU/load-local-f32-no-ds128.ll
M llvm/test/CodeGen/AMDGPU/load-local-f32.ll
M llvm/test/CodeGen/AMDGPU/load-local-f64.ll
M llvm/test/CodeGen/AMDGPU/load-local-i1.ll
M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
M llvm/test/CodeGen/AMDGPU/load-local-i32.ll
M llvm/test/CodeGen/AMDGPU/load-local-i64.ll
M llvm/test/CodeGen/AMDGPU/load-local-i8.ll
M llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
M llvm/test/CodeGen/AMDGPU/load-local.128.ll
M llvm/test/CodeGen/AMDGPU/load-local.96.ll
M llvm/test/CodeGen/AMDGPU/load-range-metadata-assert.ll
M llvm/test/CodeGen/AMDGPU/load-range-metadata-sign-bits.ll
M llvm/test/CodeGen/AMDGPU/load-saddr-offset-imm.ll
M llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
M llvm/test/CodeGen/AMDGPU/load-store-cnt.ll
M llvm/test/CodeGen/AMDGPU/load-store-opt-addc0.mir
M llvm/test/CodeGen/AMDGPU/load-store-opt-dlc.mir
M llvm/test/CodeGen/AMDGPU/load-store-opt-ds-regclass-constrain.mir
M llvm/test/CodeGen/AMDGPU/load-store-opt-scale-offset.mir
M llvm/test/CodeGen/AMDGPU/load-store-opt-scc.mir
M llvm/test/CodeGen/AMDGPU/load-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/local-64.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/local-atomics.ll
M llvm/test/CodeGen/AMDGPU/local-atomics64.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-memory.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-sort-framerefs.mir
M llvm/test/CodeGen/AMDGPU/local-stack-slot-offset.ll
M llvm/test/CodeGen/AMDGPU/loop-header-align-gfx950.mir
M llvm/test/CodeGen/AMDGPU/loop-idiom.ll
M llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll
M llvm/test/CodeGen/AMDGPU/loop-on-function-argument.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
M llvm/test/CodeGen/AMDGPU/loop_header_nopred.mir
M llvm/test/CodeGen/AMDGPU/lower-brcond-with-xor.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-dead-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-lastuse-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-declaration.ll
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-existing.ll
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll
M llvm/test/CodeGen/AMDGPU/lower-empty-ctor-dtor.ll
M llvm/test/CodeGen/AMDGPU/lower-i1-copies-clear-kills.mir
M llvm/test/CodeGen/AMDGPU/lower-i1-copies-implicit-def-unstructured-loop.mir
M llvm/test/CodeGen/AMDGPU/lower-indirect-lds-references.ll
M llvm/test/CodeGen/AMDGPU/lower-intrinsics-noalias-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-and-module-lds.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-arguments-noalias-call-no-ptr-args.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-lds-constexpr.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-lds-super-align.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-lds.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-merge.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-with-alias-scope.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-with-noalias.ll
M llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics-threshold.ll
M llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-all-indirect-accesses.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr-phi.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-inactive.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-indirect-extern-uses-max-reachable-alignment.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-classify.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-global-scope.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-internal-func.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-internal-multi-user.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-offsets.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-precise-allocate-to-module-struct.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-ambiguous.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-unambiguous.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-used-list.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-zero-size-arr.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds.ll
M llvm/test/CodeGen/AMDGPU/lower-multiple-ctor-dtor.ll
M llvm/test/CodeGen/AMDGPU/lower-noalias-kernargs.ll
M llvm/test/CodeGen/AMDGPU/lower-term-opcodes.mir
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-opt.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/lrint.ll
M llvm/test/CodeGen/AMDGPU/lro-coerce-v4i8-phi-loop.ll
M llvm/test/CodeGen/AMDGPU/lro-phi-samebb-nonlookthrough-store.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/lsr-cost-model-vector-iv.ll
M llvm/test/CodeGen/AMDGPU/lto-lower-module-lds.ll
M llvm/test/CodeGen/AMDGPU/machine-cp-propagation.mir
M llvm/test/CodeGen/AMDGPU/machine-cse-commute-target-flags.mir
M llvm/test/CodeGen/AMDGPU/machine-cse-ssa.mir
M llvm/test/CodeGen/AMDGPU/machine-function-info-cwsr.ll
M llvm/test/CodeGen/AMDGPU/machine-scheduler-rematerialization-scoring.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-revert-slot-monotonicity.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-cycle.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-fence.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-ignorable-exec-use.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-lane-mask.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
M llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir
M llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
M llvm/test/CodeGen/AMDGPU/mad-combine.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/mad_int24.ll
M llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
M llvm/test/CodeGen/AMDGPU/mad_uint24.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-mfma-scale.gfx950.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards.mir
M llvm/test/CodeGen/AMDGPU/mai-inline.ll
M llvm/test/CodeGen/AMDGPU/make-buffer-rsrc-lds-fails.ll
M llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/max3.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/mcexpr-knownbits-assign-crash-gh-issue-110930.ll
M llvm/test/CodeGen/AMDGPU/mcp-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/mcp-implicit-clobber.mir
M llvm/test/CodeGen/AMDGPU/mcp-overlap-after-propagation.mir
M llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
M llvm/test/CodeGen/AMDGPU/med3-knownbits.ll
M llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll
M llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
M llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scoped-aa.ll
M llvm/test/CodeGen/AMDGPU/memcpy_const_compare.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/memmove-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-av-none.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-av-unknown.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-barriers-mmra.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-barriers.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-global.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-local.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-addrspace.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-syncscope.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-lds-dma-volatile-and-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.mir
M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/merge-buffer-gfx12.mir
M llvm/test/CodeGen/AMDGPU/merge-buffer.mir
M llvm/test/CodeGen/AMDGPU/merge-consecutive-wait-alus.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-saddr-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-image-load-gfx10.mir
M llvm/test/CodeGen/AMDGPU/merge-image-load-gfx11.mir
M llvm/test/CodeGen/AMDGPU/merge-image-load-gfx12.mir
M llvm/test/CodeGen/AMDGPU/merge-image-load.mir
M llvm/test/CodeGen/AMDGPU/merge-image-sample-gfx10.mir
M llvm/test/CodeGen/AMDGPU/merge-image-sample-gfx11.mir
M llvm/test/CodeGen/AMDGPU/merge-image-sample-gfx12.mir
M llvm/test/CodeGen/AMDGPU/merge-image-sample.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir
M llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll
M llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.mir
M llvm/test/CodeGen/AMDGPU/merge-s-load.mir
M llvm/test/CodeGen/AMDGPU/merge-sbuffer-load.mir
M llvm/test/CodeGen/AMDGPU/merge-store-crash.ll
M llvm/test/CodeGen/AMDGPU/merge-store-usedef.ll
M llvm/test/CodeGen/AMDGPU/merge-stores.ll
M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx10.mir
M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx11.mir
M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx12.mir
M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx9.mir
M llvm/test/CodeGen/AMDGPU/merged-bfx-opt.ll
M llvm/test/CodeGen/AMDGPU/mesa3d.ll
M llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-convergent.mir
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select-gfx942.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/min-waves-per-eu-not-respected.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/min3.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
M llvm/test/CodeGen/AMDGPU/mir-dynamic-vgpr-block-size-roundtrip.mir
M llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir
M llvm/test/CodeGen/AMDGPU/misched-into-wmma-hazard-shadow.mir
M llvm/test/CodeGen/AMDGPU/misched-killflags.mir
M llvm/test/CodeGen/AMDGPU/missing-store.ll
M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
M llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll
M llvm/test/CodeGen/AMDGPU/mixed_wave32_wave64.ll
M llvm/test/CodeGen/AMDGPU/mmo-target-flags-folding.ll
M llvm/test/CodeGen/AMDGPU/mmra.ll
M llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus.mir
M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/mode-register.mir
M llvm/test/CodeGen/AMDGPU/modf-constant-fold.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll
M llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu-flat.mir
M llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-absdiff.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-lshl_add.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-lshlrev.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll
M llvm/test/CodeGen/AMDGPU/movreld-bug.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
M llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
M llvm/test/CodeGen/AMDGPU/mubuf.ll
M llvm/test/CodeGen/AMDGPU/mul.i16.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multi-call-resource-usage-mcexpr.ll
M llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
M llvm/test/CodeGen/AMDGPU/multi-dword-vgpr-spill.ll
M llvm/test/CodeGen/AMDGPU/multi-use-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/naked-fn-with-frame-pointer.ll
M llvm/test/CodeGen/AMDGPU/nand.ll
M llvm/test/CodeGen/AMDGPU/narrow_math_for_and.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/neg_ashr64_reduce.ll
M llvm/test/CodeGen/AMDGPU/neighboring-mfma-padding.mir
M llvm/test/CodeGen/AMDGPU/nested-calls.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/no-bundle-asm.ll
M llvm/test/CodeGen/AMDGPU/no-corresponding-integer-type.ll
M llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir
M llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
M llvm/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll
M llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir
M llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
M llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
M llvm/test/CodeGen/AMDGPU/nofpclass-call.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/noop-shader-O0.ll
M llvm/test/CodeGen/AMDGPU/nop-data.ll
M llvm/test/CodeGen/AMDGPU/nor-divergent-lanemask.ll
M llvm/test/CodeGen/AMDGPU/nor.ll
M llvm/test/CodeGen/AMDGPU/nsa-reassign.ll
M llvm/test/CodeGen/AMDGPU/nsa-reassign.mir
M llvm/test/CodeGen/AMDGPU/nsa-vmem-hazard.mir
M llvm/test/CodeGen/AMDGPU/object-linking-local-resources.ll
M llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-and-hostcall.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-pipeline.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-unsupported.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf.ll
M llvm/test/CodeGen/AMDGPU/operand-folding.ll
M llvm/test/CodeGen/AMDGPU/operand-spacing.ll
M llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness-wave32.mir
M llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness.mir
M llvm/test/CodeGen/AMDGPU/opt-vgpr-live-range-verifier-error.mir
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.mir
M llvm/test/CodeGen/AMDGPU/optimize-ds-bvh-stack-pre-ra.ll
M llvm/test/CodeGen/AMDGPU/optimize-exec-copies-extra-insts-after-copy.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-alloc-failure.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-no-fold-exec-copy.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-masking-strip-terminator-bits.mir
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/or3.ll
M llvm/test/CodeGen/AMDGPU/overlapping-tuple-copy-implicit-op-failure.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/packed-dependencies.mir
M llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-bf16.ll
M llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/packed-op-sel.ll
M llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable-dvgpr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-dvgpr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx950.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.6-dvgpr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.6.ll
M llvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/pal-userdata-regs.ll
M llvm/test/CodeGen/AMDGPU/partial-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/peephole-fold-imm-multi-use.mir
M llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
M llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir
M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir
M llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
M llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir
M llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
M llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
M llvm/test/CodeGen/AMDGPU/perfhint.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permlane16_opsel.ll
M llvm/test/CodeGen/AMDGPU/permlane16_var-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/phi-av-pressure.ll
M llvm/test/CodeGen/AMDGPU/phi-elim-mli-available.mir
M llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
M llvm/test/CodeGen/AMDGPU/phys-partial-liveness.mir
M llvm/test/CodeGen/AMDGPU/pk-lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/pk_max_f16_literal.ll
M llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
M llvm/test/CodeGen/AMDGPU/post-ra-sched-reset.mir
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
M llvm/test/CodeGen/AMDGPU/postra-bundle-vimage-vsample-gfx12.mir
M llvm/test/CodeGen/AMDGPU/postra-machine-sink-livein-subrange.mir
M llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir
M llvm/test/CodeGen/AMDGPU/postra-norename.mir
M llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
M llvm/test/CodeGen/AMDGPU/postra-sink-update-dependency.mir
M llvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir
M llvm/test/CodeGen/AMDGPU/pr51516.mir
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-IR-lowering.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs-IR-lowering.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
M llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/print-pipeline-passes.ll
M llvm/test/CodeGen/AMDGPU/printf-defined.ll
M llvm/test/CodeGen/AMDGPU/printf-existing-format-strings.ll
M llvm/test/CodeGen/AMDGPU/private-access-no-objects.ll
M llvm/test/CodeGen/AMDGPU/private-function.ll
M llvm/test/CodeGen/AMDGPU/prologue-epilogue-markers.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-allocation.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-bitcast-function.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-cfg.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-globals.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-invariant-markers.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-lifetime.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-loadstores.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-max-regs.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-mem-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-multidim.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-negative-index.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-non-byte-sizes.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-non-constant-index.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-placeholder-replacement.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-pointer-array.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-proper-value-replacement.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-scoring.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-strip-abi-opt-attributes.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-subvecs.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-constantexpr-use.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-icmp.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-phi.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-unhandled-intrinsic.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-use-after-erase.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-user-mult.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep-of-gep.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vgpr-ratio.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-volatile.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx10.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx90a.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir
M llvm/test/CodeGen/AMDGPU/promote-vect3-load.ll
M llvm/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll
M llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
M llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag-mubuf.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag-undef-poison.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
M llvm/test/CodeGen/AMDGPU/ptrmask.ll
M llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-register.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll
M llvm/test/CodeGen/AMDGPU/read-write-register-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/read_register.ll
M llvm/test/CodeGen/AMDGPU/readcyclecounter.ll
M llvm/test/CodeGen/AMDGPU/readlane_exec0.mir
M llvm/test/CodeGen/AMDGPU/readsteadycounter.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll
M llvm/test/CodeGen/AMDGPU/recursion.ll
M llvm/test/CodeGen/AMDGPU/recursive-resource-usage-mcexpr.ll
M llvm/test/CodeGen/AMDGPU/recursive_global_initializer.ll
M llvm/test/CodeGen/AMDGPU/reduce-build-vec-ext-to-ext-build-vec.ll
M llvm/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll
M llvm/test/CodeGen/AMDGPU/reduction.ll
M llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
M llvm/test/CodeGen/AMDGPU/reg-coalescer-subreg-liveness.mir
M llvm/test/CodeGen/AMDGPU/reg-sequence-like-v-pk-mov-b32.mir
M llvm/test/CodeGen/AMDGPU/regalloc-fail-unsatisfiable-overlapping-tuple-hints.mir
M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
M llvm/test/CodeGen/AMDGPU/regalloc-fast-dont-drop-subreg-index-issue61134.mir
M llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.mir
M llvm/test/CodeGen/AMDGPU/regalloc-illegal-eviction-assert.ll
M llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir
M llvm/test/CodeGen/AMDGPU/regalloc-sgpr128-partial-def.mir
M llvm/test/CodeGen/AMDGPU/regalloc-spill-wmma-scale.ll
M llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-64-bit-only-regs.mir
M llvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir
M llvm/test/CodeGen/AMDGPU/register-coalescer--set-undef-full-reg-use-implicit-def-erase-issue109249.mir
M llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
M llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll
M llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
M llvm/test/CodeGen/AMDGPU/reject-agpr-usage-before-gfx908.ll
M llvm/test/CodeGen/AMDGPU/rel32.ll
M llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir
M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12-dvgpr.mir
M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12.mir
M llvm/test/CodeGen/AMDGPU/release-vgprs-spill.ll
M llvm/test/CodeGen/AMDGPU/release-vgprs.mir
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
M llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll
M llvm/test/CodeGen/AMDGPU/remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir
M llvm/test/CodeGen/AMDGPU/remat-smrd.mir
M llvm/test/CodeGen/AMDGPU/remat-sop.mir
M llvm/test/CodeGen/AMDGPU/remat-through-copy.mir
M llvm/test/CodeGen/AMDGPU/remat-vop.mir
M llvm/test/CodeGen/AMDGPU/remove-incompatible-extended-image-insts.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-functions.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-gws.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-s-time.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave32-feature.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave64-feature.ll
M llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
M llvm/test/CodeGen/AMDGPU/remove-not-short-exec-branch-on-unconditional-jump.mir
M llvm/test/CodeGen/AMDGPU/remove-register-flags.mir
M llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-gpr-idx-mode.mir
M llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-special-instructions.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-unused-lanes.ll
M llvm/test/CodeGen/AMDGPU/reorder-stores.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/replace-store-of-insert-load.ll
M llvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/required-export-priority.ll
M llvm/test/CodeGen/AMDGPU/required-export-priority.mir
M llvm/test/CodeGen/AMDGPU/reserved-reg-in-clause.mir
M llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
M llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir
M llvm/test/CodeGen/AMDGPU/resource-usage-dead-function.ll
M llvm/test/CodeGen/AMDGPU/resource-usage-pal.ll
M llvm/test/CodeGen/AMDGPU/ret.ll
M llvm/test/CodeGen/AMDGPU/ret_jump.ll
M llvm/test/CodeGen/AMDGPU/return-with-successors.mir
M llvm/test/CodeGen/AMDGPU/returnaddress.ll
M llvm/test/CodeGen/AMDGPU/rewrite-mfma-form-spill-cost-reset.ll
M llvm/test/CodeGen/AMDGPU/rewrite-out-arguments-address-space.ll
M llvm/test/CodeGen/AMDGPU/rewrite-out-arguments.ll
M llvm/test/CodeGen/AMDGPU/rewrite-undef-for-phi.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-scale-to-agpr.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store-mir.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
M llvm/test/CodeGen/AMDGPU/rotate-add.ll
M llvm/test/CodeGen/AMDGPU/rotl.i64.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.i64.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32-safe.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-id-allocation.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-buffer-load-mmo-offsets.ll
M llvm/test/CodeGen/AMDGPU/s-cluster-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir
M llvm/test/CodeGen/AMDGPU/s_addk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_cmp_0.ll
M llvm/test/CodeGen/AMDGPU/s_code_end.ll
M llvm/test/CodeGen/AMDGPU/s_movk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_or_b32_transformation.ll
M llvm/test/CodeGen/AMDGPU/s_or_saveexec_xor_combine.mir
M llvm/test/CodeGen/AMDGPU/s_uaddo_usubo_pseudo.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/saddsat.ll
M llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
M llvm/test/CodeGen/AMDGPU/same-lds-variable-multiple-use-in-one-phi-node.ll
M llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir
M llvm/test/CodeGen/AMDGPU/save-fp.ll
M llvm/test/CodeGen/AMDGPU/scalar-branch-missing-and-exec.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
M llvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll
M llvm/test/CodeGen/AMDGPU/scalarize-insert-subvector.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-scratch.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-post-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-pre-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-dead-def-join.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/sched-image-sample-post-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-ldsdma-mask.mir
M llvm/test/CodeGen/AMDGPU/sched-no-schedmodel.mir
M llvm/test/CodeGen/AMDGPU/sched-prefer-non-mfma.mir
M llvm/test/CodeGen/AMDGPU/sched-setprio.ll
M llvm/test/CodeGen/AMDGPU/sched.group.classification.mir
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_diff_types.mir
M llvm/test/CodeGen/AMDGPU/schedmodel-dummywrite.mir
M llvm/test/CodeGen/AMDGPU/schedule-addrspaces.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg-crash.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/schedule-avoid-spills.ll
M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier-latency.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
M llvm/test/CodeGen/AMDGPU/schedule-ilp-liveness-tracking.mir
M llvm/test/CodeGen/AMDGPU/schedule-ilp.ll
M llvm/test/CodeGen/AMDGPU/schedule-ilp.mir
M llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll
M llvm/test/CodeGen/AMDGPU/schedule-pending-queue.mir
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-lds.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit-clustering.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit2.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit3.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-misched-max-waves.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-no-unclustered-regions.mir
M llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll
M llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll
M llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll
M llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
M llvm/test/CodeGen/AMDGPU/scheduler-rp-calc-one-successor-two-predecessors-bug.ll
M llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll
M llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
M llvm/test/CodeGen/AMDGPU/scratch-pointer-sink.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdivrem24.ll
M llvm/test/CodeGen/AMDGPU/sdwa-commute.ll
M llvm/test/CodeGen/AMDGPU/sdwa-cse.mir
M llvm/test/CodeGen/AMDGPU/sdwa-gfx9.mir
M llvm/test/CodeGen/AMDGPU/sdwa-op64-test.ll
M llvm/test/CodeGen/AMDGPU/sdwa-ops.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-fail.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-sext.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-wave32.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-wave64.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel-dst.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel-src.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
M llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir
M llvm/test/CodeGen/AMDGPU/sdwa-stack.mir
M llvm/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir
M llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll
M llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-int.ll
M llvm/test/CodeGen/AMDGPU/select-constant-xor.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract-legacy.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.legal.f16.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/select-i1.ll
M llvm/test/CodeGen/AMDGPU/select-load-to-load-select-ptr-combine.ll
M llvm/test/CodeGen/AMDGPU/select-nsz-known-values-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll
M llvm/test/CodeGen/AMDGPU/select-undef.ll
M llvm/test/CodeGen/AMDGPU/select-vectors.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/select64.ll
M llvm/test/CodeGen/AMDGPU/selectcc-opt.ll
M llvm/test/CodeGen/AMDGPU/selectcc.ll
M llvm/test/CodeGen/AMDGPU/sema-v-unsched-bundle.ll
M llvm/test/CodeGen/AMDGPU/sendmsg-m0-hazard.mir
M llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/AMDGPU/set_kill_i1_for_floation_point_comparison.ll
M llvm/test/CodeGen/AMDGPU/setcc-f64-hi32mask.ll
M llvm/test/CodeGen/AMDGPU/setcc-fneg-constant.ll
M llvm/test/CodeGen/AMDGPU/setcc-limit-load-shrink.ll
M llvm/test/CodeGen/AMDGPU/setcc-multiple-use.ll
M llvm/test/CodeGen/AMDGPU/setcc-opt.ll
M llvm/test/CodeGen/AMDGPU/setcc64.ll
M llvm/test/CodeGen/AMDGPU/seto.ll
M llvm/test/CodeGen/AMDGPU/setuo.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/sgpr-count-graphics.ll
M llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
M llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-incorrect-fi-bookkeeping-bug.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spills-empty-prolog-block.mir
M llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.ll
M llvm/test/CodeGen/AMDGPU/shader-addr64-nonuniform.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll
M llvm/test/CodeGen/AMDGPU/shift-select.ll
M llvm/test/CodeGen/AMDGPU/shl-add-to-add-shl.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shl64_reduce.ll
M llvm/test/CodeGen/AMDGPU/shl64_reduce_flags.ll
M llvm/test/CodeGen/AMDGPU/shlN_add.ll
M llvm/test/CodeGen/AMDGPU/shl_add.ll
M llvm/test/CodeGen/AMDGPU/shl_add_constant.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr_csub.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr_global.ll
M llvm/test/CodeGen/AMDGPU/shl_or.ll
M llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/shrink-carry.mir
M llvm/test/CodeGen/AMDGPU/shrink-fma-f64.mir
M llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-implicit-vcclo.mir
M llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
M llvm/test/CodeGen/AMDGPU/shrink-mad-fma-fake16.mir
M llvm/test/CodeGen/AMDGPU/shrink-mad-fma-gfx10.mir
M llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir
M llvm/test/CodeGen/AMDGPU/shrink-true16.mir
M llvm/test/CodeGen/AMDGPU/shrink-v-cmp-wave32-dead-vcc-lo.mir
M llvm/test/CodeGen/AMDGPU/shufflevector-physreg-copy.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v3i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v4i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir
M llvm/test/CodeGen/Hexagon/fminmax-v67.ll
M llvm/test/CodeGen/Hexagon/fminmax.ll
A llvm/test/CodeGen/RISCV/xqcilo-xqcilia-frame-index.ll
A llvm/test/CodeGen/SystemZ/vec-strict-pseudo-max.ll
A llvm/test/CodeGen/SystemZ/vec-strict-pseudo-min.ll
M llvm/test/CodeGen/SystemZ/zos-ppa2.ll
M llvm/test/CodeGen/X86/bitcnt-load-with-cmov.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt-i64.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt-i64.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt.ll
M llvm/test/CodeGen/X86/udiv_fix.ll
M llvm/test/CodeGen/X86/udiv_fix_sat.ll
M llvm/test/Transforms/InstCombine/known-bits.ll
A llvm/test/Transforms/InstCombine/shuffle-cmp-cast-preserve-flags.ll
A llvm/test/Transforms/InstCombine/udiv-isknownnegative.ll
M llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll
M llvm/test/Transforms/LoopVectorize/AArch64/alias-mask-uniforms.ll
M llvm/test/Transforms/LoopVectorize/AArch64/alias-mask.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-incomplete-chains.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/pr41179.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing-alias-mask.ll
M llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-alias-mask.ll
M llvm/test/Transforms/LoopVectorize/WebAssembly/induction-branch-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/fold-tail-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-opaque-pointers.ll
M llvm/test/Transforms/LoopVectorize/X86/optsize.ll
M llvm/test/Transforms/LoopVectorize/X86/pr48340.ll
M llvm/test/Transforms/LoopVectorize/X86/pr72969.ll
M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/alias-mask-data-tail-folding-style.ll
M llvm/test/Transforms/LoopVectorize/alias-mask-needs-freeze.ll
M llvm/test/Transforms/LoopVectorize/alias-mask-small-index.ll
M llvm/test/Transforms/LoopVectorize/alias-mask.ll
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/hoist-and-sink-mem-ops-with-invariant-pointers.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-different-insert-position.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
M llvm/test/Transforms/LoopVectorize/metadata.ll
M llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/pr45259.ll
M llvm/test/Transforms/LoopVectorize/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll
M llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/non-power-of-2-with-adjusted-gathers.ll
M llvm/test/Transforms/SLPVectorizer/X86/control-deps-schedule-data-recalculate.ll
A llvm/test/Transforms/SLPVectorizer/X86/crash_scatter_load_reorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-root-multiuse-same-opcode.ll
A llvm/test/tools/llvm-reduce/reduce-instructions-x86-amx.ll
A llvm/test/tools/llvm-reduce/reduce-operands-to-args-x86-amx.ll
A llvm/test/tools/llvm-reduce/reduce-operands-x86-amx.ll
M llvm/tools/llvm-mc/Disassembler.cpp
M llvm/tools/llvm-mc/Disassembler.h
M llvm/tools/llvm-mc/llvm-mc.cpp
M llvm/tools/llvm-reduce/deltas/ReduceInstructions.cpp
M llvm/tools/llvm-reduce/deltas/ReduceOperands.cpp
M llvm/tools/llvm-reduce/deltas/ReduceOperandsToArgs.cpp
M llvm/unittests/ADT/ImmutableSetTest.cpp
M llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
M llvm/utils/gn/secondary/clang-tools-extra/clang-doc/BUILD.gn
R llvm/utils/gn/secondary/clang-tools-extra/clang-doc/markdown/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/unittests/clang-doc/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysis/Analyses/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/ScalableStaticAnalysis/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Passes/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn
M llvm/utils/lit/lit/LitConfig.py
A llvm/utils/lit/tests/unit/LitConfig.py
M mlir/include/mlir/Target/LLVMIR/Dialect/All.h
R mlir/include/mlir/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.h
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/lib/Target/LLVMIR/CMakeLists.txt
M mlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt
R mlir/lib/Target/LLVMIR/Dialect/OpenACC/CMakeLists.txt
R mlir/lib/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
M mlir/test/Dialect/XeGPU/propagate-layout.mlir
M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F4.mlir
M mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-host.mlir
R mlir/test/Target/LLVMIR/openacc-llvm.mlir
M mlir/utils/generate-test-checks.py
M offload/test/offloading/fortran/declare-target-automap.f90
M orc-rt/test/unit/ErrorTest.cpp
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/Support/BUILD.bazel
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/Transforms/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Rebase, fixes
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/53da48fbaa9e...4e092a826f53
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