[all-commits] [llvm/llvm-project] 405861: [Hexagon] Register MachineKCFILegacy pass in LLVMI...
Ziqing Luo via All-commits
all-commits at lists.llvm.org
Tue Jul 14 13:39:22 PDT 2026
Branch: refs/heads/users/ziqingluo/PR-179151882
Home: https://github.com/llvm/llvm-project
Commit: 4058610aecb6d261f3ea1777dd5c0e531a5cc17e
https://github.com/llvm/llvm-project/commit/4058610aecb6d261f3ea1777dd5c0e531a5cc17e
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
Log Message:
-----------
[Hexagon] Register MachineKCFILegacy pass in LLVMInitializeHexagonTarget (#209245)
Hexagon's target-init function never called
initializeMachineKCFILegacyPass(PR), unlike X86, ARM, AArch64, and
RISCV. Since PassRegistry is process-wide and each target's init
function registers passes as a side effect when linked into the same
binary, whether test/CodeGen/Hexagon/kcfi.ll passed depended on whether
some other target providing that registration was also built into llc,
rather than on Hexagon's own configuration.
Commit: e2c8fa09872cfacba7f73599dcf8557971ebe865
https://github.com/llvm/llvm-project/commit/e2c8fa09872cfacba7f73599dcf8557971ebe865
Author: Amy Kwan <amy.kwan1 at ibm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Object/ArchiveWriter.cpp
A llvm/test/tools/llvm-ar/zos-write.test
M llvm/tools/llvm-ar/llvm-ar.cpp
Log Message:
-----------
[SystemZ][z/OS] Add z/OS archive writing support (#200087)
This patch implement z/OS archive writing in ArchiveWriter and adds the
option `llvm-ar --format=zos`.
Moreover, This patch teaches `llvm-ar` to emit z/OS-compatible archives
by:
- Detecting GOFF object files as z/OS members
- Writing z/OS member headers and archive magic
- Converting archive headers and symbol-name string tables to EBCDIC
- Emitting z/OS symbol table entries
- Using EBCDIC newline padding bytes
- Add a z/OS-specific workaround for empty symbol tables by emitting a
dummy blank symbol to satisfy binder requirements.
Commit: 6e5c97d417d1ec16c095aba6630995406dde1d87
https://github.com/llvm/llvm-project/commit/6e5c97d417d1ec16c095aba6630995406dde1d87
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt/AllocAction.h
R orc-rt/lib/executor/AllocAction.cpp
M orc-rt/lib/executor/CMakeLists.txt
M orc-rt/lib/executor/SimpleNativeMemoryMap.cpp
M orc-rt/test/unit/AllocActionTest.cpp
M orc-rt/test/unit/CommonTestUtils.h
Log Message:
-----------
[orc-rt] Hoist run-alloc-actions functions, add error reporting. (#209356)
Hoist runFinalizeActions and runDeallocActions into AllocAction.h and
turn them into function templates with a ReportErrorFn argument that
enables error reporting. This is used to report errors from dealloc
actions.
Update SimpleNativeMemoryMap to direct such errors to the Session via
ReportErrorsViaSession.
Add unit tests covering the new error-reporting paths.
Commit: 0c19355a6b3e88fcb98a398845735c6ae19a2142
https://github.com/llvm/llvm-project/commit/0c19355a6b3e88fcb98a398845735c6ae19a2142
Author: Nicolas Miller <nicolas.pierre.miller at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
M llvm/test/CodeGen/Hexagon/autohvx/conv-fp-fp.ll
Log Message:
-----------
[Hexagon] Fix fpround fp32 -> fp16 pattern (#199704)
The pattern was passing hi and lo in the wrong order to `vcvt` causing
the final output after `vdeal` to be incorrect.
Commit: 5b3fbf852e5d72d3a78ff4646a8ddad3c8d50536
https://github.com/llvm/llvm-project/commit/5b3fbf852e5d72d3a78ff4646a8ddad3c8d50536
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/include/lldb/Core/PluginManager.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/Core/PluginManager.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/OperatingSystemPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/OperatingSystemPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedBreakpointPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedFrameProviderPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedFramePythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedFramePythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedHookPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPlatformPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPlanPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPythonInterface.h
M lldb/test/Shell/Commands/command-scripting-extension-list.test
Log Message:
-----------
[lldb] Expand ScriptedExtension coverage across scripted Python interfaces (NFC) (#209307)
Commit: 795a5a9a19bb2b356d82a46426d95f245d1d0049
https://github.com/llvm/llvm-project/commit/795a5a9a19bb2b356d82a46426d95f245d1d0049
Author: Vijay Kandiah <vkandiah at nvidia.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Lower/CUDA/cuda-implicit-managed-alloc.cuf
Log Message:
-----------
[flang][cuda] Implicitly attribute allocatables/pointers under -gpu=unified (#209292)
When `-gpu=unified` is in effect, allocatables and pointers with no
explicit CUDA data attribute were left with no data attribute, and were allocated
as ordinary host memory. Under unified memory, such objects must be
reachable from the device; leaving them as plain host allocations makes device kernels
fault on systems that do not provide transparent host-memory access.
The existing code here already assigned `Managed` implicitly under
`-gpu=managed` (when CUDA Fortran is enabled). This extends that handling to
`-gpu=unified`: prefer the `Unified` attribute where it is legal (host subprogram, main
program, or derived-type component) so generic resolution still selects the unified
specific, and fall back to `Managed` elsewhere (module scope, device
subprograms). Both attributes route allocation through the same managed
allocator, so this keeps the allocation device-accessible while avoiding
spurious `ATTRIBUTES(UNIFIED)` legality errors.
The attribution stays gated on CUDA Fortran being enabled, preserving
the existing behavior for non-CUDA-Fortran translation units.
Commit: b15f9326d21cbd05463fcb34d989bae95982cc9b
https://github.com/llvm/llvm-project/commit/b15f9326d21cbd05463fcb34d989bae95982cc9b
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
A flang/test/Evaluate/fold-kind-logical.f90
A flang/test/Evaluate/fold-kind-substring.f90
A flang/test/Evaluate/fold-kind-zero-size.f90
M flang/test/Evaluate/logical-args.f90
A flang/test/Lower/HLFIR/array-ctor-character-kind.f90
A flang/test/Semantics/modfile84.F90
A flang/test/Semantics/substring-literal-kind.f90
Log Message:
-----------
[flang] Add kind-preservation regression tests (#208760)
These tests pin currently-correct behaviors where the KIND type
parameter of a result must be preserved by constant folding, semantics,
and lowering. They all pass at head; their purpose is to guard against
silent kind loss during future refactoring of the Evaluate library's
type-parameterized machinery (see the discussion on PR #206907, where an
experimental rewrite passed check-flang while dropping kinds in several
places).
Folded LOGICAL operations: `.NOT./.AND./.OR./.EQV./.NEQV.` keep their
operand kind; ANY/ALL/PARITY and logical DOT_PRODUCT results have the
MASK/argument kind (F2023 16.9.14/16.9.16/16.9.148), including for empty
masks where there is no element value to take a kind from; MERGE and
TRANSFER keep the TSOURCE/MOLD kind; STORAGE_SIZE of folded
non-default-kind logicals folds to the right value; the default BOUNDARY
fill element of a folded EOSHIFT has the array's kind; relational
results are default logical regardless of operand kinds; and generic
resolution over LOGICAL kinds is unchanged by folding
(flang/test/Evaluate/fold-kind-logical.f90 and an extension of
flang/test/Evaluate/logical-args.f90).
Empty typed array constructors and zero-size PACK/SPREAD/RESHAPE/UNPACK
results keep the kind (and character length) of their type-spec (F2023
7.8), including across a module file into a separately compiled
consumer, and empty non-default-kind character array constructors lower
with the correct `!fir.char` element type
(flang/test/Evaluate/fold-kind-zero-size.f90,
flang/test/Semantics/modfile84.F90,
flang/test/Lower/HLFIR/array-ctor-character-kind.f90).
A substring of a character literal has the kind of the literal (F2023
9.4.1): KIND() and LEN() fold correctly, and concatenation with a
same-kind literal is accepted
(flang/test/Evaluate/fold-kind-substring.f90,
flang/test/Semantics/substring-literal-kind.f90).
Assisted-by: AI
Commit: b959f7886f0fdbf8f683c11e945cca3f1afca36a
https://github.com/llvm/llvm-project/commit/b959f7886f0fdbf8f683c11e945cca3f1afca36a
Author: Sean Perry <perry at ca.ibm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/lit/lit/builtin_commands/cat.py
Log Message:
-----------
Add text file support for z/OS back in (#209259)
Support for auto conversion of text files was added to cat.py in
https://github.com/llvm/llvm-project/pull/90128. That was accidently
removed in https://github.com/llvm/llvm-project/pull/204711 while
removing some old win32 code. This adds the z/OS support back in.
Commit: 67f5b53995d3e8ce0b062ea73be1fbb9186d6b30
https://github.com/llvm/llvm-project/commit/67f5b53995d3e8ce0b062ea73be1fbb9186d6b30
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lld/test/ELF/retain-symbols-file.s
Log Message:
-----------
[ELF,test] Improve retain-symbols-file.s (#209366)
Commit: f18e59a195eb253573a26c118d3a09a83acb73ca
https://github.com/llvm/llvm-project/commit/f18e59a195eb253573a26c118d3a09a83acb73ca
Author: Thurston Dang <thurston at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_nolibc.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_dl.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_dl.h
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/tsan/go/buildgo.sh
M compiler-rt/test/sanitizer_common/TestCases/Linux/dlopen_image_base.c
Log Message:
-----------
Revert "[compiler-rt] [sanitizer_common] Fix SIGSEGV in ForEachMappedRegion for DSOs with custom image base" (#209371)
Reverts llvm/llvm-project#206299 due to buildbot breakage
(https://github.com/llvm/llvm-project/pull/206299#issuecomment-4964804971)
Commit: c4edd8bde42cf6b1a25839601b75f3865bba6976
https://github.com/llvm/llvm-project/commit/c4edd8bde42cf6b1a25839601b75f3865bba6976
Author: ejose02 <ejose at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/Object/IRSymtab.h
A llvm/test/Object/X86/irsymtab-large-common.ll
M llvm/test/Object/X86/irsymtab.ll
Log Message:
-----------
[Object] Fix irsymtab CommonSize truncation past 4 GiB (#209085)
Fixes #208669
Issue :
With -flto, Fortran COMMON blocks larger than 4 GiB were silently
miscompiled. The linker reserved only the low 32 bits of the declared
size, so stores past that boundary could segfault with no diagnostic.
Root Cause :
storage::Uncommon::CommonSize in the LTO irsymtab was stored as 32-bit
(Word). Sizes above 2^32 bytes were truncated when the symtab was
written and read back at link time.
Fix :
Widen CommonSize to 64-bit and bump irsymtab format version to 4. Added
test to verify symtab records the full size.
Commit: a527c6f0bc9644cf8b13a9fb5a43e81257bedba6
https://github.com/llvm/llvm-project/commit/a527c6f0bc9644cf8b13a9fb5a43e81257bedba6
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/lib/executor/Logging.cpp
Log Message:
-----------
[orc-rt] Statically check logging category/level name array sizes. (#209372)
Add static_asserts to trigger compilation failure if the sizes of these
arrays don't match their respective enum/macro value ranges.
Commit: a70234b00d12aaa7723eb2ae5e8efe3348aeeb37
https://github.com/llvm/llvm-project/commit/a70234b00d12aaa7723eb2ae5e8efe3348aeeb37
Author: Sergey Shcherbinin <sscherbinin at nvidia.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROpsSupport.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/FunctionAttr.cpp
A flang/test/Driver/function-attr-readonly.f90
M flang/test/Lower/HLFIR/structure-constructor.f90
M flang/test/Lower/Intrinsics/dconjg.f90
M flang/test/Lower/Intrinsics/dimag.f90
M flang/test/Lower/Intrinsics/dreal.f90
M flang/test/Lower/OpenMP/optional-argument-map.f90
M flang/test/Lower/OpenMP/wsloop-unstructured.f90
M flang/test/Lower/achar.f90
M flang/test/Lower/arguments.f90
M flang/test/Lower/call-copy-in-out.f90
M flang/test/Lower/dispatch.f90
A flang/test/Lower/dummy-argument-readonly.f90
M flang/test/Lower/polymorphic-temp.f90
M flang/test/Lower/polymorphic.f90
M flang/test/Lower/select-type.f90
M flang/test/Lower/unsigned-ops.f90
M flang/test/Lower/volatile1.f90
A flang/test/Transforms/function-attrs-readonly.fir
Log Message:
-----------
[flang] Propagate INTENT(IN) dummy arguments as readonly (#207732)
Mark eligible `INTENT(IN)` dummy data objects with a `fir.read_only`
argument attribute during lowering, and teach `FunctionAttr` to
translate the marker to LLVM `readonly` for reference arguments when
optimizing for speed.
LLVM FunctionAttrs can infer `readonly` later in the pipeline, but this
happens too late for IPSCCP function specialization.
`FunctionSpecializer::promoteConstantStackValues` requires
`onlyReadsMemory()` before promoting constant by-reference scalar
arguments. Providing `readonly` satisfies this check and allows these
arguments to be promoted, enabling function specialization, including in
non-LTO builds.
For direct-data arguments, restrict propagation to by-reference
non-character intrinsic scalars. Ordinary arrays and derived-type
arguments are excluded because compiler-generated copy-out may write
back through a forwarded dummy argument. LLVM `readonly` does not permit
such writes, even when the stored value is unchanged.
`INTENT(IN)` `POINTER` and `ALLOCATABLE` dummies are supported with
shallow descriptor semantics: `readonly` protects the descriptor
storage, but does not imply that data addressed by the descriptor is
read-only. In particular, a `POINTER` target may still be modified.
Keep `readonly` handling independent from `noalias` and `nocapture`.
`TARGET` arguments may receive `readonly`, but must not receive
`noalias` or `nocapture`. Apply `readonly` to `BIND(C)` definitions
while leaving external C declarations unannotated. `VALUE`,
`ASYNCHRONOUS`, and `VOLATILE` dummy arguments remain excluded.
In our measurements, the enabled function specialization gives a 1.5x
speedup on 548.exchange2 on NVIDIA Neoverse V2 in a non-LTO
configuration.
Update existing lowering tests to account for the new `fir.read_only`
argument attribute, and add focused coverage:
* `dummy-argument-readonly.f90` checks marker emission for supported
scalar and descriptor arguments, excluded cases, and shallow pointer
semantics.
* `function-attrs-readonly.fir` checks translation from `fir.read_only`
to LLVM `readonly`, including `TARGET`, `BIND(C)`, and descriptor
references.
* `function-attr-readonly.f90` checks the optimization-level pipeline
gate and verifies that `readonly` reaches final LLVM IR.
* `call-copy-in-out.f90` checks that ordinary array copy-out cases
remain unmarked and that pointer-target copy-out is compatible with
shallow descriptor `readonly`.
Commit: 44a42e631e5b4e01855750c371dea87fb3927550
https://github.com/llvm/llvm-project/commit/44a42e631e5b4e01855750c371dea87fb3927550
Author: Peiqi Li <voyager.lpq at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang-tools-extra/clang-tidy/misc/RedundantExpressionCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/misc/redundant-expression.cpp
Log Message:
-----------
[clang-tidy] Fix false positive in misc-redundant-expression with type aliases (#198085)
The `misc-redundant-expression` check previously flagged expressions as
redundant if their underlying `DeclRefExpr` pointed to the same
declaration. This caused false positives when comparing identical values
accessed through distinct type aliases.
Following Clang's diagnostic `aka` logic, this patch uses the AST
Printer to stringify and compare the `NestedNameSpecifier` and
`TemplateArguments`. This safely preserves sugared types while natively
normalizing all whitespaces and newlines, ensuring robustness against
multiline formatting changes.
Fixes #145415
Commit: 6de51be4f636eda95e439db50f8463bdf8bde02e
https://github.com/llvm/llvm-project/commit/6de51be4f636eda95e439db50f8463bdf8bde02e
Author: David Green <david.green at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
Log Message:
-----------
[AArch64][GlobalISel] Legalization for bf16 fptosi/fptoui. (#209206)
Similar to other operations, this makes sure we can widen bf16
fptosi/fptoui correctly, promoting the value to a f32. The vector
variants have been proven by exhaustive checking.
Commit: 1bd46015ea4e842091109cd2a491c55c0b455330
https://github.com/llvm/llvm-project/commit/1bd46015ea4e842091109cd2a491c55c0b455330
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang-tools-extra/clang-doc/CMakeLists.txt
M clang-tools-extra/clang-doc/Generators.cpp
M clang-tools-extra/clang-doc/Generators.h
M clang-tools-extra/clang-doc/Representation.h
R clang-tools-extra/clang-doc/YAMLGenerator.cpp
M clang-tools-extra/clang-doc/tool/ClangDocMain.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
R clang-tools-extra/test/clang-doc/yaml/builtin_types.cpp
R clang-tools-extra/test/clang-doc/yaml/conversion_function.cpp
R clang-tools-extra/test/clang-doc/yaml/single-file-public.cpp
R clang-tools-extra/test/clang-doc/yaml/single-file.cpp
R clang-tools-extra/test/clang-doc/yaml/templates.cpp
M clang-tools-extra/unittests/clang-doc/CMakeLists.txt
R clang-tools-extra/unittests/clang-doc/YAMLGeneratorTest.cpp
Log Message:
-----------
[clang-doc] Remove the YAML generator (#209350)
The original intent of the YAML generator was to package the
documentation information in a structured and reusable way. It has been
superseded by the JSON generator.
Commit: 05b6b4f1af9f2eb5bebc2cfd10b2fff6bbfab55d
https://github.com/llvm/llvm-project/commit/05b6b4f1af9f2eb5bebc2cfd10b2fff6bbfab55d
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt-c/Logging.h
M orc-rt/lib/executor/Logging.cpp
M orc-rt/test/unit/LoggingTest.cpp
Log Message:
-----------
[orc-rt] Add new ControllerAccess logging category. (#209380)
The orc_rt_log_Category_ControllerAccess category should be used to log
messages from ControllerAccess implementations. E.g.
ORC_RT_LOG(Error, ControllerAccess, "connect() failed with <error>");
Commit: 4d5bc903c8a79fbadb62d8dd1e7cc93ad7a394fd
https://github.com/llvm/llvm-project/commit/4d5bc903c8a79fbadb62d8dd1e7cc93ad7a394fd
Author: Sean Clarke <sclarke at tenstorrent.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/test/CodeGen/AArch64/clmul.ll
M llvm/test/CodeGen/RISCV/clmul.ll
M llvm/test/CodeGen/X86/clmul.ll
Log Message:
-----------
[SelectionDAG] Improve `CLMUL` lowering for `Promote` types wider than register width (#209265)
For `ISD::CLMUL`, add a check to `PromoteIntRes_CLMUL` to take advantage
of the cross-product expansion in `ExpandIntRes_CLMUL` when possible for
`Promote` types which are wider than the register width (e.g. `i96` for
64-bit registers).
Commit: 8eb6e260047bd2f69d9d2c1f0967ae59f7ec5374
https://github.com/llvm/llvm-project/commit/8eb6e260047bd2f69d9d2c1f0967ae59f7ec5374
Author: Martin Storsjö <martin at martin.st>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M openmp/runtime/src/kmp_utility.cpp
Log Message:
-----------
[openmp] Apply a mingw/64 bit codepath to arm64ec too (#209297)
When targeting arm64ec, neither KMP_ARCH_X86_64 nor KMP_ARCH_AARCH64 is
defined.
This fixes a compilation warning when building openmp for mingw/arm64ec.
Commit: a436e36f5e57e8daabee71fd0cb649c1633e314f
https://github.com/llvm/llvm-project/commit/a436e36f5e57e8daabee71fd0cb649c1633e314f
Author: David Green <david.green at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/round-fptoui-sat-scalar.ll
Log Message:
-----------
[AArch64][GlobalISel] Legalization for bf16 fptosi.sat/fptoui.sat (#209378)
This is the equivalent change to #209206 for fptoi.sat.
Commit: f60650c772485640b57520e91cec9779cc7f27dc
https://github.com/llvm/llvm-project/commit/f60650c772485640b57520e91cec9779cc7f27dc
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
Log Message:
-----------
[BitcodeReader] Lazily read and cache target triple (NFC) (#208175)
Lazily read and cache the target triple from the stream, currently meant
to be used only for upgrading AArch64 memory effects from old bitcode.
Co-authored-by: Caroline Concatto <caroline.concatto at arm.com>
Commit: 69ee6b114ac3d3c6652b39d0d57b292bcfa3a81c
https://github.com/llvm/llvm-project/commit/69ee6b114ac3d3c6652b39d0d57b292bcfa3a81c
Author: WMC <tnwilly at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Dialect/LLVMIR/nvvm.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
Log Message:
-----------
[NVVM] Add FP8 (e4m3/e5m2) support to dense mma.sync (#207307)
## Motivation
I'm adding NVIDIA FP8 mma.sync support in IREE for sm_89/sm_120, and
IREE's codegen lowers through `nvgpu.mma.sync` on this path, which in
turn lowers to `nvvm.mma.sync`. This MLIR-level gap is blocking that
work, so I'm upstreaming the fix here first. This is split into two PRs
per review feedback — this one covers `nvvm.mma.sync` only; a follow-up
PR will add the corresponding `nvgpu.mma.sync` support built on top of
this.
## Description:
`nvvm.mma.sync` (warp-level, dense) don't support FP8 (e4m3/e5m2)
operands, even though the underlying PTX/NVPTX intrinsics have supported
FP8 `mma.sync.m16n8k32` since sm_89. FP8 currently only exists on the
sparse mma path and on warpgroup-level `wgmma`; the warp-level dense
path was never updated.
This adds FP8 (e4m3/e5m2) support to `nvvm.mma.sync`, covering
`m16n8k16` and `m16n8k32`.
## Verification
`$ mlir-opt mlir/test/Dialect/LLVMIR/nvvm.mlir -split-input-file
-verify-diagnostics | FileCheck mlir/test/Dialect/LLVMIR/nvvm.mlir
`
```
%0 = nvvm.mma.sync A[...] B[...] C[...]
{multiplicandAPtxType = #nvvm.mma_type<e4m3>,
multiplicandBPtxType = #nvvm.mma_type<e4m3>,
shape = #nvvm.shape<m = 16, n = 8, k = 32>}
: (i32, i32, f32) -> !llvm.struct<(f32, f32, f32, f32)>
```
`$ mlir-translate -mlir-to-llvmir mlir/test/Target/LLVMIR/nvvmir.mlir
-split-input-file -verify-diagnostics | FileCheck
mlir/test/Target/LLVMIR/nvvmir.mlir
`
```
%8 = call { float, float, float, float } @llvm.nvvm.mma.m16n8k16.row.col.f32.e4m3.e4m3.f32(i32 %0, i32 %1, i32 %2, float %3, float %4, float %5, float %6)
%11 = call { float, float, float, float } @llvm.nvvm.mma.m16n8k32.row.col.f32.e4m3.e5m2.f32(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, float %6, float %7, float %8, float %9)
```
All existing tests in nvvm.mlir (including -verify-diagnostics error
cases) still pass — no regression.
Co-authored with Claude Sonnet 5
Signed-off-by: weimin023 <tnwilly at gmail.com>
Commit: 317efbe4496900a60de09812aa91b1f486b2e795
https://github.com/llvm/llvm-project/commit/317efbe4496900a60de09812aa91b1f486b2e795
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/branch-cond-split-fcmp.ll
M llvm/test/CodeGen/AArch64/sve2p1-while-pn-folds.ll
Log Message:
-----------
[AArch64] Fold CSET + BR_CC into a conditional branch (#207398)
Fold CSETs into conditional branches (rather than lowering to a CSET +
TB[N]Z). This is most useful for lowering loop conditions based on
predicate-as-counter whiles to:
```
whilelo pn8.s, x0, x1, vlx4
b.mi .Lloop
```
Commit: 70496276d0f441999b61e84ca22e59d61fa43582
https://github.com/llvm/llvm-project/commit/70496276d0f441999b61e84ca22e59d61fa43582
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/MarkLive.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/Writer.cpp
M lld/docs/ReleaseNotes.rst
M lld/docs/ld.lld.1
M lld/test/ELF/retain-symbols-file.s
M lld/test/ELF/version-script-warn.s
Log Message:
-----------
[ELF] --retain-symbols-file: keep listed symbols in .symtab, not .dynsym (#209063)
Commit c0fc25307143dd06c12fb2f5ebdb1dade7290ccf (2017) implements
--retain-symbols-file with symbol version machinery
`{local: *; global: listed;}`, which removes unlisted symbols from
.dynsym and leaves .symtab untouched. GNU ld does the opposite: it keeps
only the listed symbols in .symtab and does not touch .dynsym.
Reuse the --discard-{locals,all} mechanism to reimplement the feature,
matching GNU ld.
Use --export-dynamic-symbol or a version script to control .dynsym.
Extend `markUsedSymbols` to mark referenced globals as well, so
--emit-relocs/-r keep a valid symbol index.
Fix #91055
Commit: e8e88dbde96a75ffe0e8bf10ea9481a053292421
https://github.com/llvm/llvm-project/commit/e8e88dbde96a75ffe0e8bf10ea9481a053292421
Author: Harlen Batagelo <hbatagelo at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaTemplateInstantiate.cpp
A clang/test/SemaTemplate/GH195988.cpp
Log Message:
-----------
[clang][sema] Fix crash on class template instantiation when a member variable partial specialization has an invalid primary template (#202006)
Fixes #195988.
For the root cause, consider this reproducer:
https://godbolt.org/z/6jTnvocs4
```cpp
template <typename> struct A {
template <typename U> static B x; // unknown type name 'B'
template <typename U> static int x<U*>;
};
A<int> a;
```
During the instantiation of `A<int>`, the variable template `x` is
skipped because it was marked as an invalid declaration due to the
unknown type `B`. When the partial specialization `x<U*>` is visited
next, the lookup for `x` finds nothing and triggers the assertion:
https://github.com/llvm/llvm-project/blob/2433b06e6dbe3ef015a226620d207a45f7b98c7c/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp#L2538
Fix by instantiating invalid variable templates using the `int` fallback
instead of skipping them.
Commit: aae01919171394ed4a4bf6b2fb82cc0d70561994
https://github.com/llvm/llvm-project/commit/aae01919171394ed4a4bf6b2fb82cc0d70561994
Author: Petr Hosek <phosek at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/src/include/overridable_function.h
Log Message:
-----------
[libcxx] Rename __libcpp_launder to __launder_function_pointer (#209320)
This addresses post-commit feedback raised in #208330.
Commit: 6c6ecb376a940d16e17dae2d40dc076466898860
https://github.com/llvm/llvm-project/commit/6c6ecb376a940d16e17dae2d40dc076466898860
Author: Petr Hosek <phosek at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/src/include/overridable_function.h
M libcxx/src/new.cpp
M libcxxabi/src/stdlib_new_delete.cpp
Log Message:
-----------
[libcxx][libcxxabi] Remove OVERRIDABLE_FUNCTION macro (#209323)
This is no longer needed, we can just use [[gnu::weak]] attribute.
Commit: 9a342c137d4ed8c6d4571ebc5a62f22aa9642278
https://github.com/llvm/llvm-project/commit/9a342c137d4ed8c6d4571ebc5a62f22aa9642278
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/early-exit-live-out.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-prune-vf.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-access-wide-stride.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
M llvm/test/Transforms/LoopVectorize/VPlan/RISCV/expand-scev.ll
Log Message:
-----------
[VPlan] Use VPSCEVExpander in convertToStridedAccesses (#208939)
Expand SCEVs to VPInstructions, falling back to expanding to IR
instructions. Expanding to VPInstructions has the advantage that the
expansion would be made visible to the VPlan optimization pipeline,
allowing existing simplifications to kick in.
Commit: 5514c1eff5fe52d0bcc2c017c0210bd31fd0bf32
https://github.com/llvm/llvm-project/commit/5514c1eff5fe52d0bcc2c017c0210bd31fd0bf32
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/UseScopedLockCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/use-scoped-lock.rst
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-scoped-lock-warn-on-single-locks-false.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-scoped-lock.cpp
Log Message:
-----------
[clang-tidy] Flag consecutive scoped_locks in use-scoped-lock (#209272)
Fixes https://github.com/llvm/llvm-project/issues/209112.
Commit: 94b7d2b4d8d7c8cfa2d09a6aa2bb1d7df81d047c
https://github.com/llvm/llvm-project/commit/94b7d2b4d8d7c8cfa2d09a6aa2bb1d7df81d047c
Author: gtrong <40399865+gtrong at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Parse/ParseDecl.cpp
M clang/test/Parser/cxx-default-args.cpp
Log Message:
-----------
[Clang] Fix error recovery for default arguments (#208868)
Fixes #205718
### Description
This PR fixes an issue where Clang incorrectly skips the creation of a
parameter when an error occurs in a default argument that involves a GNU
statement expression (`({ ... })`).
Previously, if the default expression evaluation failed within a
statement expression, the error recovery was not handled properly,
leading to the parameter being dropped. This fix ensures that the
parameter is correctly created and error recovery proceeds as expected.
### Testing
Added/Updated test cases in
`clang/test/SemaCXX/default-arg-error-recovery.cpp` to cover invalid
default arguments inside statement expressions.
Commit: 9144e3292c6caaeed2ad16b6ed2a2eba620c0257
https://github.com/llvm/llvm-project/commit/9144e3292c6caaeed2ad16b6ed2a2eba620c0257
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/include/clang/Basic/AArch64CodeGenUtils.h
M clang/include/clang/Basic/arm_neon.td
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
M clang/test/Sema/aarch64-neon-target.c
M clang/test/Sema/aarch64-neon-without-target-feature.cpp
Log Message:
-----------
[AArch64][llvm][clang] Rename 9.7 ACLE vmmlaq_f16_f16 to vmmlaq_f16 (#209242)
Rename Armv9.7 ACLE intrinsic `vmmlaq_f16_f16` to `vmmlaq_f16`
as it matches convention better.
See https://github.com/ARM-software/acle/pull/443 for the ACLE change.
Commit: 25ee70e271dd60978f8bfded54198dbe72009847
https://github.com/llvm/llvm-project/commit/25ee70e271dd60978f8bfded54198dbe72009847
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
Log Message:
-----------
[WebAssembly] Fix operands in relaxed_pmin/relaxed_pmax pattern (#209398)
After 56e62e539eb65ebe4ec9fc6de0328fea21ae86fd these should be
operands 0 and 1 instead of 1 and 2.
Also add an explicit SIMD128 check when marking these as legal.
It works fine without it (presumably because the types just aren't
legal), but this makes it more explicit when the operations are
available.
Commit: 95349af763cfc48858fdd40058bd46a11779deb2
https://github.com/llvm/llvm-project/commit/95349af763cfc48858fdd40058bd46a11779deb2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
A llvm/test/MC/AMDGPU/amdgcn-target-directive-conflict.s
M llvm/test/MC/AMDGPU/amdgcn-target-directive-subarch-cpu-field.s
M llvm/test/MC/AMDGPU/amdgcn-target-directive-triple-env.s
M llvm/test/MC/AMDGPU/hsa-diag-v4.s
M llvm/test/MC/AMDGPU/hsa-exp.s
M llvm/test/MC/AMDGPU/hsa-gfx12-v4.s
M llvm/test/MC/AMDGPU/hsa-gfx13-v4.s
M llvm/test/MC/AMDGPU/hsa-tg-split.s
M llvm/test/MC/AMDGPU/hsa-v4.s
M llvm/test/MC/AMDGPU/hsa-v5-uses-dynamic-stack.s
M llvm/test/MC/AMDGPU/isa-version-hsa.s
M llvm/test/MC/AMDGPU/isa-version-pal.s
M llvm/test/MC/AMDGPU/isa-version-unk.s
M llvm/test/MC/ELF/AMDGPU/cfi.s
Log Message:
-----------
AMDGPU: Defer validation of target assembler directives (#207812)
Stop immediately emitting the .amdgcn_target directive from the command
line's target, and wait until any target directives in the file are
encountered. This requires lazily emitting the target directive to before the
point anything is to be emitted. Weaken the validation that the xnack and
sramecc settings match the command line's state, and take the mode from the
target directive
(mutating the tracked target ID state). Liberalize the triple check so that after
#206480, old assembly files will not break on new assembler invocations.
For some reason we have 2 different assembler directives that indicate
the target, .amdgcn_target for amdhsa and .amd_amdgpu_isa for amdpal.
Previously, we would take the target from the command line and then error if the
directive did not exactly match. In order to move away from depending on the xnack
and sramecc subtarget features, start treating the directives as a change of
target, similar to ARM's .cpu and .arch directives.
Both .amdgcn_target and .amd_amdgpu_isa encode full triples, but unlike
.amdgcn_target, the PAL directive does not include xnack or sramecc.
Ideally we would introduce new independent directives for these.
Co-Authored-By: Claude Opus 4.6 <noreply at anthropic.com>
Commit: 2d401082440f16d36a42e5b55c2992f8bab4cb5f
https://github.com/llvm/llvm-project/commit/2d401082440f16d36a42e5b55c2992f8bab4cb5f
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
[GitHub] Install libedit, libxml2 and liblzma to be used in Linux LLDB builds (#209129)
In #188049 we missed some test failures because GitHub CI does not have
libxml2 installed. I checked the logs and found a couple of other things
missing.
In this change I'm adding to the Linux container:
* libedit
* libxml2
* liblzma
I am not adding ncurses because this would enable text user interface
tests that are often unstable. They do run post-commit, and don't change
that often anyway.
I am not adding Lua or TreeSitter because they are more obscure and are
tested somewhere post-commit (in Green Dragon I think).
Commit: f195f4d45dc253192270a4be3f806f2913a071d1
https://github.com/llvm/llvm-project/commit/f195f4d45dc253192270a4be3f806f2913a071d1
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/bindings/interface/SBTargetDocstrings.i
M lldb/docs/use/tutorial.md
M lldb/source/Breakpoint/Watchpoint.cpp
M lldb/test/Shell/Register/x86-db-read.test
Log Message:
-----------
[lldb] Add comma separator in watchpoint description (#209176)
I find it easier to read this way, especially the last "state = enabled type = m" which looks like "enabled type = m" at a glance:
Watchpoint 1: addr = 0xaaaaaaab1018 size = 20 state = enabled type = m
With commas:
Watchpoint 1: addr = 0xaaaaaaab1018, size = 20, state = enabled, type = m
Code breakpoints include commas already:
1: name = 'main', locations = 1, resolved = 1, hit count = 1
1.1: where = test.o`main at test.c:13:15, address = 0x0000aaaaaaaa0714, resolved, hit count = 1
Used the regex "Watchpoint [0-9]+:" to find tests and docs that needed
updating.
Commit: dad3e30521b596cade7e3c516909657c44ed2840
https://github.com/llvm/llvm-project/commit/dad3e30521b596cade7e3c516909657c44ed2840
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/Rematerializer.h
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/unittests/CodeGen/RematerializerTest.cpp
Log Message:
-----------
[CodeGen] Fix incorrect rematerialization rollback order (#197576)
This fixes an issue in the rematerializer's rollbacker wherein adjacent
MIs that were deleted through rematerializations would
sometimes---depending on the exact order in which they were
deleted---not be re-created in their original pre-rematerialization
order. While this does not impact correctness (i.e., use-def relations
are always honored), this goes against the rollbacker's intent to
re-create the MIR exactly as it was pre-rematerializations (up to slot
index changes).
Commit: 5566c87df36cacb1f006535476108dc5e4c8c18f
https://github.com/llvm/llvm-project/commit/5566c87df36cacb1f006535476108dc5e4c8c18f
Author: Victor Campos <victor.campos at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGen/builtins.c
Log Message:
-----------
[Clang] Fix boolean vector bit counting on big-endian targets (#209146)
`__builtin_ctzg` and `__builtin_clzg` (count leading/trailing zeroes)
can accept boolean vectors as arguments. In this case, they operate in
logical vector lane order. However, `EmitBitCountExpr`, used to generate
the argument to those builtins, bitcasts boolean vectors directly to
integer bitfields, whose bit order is reversed on big-endian targets.
This caused libc's SIMD `find_first_set` and `find_last_set` helpers to
count lanes from the wrong end in big-endian mode. But the issue was
general and could affect any user.
This patch normalizes the integer representation with `llvm.bitreverse`
on big-endian targets before emitting bit-count intrinsics. On top of
that, the codegen test has been refactored to run on more targets and to
cover big-endian mode as well.
As a side effect of this change, and because of the way the code is
structured, the bit reverse operation also happens for
`__builtin_popcountg`. For this intrinsic, the integer bitfield's bit
order doesn't matter because it simply counts set bits. However, to make
this change only affect the count leading/trailing intrinsics would be
too intrusive, and in any case, with optimizations enabled, the
pointless bit reversing operation on popcount is optimized away. This
behaviour is covered in the test.
Assisted-by: codex. It was used for the test, not the implementation.
Commit: afac9463c13d6e44f287ee693309497cb79e1e10
https://github.com/llvm/llvm-project/commit/afac9463c13d6e44f287ee693309497cb79e1e10
Author: Mateusz Chudyk <mateusz.chudyk at intel.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
Log Message:
-----------
[GlobalISel] Fix crash in matchCombineInsertVecElts with INLINEASM-de… (#208225)
…fined base
matchCombineInsertVecElts walks the G_INSERT_VECTOR_ELT chain by
following operand 0 of the source-defining instruction. When the base
vector is defined by INLINEASM, operand 0 is the asm string (not a
register), so calling getReg() triggers an assertion:
Assertion `isReg() && "This is not a register operand!"' failed.
Fix by using the mi_match overload that takes a MachineInstr instead of
a Register, which checks the instruction opcode before accessing any
operands.
Commit: 7401694a38d9126bc910d3edf7e04331a66befa4
https://github.com/llvm/llvm-project/commit/7401694a38d9126bc910d3edf7e04331a66befa4
Author: YaFan Tao <765370813 at qq.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
A llvm/test/CodeGen/AMDGPU/atomic_optimizations_dpp_lds_expected_active_lanes.ll
A llvm/test/Verifier/amdgpu-expected-active-lanes.ll
Log Message:
-----------
[AMDGPU] Add threshold for DPP atomic optimizer on LDS atomics (#186762)
Add amdgpu.expected.active.lane metadata which can be applied to operations by a
compiler front-end. Do not apply the DPP atomic optimizer to LDS atomics where
less than five active lanes are expected.
This is an empirically derived threshold based on GFX11 and GFX12 testing.
---------
Co-authored-by: YaFan <YaFan.Tao at amd.com>
Commit: c9610acc5b1d4f49d197a4c8816fb688736963ae
https://github.com/llvm/llvm-project/commit/c9610acc5b1d4f49d197a4c8816fb688736963ae
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYTargetStreamer.h
Log Message:
-----------
[CSKY] Fix build without PCH (#209405)
Commit: 00bf3d6cf36d1c9a910d470814a76a4be1ab1634
https://github.com/llvm/llvm-project/commit/00bf3d6cf36d1c9a910d470814a76a4be1ab1634
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/clang-tools-extra/clang-doc/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 1bd4601 (#209377)
This fixes 1bd46015ea4e842091109cd2a491c55c0b455330.
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=1bd46015ea4e842091109cd2a491c55c0b455330
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 7c151447bc8abceefa3be9e5f1b27b83803d77af
https://github.com/llvm/llvm-project/commit/7c151447bc8abceefa3be9e5f1b27b83803d77af
Author: Folkert de Vries <folkert at folkertdev.nl>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
R llvm/test/CodeGen/X86/pr142937.ll
A llvm/test/CodeGen/X86/type-tests-must-be-lowered.ll
Log Message:
-----------
[SDAG] emit error when `llvm.type.checked.load` is not lowered (#208058)
Fixes https://github.com/llvm/llvm-project/issues/164663
In rust we can enable devirtualization and LTO on a build that actually
builds a library and hence LTO does not really run. That means typed
loads are emitted, but they are not lowered (or cleaned up), which made
us hit an ICE. Giving a slightly better error message, analogous to the
existing one for `Intrinsic::type_test`, seems nice.
I'm putting this together based on
https://github.com/llvm/llvm-project/pull/179249 and
https://github.com/llvm/llvm-project/issues/164663#issuecomment-3433581033.
Commit: a31c941fa7fd9eaea855cff3bb40347c0d22243d
https://github.com/llvm/llvm-project/commit/a31c941fa7fd9eaea855cff3bb40347c0d22243d
Author: David Stuttard <david.stuttard at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
A llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-hsa.ll
A llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-rel32.mir
A llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr.ll
Log Message:
-----------
[AMDGPU] Support global address in V/S_MOV_B64 lowering (#203527)
Hit an issue where V_MOV_B64_PSEUDO had a global, which wasn't
previously handled.
Added support for this, and also for the S_MOV_B64_IMM_PSEUDO to make it
symmetrical.
Claude has been used for this commit, primarily assisting creating a
test.
Commit: d21d602d65bc5f6494da679d004b764e47347b49
https://github.com/llvm/llvm-project/commit/d21d602d65bc5f6494da679d004b764e47347b49
Author: Vikram Hegde <Vikram.Hegde at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/Analysis/ModuleSummaryAnalysis.h
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/Analysis/StackSafetyAnalysis.cpp
M llvm/lib/Passes/PassRegistry.def
Log Message:
-----------
[NPM] Port ImmutableModuleSummaryAnalysis to NPM (#203510)
Required in LTO pipelines
Commit: d4568c9fd15235bd4545a5c57f23bfcb42673f39
https://github.com/llvm/llvm-project/commit/d4568c9fd15235bd4545a5c57f23bfcb42673f39
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
Log Message:
-----------
[mlir][SPIR-V] Collapse TanPattern/TanhPattern into DirectConversionPattern (#203830)
Commit: 6a1f23ab1333ced760666282c23a7afd2db2719e
https://github.com/llvm/llvm-project/commit/6a1f23ab1333ced760666282c23a7afd2db2719e
Author: Vikram Hegde <Vikram.Hegde at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/MachineBlockPlacement.h
M llvm/include/llvm/CodeGen/RegisterCoalescerPass.h
M llvm/include/llvm/CodeGen/RenameIndependentSubregs.h
M llvm/include/llvm/CodeGen/TwoAddressInstructionPass.h
M llvm/include/llvm/CodeGen/UnreachableBlockElim.h
M llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h
M llvm/include/llvm/Transforms/Utils/UnifyLoopExits.h
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.h
M llvm/lib/Target/AMDGPU/GCNNSAReassign.h
M llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
M llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h
M llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h
M llvm/lib/Target/AMDGPU/SILowerControlFlow.h
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
M llvm/lib/Target/AMDGPU/SILowerWWMCopies.h
M llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
Log Message:
-----------
[NPM] Make few more passes required (#203511)
essentially a port of https://github.com/llvm/llvm-project/pull/148115.
matches legacy behaviour. MachineBlockPlacement is made optional since
it is optional in legacy as well. not sure if there was any reason to
make it required in NPM.
Commit: 37d488f15991d8c65666834a7aed14000d1393fa
https://github.com/llvm/llvm-project/commit/37d488f15991d8c65666834a7aed14000d1393fa
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/induction-condition-in-loop-exit.ll
M llvm/test/Transforms/ConstraintElimination/loops-header-tested-pointer-cmps.ll
Log Message:
-----------
[ConstraintElim] Look through post-increment in header EQ/NE compare. (#209199)
Extend the header-controlled induction handling to look through a
post-increment `PN + C` (constant C) on the compared value
For now, the new path is limited to deriving unsigned facts.
Alive2 Proof: https://alive2.llvm.org/ce/z/DCNeSr
PR: https://github.com/llvm/llvm-project/pull/209199
Commit: 922b1a9da0a16e9df23c1a91203cf37c24d5c26d
https://github.com/llvm/llvm-project/commit/922b1a9da0a16e9df23c1a91203cf37c24d5c26d
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/cmake/modules/FindDIASDK.cmake
Log Message:
-----------
Revert "[cmake] Fix VSINSTALLDIR check in FindDIASDK module (#208524)" (#209137)
This reverts commit 4c5e15667fe384e434961fe44cf5950dc309fdf1.
https://github.com/llvm/llvm-project/pull/208524 fixed a flag which
enabled testing with the DIA SDK. This broke all Windows build bots,
because the SDK is not available in the PATH.
Commit: add1925e5ee942794d7d6e8b4d65b32c959d472a
https://github.com/llvm/llvm-project/commit/add1925e5ee942794d7d6e8b4d65b32c959d472a
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] NFCI: Simplify LowerVectorFP_TO_INT_SAT (part 2) (#207199)
This simplifies the logic a bit more, such that the flow of the lowering
is as follows:
* Try to promote if necessary (fp16/bf16 types or src < dst)
* Try to handle natively (satwidth == srcwidth == dstwidth)
* Otherwise use min/max + truncate.
Commit: dbbd4e0de70b62c2e05d8a650ddcdff954ef8d0f
https://github.com/llvm/llvm-project/commit/dbbd4e0de70b62c2e05d8a650ddcdff954ef8d0f
Author: Ralf Jung <post at ralfj.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/docs/LangRef.md
Log Message:
-----------
[LangRef] select: describe behavior for undef and poison (#208724)
The poison semantics is based on
https://llvm.org/docs/UndefinedBehavior.html#propagation-of-poison-through-select.
IMO this definitely should appear in the "semantics" section of the
`select` instruction. If this isn't part of the `select` semantics I
don't know what is.
The undef semantics are based on what Alive does.
Commit: 8c75e8018d52ead8f97648b7b279671b89c59fa0
https://github.com/llvm/llvm-project/commit/8c75e8018d52ead8f97648b7b279671b89c59fa0
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon/fullfp16.c
M clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
Log Message:
-----------
[CIR][AArc64] Add lowering for fp16 intrinsics (multiply extended) (#209222)
This PR adds lowering for the following intrinsic groups:
* https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#multiply-extended-1
It also moves the corresponding tests from:
* clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
to:
* clang/test/CodeGen/AArch64/neon/fullfp16.c
The lowering follows the existing implementation in
CodeGen/TargetBuiltins/ARM.cpp.
Commit: 19401e09c063367a3503ae6cc1a47babfa95f243
https://github.com/llvm/llvm-project/commit/19401e09c063367a3503ae6cc1a47babfa95f243
Author: Andrew Ng <andrew.ng at sony.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/Format/CMakeLists.txt
Log Message:
-----------
[clang-format] Fix `check-format-depends` CMake for Windows (#209205)
Add `find_program` for `touch`. Convert found program paths to native
form and use these paths in the command invocation.
Commit: aa5960600ac38fcd923e69777bad1293f56658d7
https://github.com/llvm/llvm-project/commit/aa5960600ac38fcd923e69777bad1293f56658d7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Object/OffloadBinary.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
Revert "clang-linker-wrapper: Use AMDGPU::TargetID for device-image compatibility" (#209407)
Reverts llvm/llvm-project#209135
This shouldn't be doing logical linking compatibility
Commit: f6393d657271b632de22cdfeaff35cfb3d45bf92
https://github.com/llvm/llvm-project/commit/f6393d657271b632de22cdfeaff35cfb3d45bf92
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/docs/CommandGuide/lit.rst
M llvm/utils/lit/lit/cl_arguments.py
M llvm/utils/lit/lit/main.py
M llvm/utils/lit/lit/util.py
A llvm/utils/lit/tests/Inputs/time-tests/b.txt
A llvm/utils/lit/tests/Inputs/time-tests/c.txt
M llvm/utils/lit/tests/time-tests.py
Log Message:
-----------
[lit] Add configurable slowest-test limit to --time-tests (#208444)
The PR parameterizes `--time-tests`, which was hardcoded to 20 tests. We
now allow `--time-tests=N` or `--time-tests=all`.
The changes still honor the original behavior of `--time-tests`. The
parsing logic could be slightly simpler if `--time-tests` would always
require an explicit number of tests (like `-j`), but that would be a CLI
breaking change.
Commit: 1a8e5b6f594926adaaa0417543773108b7fd737d
https://github.com/llvm/llvm-project/commit/1a8e5b6f594926adaaa0417543773108b7fd737d
Author: Xiaomeng Zhang <zhangxiaomeng at hygon.cn>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86.td
M llvm/test/CodeGen/X86/slow-unaligned-mem.ll
M llvm/test/CodeGen/X86/x86-prefer-no-gather-no-scatter.ll
A llvm/test/Transforms/LoopVectorize/X86/x86-prefer-no-gather.ll
A llvm/test/Transforms/LoopVectorize/X86/x86-prefer-no-scatter.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-abs.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-saddo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-ssat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-uaddo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-usat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-div.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fix.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-mul-smulo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-mul-umulo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-mul.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-scmp.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-smax.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-smin.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-ssat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-ssubo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-usat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-usubo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-ucmp.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-umax.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-umin.ll
M llvm/test/Transforms/SLPVectorizer/X86/fabs.ll
M llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll
M llvm/test/Transforms/SLPVectorizer/X86/fma.ll
M llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
M llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
M llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
M llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
M llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
M llvm/test/Transforms/SLPVectorizer/X86/fround.ll
M llvm/test/Transforms/SLPVectorizer/X86/shift-ashr.ll
M llvm/test/Transforms/SLPVectorizer/X86/shift-lshr.ll
M llvm/test/Transforms/SLPVectorizer/X86/shift-shl.ll
M llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
M llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
A llvm/test/Transforms/SLPVectorizer/X86/x86-prefer-no-gather.ll
Log Message:
-----------
[X86] Add tuning features for Hygon C86-4G-M7 (#205992)
Add TuningPreferNoGather. TuningPreferNoScatter and TuningPrefer256Bit to C864GM7Tuning.
This will improve the performance of the C86-4G-M7.
Commit: 79acf12724942b687b7c777e1dc46dd56ca4d287
https://github.com/llvm/llvm-project/commit/79acf12724942b687b7c777e1dc46dd56ca4d287
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/test/Driver/msvc-link.c
Log Message:
-----------
[clang] Use lld-link by default when -marm64x is specified (#209324)
ARM64X hybrid object files require lld-link, as it is currently the only
linker that supports them.
Commit: f2ada6d997fe4f4854f15f2c880dd740cd2ebb8a
https://github.com/llvm/llvm-project/commit/f2ada6d997fe4f4854f15f2c880dd740cd2ebb8a
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-unroll.ll
Log Message:
-----------
[VPlan] Add test for convertToStridedAccess flag issue. NFC (#209425)
>From the comment in
https://github.com/llvm/llvm-project/pull/209168/changes#r3574524959
Commit: b3f5986138f2f6a65072b6822892afa5d8859cf7
https://github.com/llvm/llvm-project/commit/b3f5986138f2f6a65072b6822892afa5d8859cf7
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
Log Message:
-----------
[clang][CIR][AArch64] Add lowering for conversion intrinsics (#209252)
This PR adds lowering for intrinsic from the following groups:
* https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions
It continues the work started in #190961, #193273 and #199990. This PR
implements the remaining conversions truncating to zero:
* vcvtd_s32_f64
* vcvtd_s64_f64
* vcvtd_u32_f64
* vcvtd_u64_f64
The corresponding tests are moved from:
* clang/test/CodeGen/AArch64/
to:
* clang/test/CodeGen/AArch64/neon/
The lowering follows the existing implementation in
CodeGen/TargetBuiltins/ARM.cpp.
Commit: 95e647c8aa180f946c83d1e6f361989442206f52
https://github.com/llvm/llvm-project/commit/95e647c8aa180f946c83d1e6f361989442206f52
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/intrinsic-amdgcn-s-alloc-vgpr.ll
M llvm/test/CodeGen/AMDGPU/invalid-cast-load-i1.ll
M llvm/test/CodeGen/AMDGPU/invalid-hidden-kernarg-in-kernel-signature.ll
M llvm/test/CodeGen/AMDGPU/invariant-image-load.ll
M llvm/test/CodeGen/AMDGPU/ipra.ll
M llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/issue121601-combine-concat-vectors-assumes-f16.ll
M llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
M llvm/test/CodeGen/AMDGPU/issue139317-bad-opsel-reg-sequence-fold.ll
M llvm/test/CodeGen/AMDGPU/issue153808-extract-subvector-legalize.ll
M llvm/test/CodeGen/AMDGPU/issue176966-extend-vector-inreg.ll
M llvm/test/CodeGen/AMDGPU/issue48473.mir
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
M llvm/test/CodeGen/AMDGPU/issue98474-assigned-physreg-interference.mir
M llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll
M llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir
M llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/kernarg-size.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
M llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/kill-true-in-return-block.ll
M llvm/test/CodeGen/AMDGPU/known-never-nan.ll
M llvm/test/CodeGen/AMDGPU/known-never-snan.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll
M llvm/test/CodeGen/AMDGPU/large-avgpr-assign-last.mir
M llvm/test/CodeGen/AMDGPU/large-constant-initializer.ll
M llvm/test/CodeGen/AMDGPU/large-phi-search.ll
M llvm/test/CodeGen/AMDGPU/large-work-group-promote-alloca.ll
M llvm/test/CodeGen/AMDGPU/lds-barrier-memoperand.ll
M llvm/test/CodeGen/AMDGPU/lds-bounds.ll
M llvm/test/CodeGen/AMDGPU/lds-branch-vmem-hazard.mir
M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx11.mir
M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx12.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-hazards.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll
M llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll
M llvm/test/CodeGen/AMDGPU/lds-initializer.ll
M llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-agpr.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-callgraph.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-named-barrier.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-typeid.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-named-barrier.ll
M llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/lds-mixed-absolute-addresses-unused.ll
M llvm/test/CodeGen/AMDGPU/lds-mixed-absolute-dynlds.ll
M llvm/test/CodeGen/AMDGPU/lds-no-realign-allocated-variables.ll
M llvm/test/CodeGen/AMDGPU/lds-reject-anonymous-kernels.ll
M llvm/test/CodeGen/AMDGPU/lds-reject-mixed-absolute-addresses.ll
M llvm/test/CodeGen/AMDGPU/lds-relocs.ll
M llvm/test/CodeGen/AMDGPU/lds-run-twice-absolute-md.ll
M llvm/test/CodeGen/AMDGPU/lds-run-twice.ll
M llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx950.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.dead.mir
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-fp-load-invariant.ll
M llvm/test/CodeGen/AMDGPU/legalize-soffset-mbuf.ll
M llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
M llvm/test/CodeGen/AMDGPU/licm-valu.mir
M llvm/test/CodeGen/AMDGPU/licm-wwm.mir
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (17) (#209120)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: db8ea12c3918fe10912298b7acfd21269d03cab2
https://github.com/llvm/llvm-project/commit/db8ea12c3918fe10912298b7acfd21269d03cab2
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt-c/Logging.h
M orc-rt/test/regression/logging/os_log/delivery.test
M orc-rt/test/tools/orc-rt-log-check.cpp
M orc-rt/test/unit/LoggingTest.cpp
Log Message:
-----------
[orc-rt] Add ORC_RT_LOG_PUB_S for logging runtime strings. (#209401)
ORC_RT_LOG requires its format to be a string literal, so the specifier
for a runtime C string cannot be written at the call site by hand -- and
it differs by backend: os_log redacts a plain "%s" argument to <private>
unless it carries a "%{public}s" annotation, which libc's printf does
not understand.
Add ORC_RT_LOG_PUB_S, which expands to "%{public}s" on the os_log
backend and plain "%s" everywhere else. Call sites compose it into the
format by literal adjacency, so the format stays a single literal on
every backend:
ORC_RT_LOG(Info, General, "resolved " ORC_RT_LOG_PUB_S, SymbolName);
LoggingTest covers the compile/format-check path (including os_log
builds); the orc-rt-log-check delivery test confirms os_log publishes
the string rather than redacting it to <private>.
Commit: e793eee71340131b7dcbfd5fce2edde84ab4ad5a
https://github.com/llvm/llvm-project/commit/e793eee71340131b7dcbfd5fce2edde84ab4ad5a
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
Log Message:
-----------
[ORC] Add LLLazyJIT destructor with call to endSession. (#209399)
Add an LLLazyJIT destructor with a call to ExecutionSession::endSession.
This ensures that the ExecutionSession's TaskDispatcher is shut down
(and in-flight tasks completed) before LLLazyJIT class members are
destroyed. Failure to do this could lead to use-after-free errors when
using thread-based task dispatch. This was likely the cause of flakiness
in test/ExecutionEngine/OrcLazy/multiple-compile-threads-basic.ll.
rdar://181982834
Commit: 2a6cc991cc691f2cc666483c417f01675321ce2c
https://github.com/llvm/llvm-project/commit/2a6cc991cc691f2cc666483c417f01675321ce2c
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/SystemZ/SystemZInstrVector.td
M llvm/test/CodeGen/SystemZ/vec-max-05.ll
M llvm/test/CodeGen/SystemZ/vec-max-min-zerosplat.ll
M llvm/test/CodeGen/SystemZ/vec-min-05.ll
Log Message:
-----------
[SystemZ] Support pseudo fmin/fmax (#209178)
s390x supports the pseudo fmin/fmax operations (x < y ? x : y and x > y
? x : y) as mode 2 in vfmin/vfmax. As such, we should lower
PSEUDO_FMIN/FMAX to those. Also disable formation of minnum/maxnum in
SDAGBuilder, as it's not useful if we have native support for this
operation.
Commit: a9d295d615a81574eabb3645ed5d2eb5a5f4efd9
https://github.com/llvm/llvm-project/commit/a9d295d615a81574eabb3645ed5d2eb5a5f4efd9
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolutionDivision.cpp
Log Message:
-----------
[SCEVDivision] Add assertion to check operand types match (NFCI) (#204146)
In ScalarEvolutionDivision.h, the `SCEVDivision::divide` operation is
defined as follows:
```
/// Computes the Quotient and Remainder of the division of Numerator by
/// Denominator. We are not actually performing the division here. Instead, we
/// are trying to find SCEV expressions Quotient and Remainder that satisfy:
///
/// Numerator = Denominator * Quotient + Remainder
```
Therefore, I believe it makes sense to enforce that the types of
`Numerator` and `Denominator` are the same.
This patch adds an assertion to verify that restriction.
Commit: 96dcb03caa310852329c4e7ad1d678c024c6ed94
https://github.com/llvm/llvm-project/commit/96dcb03caa310852329c4e7ad1d678c024c6ed94
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
Log Message:
-----------
[NFC][LLVM][CodeGen][SVE] Strengthen the isel definition of AArch64setcc_z. (#209170)
Making all operand types derive from the compare's LHS reduces the
number of types an isel rule must specify, which improves readability.
Commit: 16094a86a6cfe79fa50dcca39b539ab6465b8ac0
https://github.com/llvm/llvm-project/commit/16094a86a6cfe79fa50dcca39b539ab6465b8ac0
Author: Srinivasa Ravi <srinivasar at nvidia.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPUOps.td
M mlir/lib/Conversion/NVGPUToNVVM/CMakeLists.txt
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
M mlir/lib/Dialect/NVGPU/IR/NVGPUDialect.cpp
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-extf-large.mlir
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-extf.mlir
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-truncf-large.mlir
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-truncf.mlir
A mlir/test/Dialect/NVGPU/nvgpu-extf-invalid.mlir
A mlir/test/Dialect/NVGPU/nvgpu-truncf-invalid.mlir
Log Message:
-----------
[MLIR][NVGPU] Add truncf and extf Ops (#199700)
This change adds the `extf` and `truncf` ops to the NVGPU dialect to
support floating-point conversion operations.
These ops support scalar and vector inputs and lower to the corresponding
NVVM ops after padding and chunking the input into `i32` registers.
Commit: c311e7b3d68cb88487c4dbc4029d101e4c19c908
https://github.com/llvm/llvm-project/commit/c311e7b3d68cb88487c4dbc4029d101e4c19c908
Author: Iurii Khosoi <aadaa_fgtaa at pm.me>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/test/CodeGen/X86/bitcnt-false-dep.ll
A llvm/test/CodeGen/X86/bls-false-dep.ll
A llvm/test/CodeGen/X86/compress-false-deps.ll
A llvm/test/CodeGen/X86/expand-false-deps.ll
Log Message:
-----------
[X86] Break false dependencies on Zen 4 and 5 (#206849) (#207079)
Some variants of Zen 5 microarchitectures have a false dependency on the
output register of tzcnt, blsr, blsi and blsmsk instructions. This PR
splits existing tuning feature for the false dependency of tzcnt/lzcnt
and adds a new tuning feature for bls*. The tzcnt and bls* tunings are
enabled by default for Zen 5.
Furthermore, at least some variants of Zen 4 and 5 microarchitectures
appear to have a false dependency on the output register of zero-masked
compress and expand instructions. Tested on Ryzen 9 9950X, Ryzen 9 7950X
and Ryzen AI 7 350, also apparent in uops.info data from Ryzen 5 7600X
and Ryzen 7 9700X (see #206849). This PR adds a new tuning feature for
the false dependency of compress/expand. The tuning is enabled for Zen 4
and Zen 5.
Fixes #206849
Commit: 7de5af16e0e72d6325d3dd63ee619a1cb3bce783
https://github.com/llvm/llvm-project/commit/7de5af16e0e72d6325d3dd63ee619a1cb3bce783
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/test/API/tools/lldb-dap/stackTrace/TestDAP_stackTrace.py
M lldb/test/API/tools/lldb-dap/stackTraceCompilerGeneratedCode/TestDAP_stackTraceCompilerGeneratedCode.py
M lldb/test/API/tools/lldb-dap/stackTraceDisassemblyDisplay/TestDAP_stackTraceDisassemblyDisplay.py
M lldb/test/API/tools/lldb-dap/stackTraceMissingFunctionName/TestDAP_stackTraceMissingFunctionName.py
M lldb/test/API/tools/lldb-dap/stackTraceMissingModule/TestDAP_stackTraceMissingModule.py
Log Message:
-----------
[lldb-dap] Migrate lldb-dap stackTrace tests (#209236)
Migrate
- TestDAP_stackTrace
- TestDAP_stackTraceDisassemblyDisplay
- TestDAP_stackTraceDisassemblyDisplay
- TestDAP_stackTraceMissingFunctionName
- TestDAP_stackTraceMissingModule
Commit: c1ae9eabc8b55aa4e2a06efacca6003ccecf6249
https://github.com/llvm/llvm-project/commit/c1ae9eabc8b55aa4e2a06efacca6003ccecf6249
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] Fixup possibly unused variable warning after #207199 (#209418)
Using [[maybe_unused]] as the variable is only used in asserts which
results in a diagnostic for no-assert builds.
Commit: 64de40e5cbfba35eb4118254326889dabb04bb6c
https://github.com/llvm/llvm-project/commit/64de40e5cbfba35eb4118254326889dabb04bb6c
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/Rematerializer.h
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/unittests/CodeGen/RematerializerTest.cpp
Log Message:
-----------
[CodeGen][AMDGPU] Prepare rematerializer for multi-def remat support (NFC) (#197579)
This makes some NFCs to the rematerializer before adding initial support
for rematerializing registers with multiple defs. The main change is
that, in the representation of (un)rematerializable register
dependencies, we drop references to machine operand indices which lose
meaning in the multi-def case.
Other minor changes listed below.
- Removal of `DefRegion` argument to `Rematerializer::recreateReg`.
Registers are always re-created in their original region so there is no
need to set their region again.
- Removal of `InsertPos` unused argument to
`Rematerializer::postRematerialization`.
- Refactor of how AMDGPU's scheduler checks whether a given register is
rematerializable.
Commit: 9582f71a3b5f71e871bee0062e641f3587e0ae23
https://github.com/llvm/llvm-project/commit/9582f71a3b5f71e871bee0062e641f3587e0ae23
Author: Mikołaj Piróg <mikolaj.maciej.pirog at intel.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86WinEHUnwindV3.cpp
M llvm/test/CodeGen/X86/win64-eh-unwindv3-split-large.ll
Log Message:
-----------
[UnwinderV3] Include padding in spliting calculations (#208458)
As in title. This is achieved by making the pass count split points in
bytes and making the average instruction size a variable.
PR done with usage of Claude Code
Commit: 24c3eaa9ccaffca94e4d82a312fcc4ed13e62476
https://github.com/llvm/llvm-project/commit/24c3eaa9ccaffca94e4d82a312fcc4ed13e62476
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/limit-soft-clause-reg-pressure.mir
M llvm/test/CodeGen/AMDGPU/literal-constant-like-operand-instruction-size.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/live-interval-bug-in-rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/liveout-implicit-def-subreg-redef-blender-verifier-error.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.add.min.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.addrspacecast.nonnull.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load-last-use.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.lds.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.flat.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-agent.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-basic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-singlethread.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-system.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-wavefront.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-workgroup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f32.fp8.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.e5m3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.off.f32.i4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.pk.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dot4.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.add.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.append.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.async.barrier.arrive.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.fi.b32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.push.pop.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.consume.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-bundle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.br.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.p.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.v.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add-errors.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add-unsupported.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.read.tr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.sub.gs.reg.rtn.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (18) (#209121)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping
the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 23a32bcedb91f27ffdac5d6e6bc65a3b19b3b36c
https://github.com/llvm/llvm-project/commit/23a32bcedb91f27ffdac5d6e6bc65a3b19b3b36c
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolutionDivision.cpp
Log Message:
-----------
[SCEVDivision] Remove unnecessary integer casts (NFCI) (#208155)
Since #204146 requires callers of SCEVDivision to pass the numerator and
the denominator with the same type, the bitwidth check in
`visitConstant` no longer makes sense.
Commit: b1c29d83c938183a4fbd706818aa09de7e9eafec
https://github.com/llvm/llvm-project/commit/b1c29d83c938183a4fbd706818aa09de7e9eafec
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/docs/resources/lldbgdbremote.md
Log Message:
-----------
[lldb][docs] Fix some formatting in the packets doc (#209440)
Commit: 03b4714611ab0aab34c7267e0946fb79bf40babe
https://github.com/llvm/llvm-project/commit/03b4714611ab0aab34c7267e0946fb79bf40babe
Author: Sergey Shcherbinin <sscherbinin at nvidia.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/test/Driver/function-attr-readonly.f90
Log Message:
-----------
[flang][NFC] Fix function-attr-readonly test on PowerPC (#209431)
Follow-up fix for the newly added test, which was not exercised on all
targets. PowerPC adds llvm.target_features between the function argument
list and the body. Stop requiring the opening brace to immediately
follow the argument list so that the checks remain target-independent.
Commit: 48636d19ab5e3bf82cbff593a82573e8094abed1
https://github.com/llvm/llvm-project/commit/48636d19ab5e3bf82cbff593a82573e8094abed1
Author: Joel Walker <theagingboy05 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-avg.mir
M llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll
Log Message:
-----------
[GlobalISel] Add G_UAVGFLOOR/G_UAVGCEIL/G_SAVGFLOOR/G_SAVGCEIL to computeKnownBits (#209171)
Add known-bits handling for the averaging (halving add) opcodes G_UAVGFLOOR,
G_UAVGCEIL, G_SAVGFLOOR and G_SAVGCEIL in GISelValueTracking, using the
existing `KnownBits::avg{Floor,Ceil}{S,U}` helpers. This matches
SelectionDAG's handling of the corresponding ISD::AVGFLOOR*/AVGCEIL*
nodes.
This lets GlobalISel drop the redundant masking around hadd/rhadd of
zero-extended operands on AArch64 (see aarch64-known-bits-hadd.ll, where the
GlobalISel output now matches SelectionDAG). The sign-extended cases are
unaffected, since the masking is not redundant there.
Part of #150515.
---
Assisted by Claude (Anthropic).
Commit: cba0124e3c4f0bb5eebf551b049f8e463879642b
https://github.com/llvm/llvm-project/commit/cba0124e3c4f0bb5eebf551b049f8e463879642b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.prim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fract.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.async.from.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.simple.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2b.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2c.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.flt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.pk.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.o.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.getlod.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.x.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.cd.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.cd.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.cd.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.o.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.direct.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.param.load.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (19) (#209122)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: da99ce2fe0f4a185ceb02c9a650ba5efdb208612
https://github.com/llvm/llvm-project/commit/da99ce2fe0f4a185ceb02c9a650ba5efdb208612
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libc/include/llvm-libc-macros/linux/signal-macros.h
M libc/test/src/signal/sigaction_test.cpp
Log Message:
-----------
[libc] Implement SA_NODEFER and SA_RESETHAND signal flags (#209429)
Defined SA_NODEFER and SA_RESETHAND in Linux signal-macros.h.
Added unit tests in sigaction_test.cpp to verify the behavior of the new
flags. Also added a test case for SA_SIGINFO.
Assisted-by: Automated tooling, human reviewed.
Commit: b4b19c8f0cc28c20d98fe2ebcd2e869d0835c8eb
https://github.com/llvm/llvm-project/commit/b4b19c8f0cc28c20d98fe2ebcd2e869d0835c8eb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lerp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.clamp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mbcnt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.form.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.i8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.gfx1251.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.u32.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.msad.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mulhi.i24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mulhi.u24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.bcast.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.down.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.idx.gen.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.up.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.xor.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane32.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.prng.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.xfail.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.xfail.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.m0.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (20) (#209211)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping
the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 5d5dd83a547ea555a8eada2dfd50413c44a3cfe9
https://github.com/llvm/llvm-project/commit/5d5dd83a547ea555a8eada2dfd50413c44a3cfe9
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Passes/Pipelines.cpp
M llvm/include/llvm/Passes/OptimizationLevel.h
M llvm/include/llvm/Transforms/IPO/ExpandVariadics.h
M llvm/lib/Passes/CMakeLists.txt
R llvm/lib/Passes/OptimizationLevel.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M polly/lib/Support/RegisterPasses.cpp
Log Message:
-----------
[Passes] Replace OptimizationLevel with an enum (#209424)
Now that OptimizationLevel no longer has a size dimension, replace it
with a simple enum class.
Commit: 367d196e5cf964a1d89d596e13c89868da8c4d8c
https://github.com/llvm/llvm-project/commit/367d196e5cf964a1d89d596e13c89868da8c4d8c
Author: Anonmiraj <ezzibrahimx at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/Lex/Preprocessor.cpp
Log Message:
-----------
[clang][Diagnostics] Fix check-point recording under default colors (#209355)
`getShowColors() != ShowColorsKind::Off` is also true for the default
Auto, so ordinary non-TTY compiles where colors are never actually
emitted kept recording check points, leaving the original 718aac9f cost
in place.
Commit: ad3c1ef174f9cac5bd0332747226740ce1b16159
https://github.com/llvm/llvm-project/commit/ad3c1ef174f9cac5bd0332747226740ce1b16159
Author: Gábor Horváth <xazax.hun at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/Analysis/LiveVariables.cpp
Log Message:
-----------
[clang][Analysis] Speed up LiveVariables set merge (#209430)
LiveVariables' mergeSets built the union by unconditionally inserting
every element of B into A. Apply the two cheap tricks the
lifetime-safety analysis uses in its dataflow join:
* Return early when both operands are the same tree (an O(1) pointer
comparison), skipping the merge entirely. Merged liveness values are
canonicalized, so two predecessors with identical liveness share the
same tree -- common at confluence points.
* Insert the smaller set into the larger one, so the number of O(log n)
insertions is min(|A|, |B|) rather than always |B|.
The result is unchanged: set union is commutative and order-independent.
On a pathological function (1000 simultaneously-live locals across 5000
control-flow merges of identical sets) the liveness computation is ~18%
faster, essentially all from the identical-set short circuit. On real
translation units the merge is a small fraction of the analysis, so the
effect is within noise (measured neutral on DAGCombiner.cpp and
X86ISelLowering.cpp); this mainly avoids redundant work at unchanged
confluence points and brings the two dataflow analyses' merges into
line.
Assisted by: Claude Opus 4.8
Co-authored-by: Gabor Horvath <gaborh at apple.com>
Commit: edd94b8fbfae72059cbe31c78ac4580056b6bb9a
https://github.com/llvm/llvm-project/commit/edd94b8fbfae72059cbe31c78ac4580056b6bb9a
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/include/lldb/Utility/Log.h
M lldb/source/Commands/CommandObjectLog.cpp
M lldb/source/Utility/Log.cpp
M lldb/unittests/Utility/LogTest.cpp
Log Message:
-----------
[lldb] Return llvm::Error from DisableLogChannel (#207004)
Follow up to #206479.
llvm:Error better describes the success exor error message states that
we were previously doing with a boolean plus an error stream.
Commit: 42d52dfb9ceae5cb261b6032e50fba512479c7ce
https://github.com/llvm/llvm-project/commit/42d52dfb9ceae5cb261b6032e50fba512479c7ce
Author: Ömer Sinan Ağacan <omeragacan at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
Log Message:
-----------
[SelectionDAG] Update MemOp to distinguish memmove from memcpy (#206005)
Commit: 0c36950dd422b118b29621c4fc3e0c91cfcfd346
https://github.com/llvm/llvm-project/commit/0c36950dd422b118b29621c4fc3e0c91cfcfd346
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 16094a8 (#209435)
This fixes 16094a86a6cfe79fa50dcca39b539ab6465b8ac0.
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=16094a86a6cfe79fa50dcca39b539ab6465b8ac0
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 269820947e948a4e4bd0b3e352b6c2bd77525e83
https://github.com/llvm/llvm-project/commit/269820947e948a4e4bd0b3e352b6c2bd77525e83
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.decperflevel.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.get.waveid.in.workgroup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.incperflevel.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memtime.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.monitor.sleep.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.nop.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sethalt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.inc.wg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.ttracedata.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt_gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.hi.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.iterative.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (21) (#209212)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping
the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: f5a55b576add124ef5350d81089eccda7103cb93
https://github.com/llvm/llvm-project/commit/f5a55b576add124ef5350d81089eccda7103cb93
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/include/mlir/TableGen/Format.h
Log Message:
-----------
[MLIR][NFC] Fix tgfmt compilation with MSVC (#209446)
Apparently older MSVC has problems with inferring template argument
types. Provide them explicitly.
Fixes https://github.com/llvm/llvm-project/issues/209303.
Commit: cd75ff08c6baf74114933a927308e8ce581efc70
https://github.com/llvm/llvm-project/commit/cd75ff08c6baf74114933a927308e8ce581efc70
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[VPlan] Type VP(Recipe|Block)Ty SubclassID (NFC) (#209132)
With the advantage that switching over the SubclassID would give better
compile-time diagnostics.
Co-authored-by: Luke Lau <luke at igalia.com>
Commit: 4b32060e213376bf1d014ffc3a462c959d8adc0a
https://github.com/llvm/llvm-project/commit/4b32060e213376bf1d014ffc3a462c959d8adc0a
Author: disservin <disservin.social at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/bitreverse.ll
Log Message:
-----------
[X86] Use BMM for bitreverse without GFNI (#209223)
For the scalar path bitreverse currently doesn't lower to vbitrevb on
AVX512-BMM unless GFNI is specified as well. However, GFNI isn't
required at all for this and only BMM needs to be present.
See https://godbolt.org/z/xr61xYzYr
Commit: 5ae6537bbaf577889fb81f5f8397463b0d0499c3
https://github.com/llvm/llvm-project/commit/5ae6537bbaf577889fb81f5f8397463b0d0499c3
Author: ioana ghiban <ioana.ghiban at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/lib/Conversion/EmitCCommon/TypeConverter.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/test/Conversion/FuncToEmitC/func-to-emitc-failed.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-dealloc.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-load-store.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-copy.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-failed.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc.mlir
Log Message:
-----------
[mlir][EmitC] Add rank-0 MemRef conversion (#205774)
Add rank-0 memref support to MemRefToEmitC and the EmitC TypeConverter,
needed for lowering the models generated by:
- `llvm/lib/Analysis/models/gen-inline-oz-test-model.py`
- `llvm/lib/Analysis/models/gen-regalloc-eviction-test-model.py`
Rank-0 memrefs are no longer rejected by `isMemRefTypeLegalForEmitC`.
The EmitC type converter maps `memref<T>` to `!emitc.ptr<T>`, giving
rank-0 memrefs addressable scalar storage.
`memref.alloc` now allocates one element for rank-0 memrefs.
`memref.dealloc` frees the pointer-backed value. `memref.load` and
`memref.store` lower rank-0 accesses through `emitc.subscript %ptr[0]`,
followed by `emitc.load` or `emitc.assign`. `memref.copy` lowers rank-0
copies as scalar load plus assign.
`memref.alloca` still rejects rank-0 memrefs because this patch only
supports pointer-backed rank-0 lowering.
The pointer recovery helper now accepts both direct `emitc.ptr<T>`
values and pointer values behind `builtin.unrealized_conversion_cast`,
which is needed by dealloc, copy, load, and store depending on where the
value comes from in conversion.
Tests cover rank-0 alloc/dealloc, load/store, alloc-backed load/store,
and copy. Removed cases this patch adds support for (rank-0) from
`func-to-emitc-failed`.
Assisted-by: Codex (refine implementation + tests). I reviewed all code
and tests before submission.
Commit: 2d1bc4fc5d00d6c96307d5375d7259011509faf3
https://github.com/llvm/llvm-project/commit/2d1bc4fc5d00d6c96307d5375d7259011509faf3
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/src/atomic.cpp
Log Message:
-----------
[libc++] Fix usage of constructive interference when we meant destructive (#208804)
We maintain a contention table to implement atomic wait/notify inside
atomic.cpp. Entries in that table are padded to avoid false sharing,
since they are expected to be accessed from multiple threads
concurrently.
However, we used std::hardware_constructive_interference_size for that,
when in reality std::hardware_destructive_interference_size is the one
we need. The semantics of constructive interference are to promote true
sharing for data that should stay colocated, while destructive
interference is to prevent false sharing.
Note that on platforms such as macOS arm64, destructive interference
size is larger than constructive interference size, which means that
this patch may regress the size of the dylib on some platforms. However,
that is required for performance purposes.
Fixes #208305
Commit: bf086335b25387ed7496577eb027531ea287f524
https://github.com/llvm/llvm-project/commit/bf086335b25387ed7496577eb027531ea287f524
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.shuffle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wavefrontsize.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.fmt-error.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.index.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id-unsupported-calling-convention.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.ll
M llvm/test/CodeGen/AMDGPU/llvm.deoptimize.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.modf.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.pow-gfx9.ll
M llvm/test/CodeGen/AMDGPU/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.ll
M llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/lo16-hi16-illegal-copy.mir
M llvm/test/CodeGen/AMDGPU/lo16-hi16-physreg-copy.mir
M llvm/test/CodeGen/AMDGPU/lo16-lo16-physreg-copy-agpr.mir
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (22) (#209213)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping
the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 6e515cd0982dbf8db7ab3850b23994396efb40bf
https://github.com/llvm/llvm-project/commit/6e515cd0982dbf8db7ab3850b23994396efb40bf
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[lldb][Windows] add release notes for lldb-server (#209415)
As of https://github.com/llvm/llvm-project/pull/209258,
`lldb-server.exe` is now the default plugin if libxml2 is available at
build time.
This patch adds a release note for this change.
Commit: 98c4ea46bd474bff97c99be0800bd7b310185a29
https://github.com/llvm/llvm-project/commit/98c4ea46bd474bff97c99be0800bd7b310185a29
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/cmake/Modules/HandleLibCXXABI.cmake
Log Message:
-----------
[libc++] Improve diagnostic for libcxxabi missing from the runtimes (#208274)
When libc++ is configured to use libc++abi as an ABI library but
libcxxabi is not part of the runtimes, we'd end up with a confusing
build error about a missing <cxxabi.h> header. Instead, diagnose at
CMake configuration time.
Closes #136480
Commit: 23b3f21fd0fff64644cf60065b971686aab9c1b3
https://github.com/llvm/llvm-project/commit/23b3f21fd0fff64644cf60065b971686aab9c1b3
Author: inquisitivecrystal <open-source at inquisitivecrystal.addy.io>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/docs/Status/Cxx20Papers.csv
M libcxx/docs/Status/Cxx23Issues.csv
Log Message:
-----------
[libc++] Mark LWG3403 as complete (#208866)
LWG3403 specifies that `ranges::ssize` should work on non-range objects
for which `ranges::size` is valid. This has been true in libc++ since
6f1b10d, which first implemented `ranges::ssize` for libc++13. The tests
introduced by that commit are sufficient to verify compliance since they
test calling `ranges::ssize` with various non-range arguments.
In addition to marking LWG3403 as complete, this also updates the status
page entry for P1970R2, the paper that added `ranges::ssize`. P1970R2 was
previously marked complete in libc++15 as an approximation; however, it was
actually complete in libc++13.
Resolves #104280
Commit: cf9a244fb2216fb55b77e1df785f6535b44b3e7f
https://github.com/llvm/llvm-project/commit/cf9a244fb2216fb55b77e1df785f6535b44b3e7f
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libc/include/llvm-libc-macros/gpu/signal-macros.h
M libc/include/llvm-libc-macros/linux/signal-macros.h
M libc/include/llvm-libc-macros/netinet-in-macros.h
M libc/include/llvm-libc-types/__futex_word.h
M libc/include/sys/prctl.h.def
Log Message:
-----------
[libc] Fix non-relative includes of __llvm-libc-common.h (#209412)
This seems to work, but I ran into this problem when trying to expand
hermetic tests.
The hdrgen-generated headers already use relative includes of this file.
Commit: cd943207f38d36528a36009e55f80501da98bcef
https://github.com/llvm/llvm-project/commit/cd943207f38d36528a36009e55f80501da98bcef
Author: Mark Zhuang <mark.zhuang at spacemit.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang-rt/CMakeLists.txt
Log Message:
-----------
[flang-rt] Disable tests by default when cross-compiling (#208926)
Cross-compiled tests can't run on the build host and pull in host
dependencies (e.g. LLVMSupport's ZLIB::ZLIB) that break the build.
Fixes #208924
Commit: d64972c91369c6372e23e728881d9c645edeb37d
https://github.com/llvm/llvm-project/commit/d64972c91369c6372e23e728881d9c645edeb37d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
Log Message:
-----------
clang-linker-wrapper: Add additional amdgpu device merging tests (#209428)
Commit: 12ce00a865b09cb72a3ea9a84f9308236a4f6038
https://github.com/llvm/llvm-project/commit/12ce00a865b09cb72a3ea9a84f9308236a4f6038
Author: Ben Dunbobbin <Ben.Dunbobbin at sony.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
A cross-project-tests/dtlto/cache-extraction.test
R cross-project-tests/dtlto/cache-serialization.test
M lld/test/ELF/dtlto/timetrace.test
M llvm/include/llvm/DTLTO/DTLTO.h
M llvm/include/llvm/LTO/LTO.h
M llvm/lib/DTLTO/DTLTO.cpp
M llvm/lib/DTLTO/DTLTOInputFiles.cpp
Log Message:
-----------
[DTLTO] terminology - use extract rather than serialize (#208468)
Change the terminology used for DTLTO from "serialization" to
"extraction" for improved clarity.
Update the DTLTO time-trace scope and tests to match the new wording,
and rename/update related LLD and cross-project DTLTO cache tests.
I have also improved some unrelated wording in the comments and removed
a redundant comment block from the DTLTO class comment.
This terminology improvement was agreed in
https://github.com/llvm/llvm-project/pull/204104. Note that the
documentation already uses this terminology, see:
https://llvm.org/docs/DTLTO.html.
Commit: 226acaf7aeeda64a6e4e55d21f586ffe97a72fc8
https://github.com/llvm/llvm-project/commit/226acaf7aeeda64a6e4e55d21f586ffe97a72fc8
Author: Osama Abdelkader <osama.abdelkader at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/Sema/DeclSpec.cpp
M clang/test/SemaCXX/auto-cxx0x.cpp
Log Message:
-----------
Fix auto type-specifier conflict crash (#209308)
Clear owned type state when an invalid C++ auto/type-specifier conflict
is converted to an error so invalid declarations cannot trip DeclSpec
invariants.
Fixes https://github.com/llvm/llvm-project/issues/209000
Commit: 40152b8767769873a8f0d99b857f07c874cccf4a
https://github.com/llvm/llvm-project/commit/40152b8767769873a8f0d99b857f07c874cccf4a
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/include/__functional/function.h
Log Message:
-----------
[libc++][NFC] Inline std::function members into the class body (#209461)
The `std::function` members are incredibly simple to the point where
they are just wrappers around internal functions. We can inline them
into the body to simplify the implementation a bit.
Commit: 8748e5e3ac5d06663c3f2057a71ef19065baebaf
https://github.com/llvm/llvm-project/commit/8748e5e3ac5d06663c3f2057a71ef19065baebaf
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt/Compiler.h
M orc-rt/test/unit/CMakeLists.txt
A orc-rt/test/unit/CompilerTest.cpp
Log Message:
-----------
[orc-rt] Add ORC_RT_UNREACHABLE / ORC_RT_BUILTIN_UNREACHABLE (#209466)
ORC_RT_BUILTIN_UNREACHABLE is an optimizer hint that a location is
unreachable, wrapping __builtin_unreachable / __assume(false). Executing
it is undefined behavior.
ORC_RT_UNREACHABLE(MSG) marks a point the program must never reach. It
aborts with MSG in +Asserts builds; otherwise it lowers to
ORC_RT_BUILTIN_UNREACHABLE.
Adds a CompilerTest unit test covering both the returning-function
compile path and, in +Asserts builds only, the abort behavior via a
death test.
Commit: 2e86804e612fc6d1bace4e08b8404d0ea383d368
https://github.com/llvm/llvm-project/commit/2e86804e612fc6d1bace4e08b8404d0ea383d368
Author: Scott Manley <rscottmanley at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
M mlir/lib/Dialect/OpenACC/Transforms/ACCRecipeMaterialization.cpp
M mlir/test/Dialect/OpenACC/acc-recipe-materialization-reduction.mlir
Log Message:
-----------
[OpenACC] apply seq par dims to reduction variables (#209261)
When the acc.parallel op is "effectively sequential" apply the correct
par dims during recipe materialization of reduction variables
Commit: fba1a4b1292af3e7d08e9678e967ce12795d67d4
https://github.com/llvm/llvm-project/commit/fba1a4b1292af3e7d08e9678e967ce12795d67d4
Author: Hrólf Kraki <janmejayapanda400 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/Sema/SemaOverload.cpp
M clang/test/SemaCXX/recovery-expr-type.cpp
Log Message:
-----------
[clang] Prevent nested RecoveryExpr in BuildConvertedConstantExpression (#207072)
when BuildConvertedConstantExpression receives an expression that is
already a RecoveryExpr, return it directly instead of wrapping it in
another RecoveryExpr
Fixes #186656
Fixes #202117
Commit: 8518c74b5ef8950b9b604df588f29d9037fe1380
https://github.com/llvm/llvm-project/commit/8518c74b5ef8950b9b604df588f29d9037fe1380
Author: 1sgtpepper <cynejarviszarceno at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/LLVMIR/Import/function-attributes.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[mlir][llvm] Preserve function entry count metadata (#204707)
Fixes #202374.
Preserve LLVM function `!prof` metadata for:
- `synthetic_function_entry_count`
- `function_entry_count` with import GUID operands
The importer represents the entry count, count kind, and trailing import
GUID operands in a single `#llvm.function_entry_count` attribute,
validates malformed operands before mutating the operation, and exports
the metadata through `llvm::Function::setEntryCount`.
Tests cover import, export, malformed metadata operands, synthetic
counts, synthetic counts with trailing operands, import GUID
round-tripping, and raw i64 bit-pattern preservation.
Checks:
- `git diff --check`
- `git clang-format --diff origin/main -- ...`
- `llvm-as -disable-output` smoke check
Codex was used in making this PR.
Commit: 571a27629c1bdf0b63e65a884ffa35c5c3ede767
https://github.com/llvm/llvm-project/commit/571a27629c1bdf0b63e65a884ffa35c5c3ede767
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/test/unit/CMakeLists.txt
Log Message:
-----------
[orc-rt] Sort unit test sources in CMakeLists.txt. NFC. (#209470)
Commit: b26c417dd887aec06f4a09cd23a979b705c59fa2
https://github.com/llvm/llvm-project/commit/b26c417dd887aec06f4a09cd23a979b705c59fa2
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Analysis/InlineCost.cpp
M llvm/test/Transforms/Inline/byval.ll
Log Message:
-----------
[InlineCost] Drop Requirements around ByVal Arguments
The underlying behavior was fixed in
e47359a925b88cd081ea85d10b55b0625d17b212, but given that the example
was marked alwaysinline, it bypassed any legality checks it would have
otherwise hit.
See
https://github.com/llvm/llvm-project/pull/97306#discussion_r1679306183
for discussion around which address space we should be using/legality.
This is necessary to preserve the behavior in
byval-with-non-alloca-addrspace.ll after we enable function attribute
compatibility checks in always-inline.
Reviewers: aeubanks, nikic, arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/209344
Commit: 37b8e765ce4837a7577e6f762bcdffe4b232759c
https://github.com/llvm/llvm-project/commit/37b8e765ce4837a7577e6f762bcdffe4b232759c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/IPO/AlwaysInliner.cpp
A llvm/test/Transforms/Inline/X86/always-inline-incompatible-target-features.ll
M llvm/test/Transforms/Inline/always-inline-phase-ordering.ll
Log Message:
-----------
[AlwaysInliner] Do not inline on attribute mismatches
7bdca287b102ee935e982613dba2264cbc7a32ad made it so that the inliner
will not inline functions with mismatched target attributes regardless
of the presence of alwaysinline. However, always-inline never actually
called into this function so would still do the illegal thing. I believe
the motivation for not putting it here originally/recently was that
clang does some rudimentary target feature checks, but we should not be
crashing on valid IR, and we do generate IR that caused crashes in ISel
due to this (e.g., ICP in ThinLTO backend actions).
Reviewers: nikic, aeubanks
Pull Request: https://github.com/llvm/llvm-project/pull/209345
Commit: c43967ca744ae2479987c1859df36fbb2fcf0866
https://github.com/llvm/llvm-project/commit/c43967ca744ae2479987c1859df36fbb2fcf0866
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/unittests/StaticAnalyzer/FalsePositiveRefutationBRVisitorTest.cpp
Log Message:
-----------
[analyzer] Uplift UnSatAtErrorNodeDueToRefinedConstraint test after smarter range inference (#209443)
Commit db28e48d67e3b0c44d88be9ea2d28eca2d239a9a taught
`SymbolicRangeInferrer` to derive the range of
`BO_Add`/`BO_Sub`/`BO_Mul` symbols from their operands via
`inferFromCorners`. This broke
`FalsePositiveRefutationBRVisitorTestBase.UnSatAtErrorNodeDueToRefinedConstraintNoReport`.
The test relied on the analyzer not being able to bound `int y = x + n;`
(with `x:[0,2]`, `n:[1,2]`), so that `reportIfCanBeTrue(y == 5)` created
a false state that only the Z3 crosscheck could refute. Now the analyzer
natively bounds y to `[1,4]`, proves `y == 5` infeasible, and never
emits `CAN_BE_TRUE`, so the non-Z3 assertion lost its second line.
Addition can never produce a gap (the sum of two intervals is a full
interval), so the test's premise is no longer achievable with '+'.
Switch to multiplication: for `x:[0,2]`, `n:[1,2]` the reachable
products are `{0,1,2,4}`, but `inferFromCorners` over-approximates `x*n`
to the contiguous range `[0,4]`. So `y == 3` is inside the inferred
range (native manager returns `UNKNOWN -> CAN_BE_TRUE` emitted without
Z3) yet is genuinely unreachable (Z3 refutes `x*n == 3` -> report
invalidated with crosscheck). This restores the exact refutation-visitor
mechanism the test exercises.
Fixes up #209048.
This issue would have been caught if we had a CI running Z3, like
proposed in #184695.
Assisted-by: Claude Opus 4.8
Commit: fb423ba07c3ff51fda3caa41d8bbb78d50f61906
https://github.com/llvm/llvm-project/commit/fb423ba07c3ff51fda3caa41d8bbb78d50f61906
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
A llvm/test/Assembler/thinlto-bad-summary-5.ll
Log Message:
-----------
[ThinLTO] Error on missing ValueInfo for function definition
We assume that these are available inside of BitcodeWriter
https://github.com/llvm/llvm-project/blob/09796808802f99c30a23bc0f2cd68243764e84ab/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp#L4927,
but do not currently validate this in input IR. This means that when
doing reductions with automated tooling in a non-asserts build, it is
pretty easy to end up with invalid IR that is not caught as invalid.
Reviewers: teresajohnson, mtrofin
Pull Request: https://github.com/llvm/llvm-project/pull/208948
Commit: 6af0a79d7a4e8558e89290df56491521c6730acd
https://github.com/llvm/llvm-project/commit/6af0a79d7a4e8558e89290df56491521c6730acd
Author: Douglas Yung <douglas.yung at sony.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang-tools-extra/docs/ReleaseNotes.rst
M clang/docs/ReleaseNotes.md
M cmake/Modules/LLVMVersion.cmake
M flang/docs/ReleaseNotes.md
M libcxx/include/__config
M lld/docs/ReleaseNotes.rst
M llvm/docs/ReleaseNotes.md
M llvm/utils/gn/secondary/llvm/version.gni
M llvm/utils/lit/lit/__init__.py
M llvm/utils/mlgo-utils/mlgo/__init__.py
Log Message:
-----------
Bump version to 24.0.0git (#209473)
Commit: aefba88f46a6e55645c848f58f6ba56944d5ae62
https://github.com/llvm/llvm-project/commit/aefba88f46a6e55645c848f58f6ba56944d5ae62
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/CodeGen/AArch64/sve-cmp-folds.ll
Log Message:
-----------
[LLVM][CodeGen][SVE] Add isel for zext(setcc(x,0,ne)) -> umin(x,1). (#209452)
Commit: c5022b53e409f68de0a21039f536d0119bb666c9
https://github.com/llvm/llvm-project/commit/c5022b53e409f68de0a21039f536d0119bb666c9
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZInstrVector.td
A llvm/test/CodeGen/SystemZ/vec-strict-pseudo-max.ll
A llvm/test/CodeGen/SystemZ/vec-strict-pseudo-min.ll
Log Message:
-----------
[SystemZ] Add support for strict_pseudo_fmin/fmax (#209434)
Mode 2 of vfmin/vfmax is also compatible with strict semantics
(producing invalid operation exception for both qNaN and sNaN and
returning RHS if masked.)
Commit: 6d12cf1389fa3ef57f880b8c0b25e66f0caa2f32
https://github.com/llvm/llvm-project/commit/6d12cf1389fa3ef57f880b8c0b25e66f0caa2f32
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/Analysis/CGSCCPassManager.h
M llvm/include/llvm/CodeGen/MachinePassManager.h
M llvm/include/llvm/IR/PassManager.h
M llvm/include/llvm/IR/PassManagerInternal.h
M llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
Log Message:
-----------
Reapply "[IR][NFC] Drop vtable from PassConcept/PassModel" (#208168) (#209414)
The PassConcept/PassModel vtable has a size of 64 bytes (offset to top,
RTTI pointer, complete object destructor, deleting destructor, run,
printPipeline, name, isRequired), which add up to 53kiB (all
targets)/44 kiB (single-target). As more back-end passes get ported to
the new pass manager, this size will increase.
Remove the vtables by replacing the virtual dispatch with explicit
function pointers, initialized when adding the pass to the pass manager.
While this very slightly increases the cost of adding a pass, there's
also a very slight win from avoiding the vtable indirection when
running/destructing the pass.
Use a unique_ptr with a custom deleter to store PassConcept instances.
This avoids new/delete size mismatches.
This reverts commit 6ae5965f26e53d7338a779a73725a597a4d136e5.
Commit: b1a6a90dff53b60d66f49516938ef47344a45699
https://github.com/llvm/llvm-project/commit/b1a6a90dff53b60d66f49516938ef47344a45699
Author: Vachan <vachanvy05 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/test/CodeGen/X86/bitcnt-load-with-cmov.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt-i64.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt-i64.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt.ll
Log Message:
-----------
[X86] Remove redundant `cmp` before `adc` after `lzcnt` or `tzcnt` (#208392)
fixes #193178
Commit: 3205689645eea30c9d7fde2474bdeff52629210d
https://github.com/llvm/llvm-project/commit/3205689645eea30c9d7fde2474bdeff52629210d
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/test/unit/ErrorTest.cpp
Log Message:
-----------
[orc-rt] Move ErrorTest death tests to an ErrorDeathTest suite. (#209476)
GoogleTest recommends putting death tests in a suite whose name ends in
"DeathTest": it runs those suites before all others, which avoids the
fork-after-threads hazard that can make death tests flaky.
Move the nine EXPECT_DEATH tests in ErrorTest.cpp from the ErrorTest
suite to a new ErrorDeathTest suite. Only the suite name changes; the
test bodies are untouched.
Commit: 1b10cd91d12d783fe8754c100a3afaacfee3bf9f
https://github.com/llvm/llvm-project/commit/1b10cd91d12d783fe8754c100a3afaacfee3bf9f
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/non-power-of-2-with-adjusted-gathers.ll
M llvm/test/Transforms/SLPVectorizer/X86/control-deps-schedule-data-recalculate.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-root-multiuse-same-opcode.ll
Log Message:
-----------
[SLP]Do not blacklist ordered-reduction operands on failed root attempt
An ordered reduction pulls its leaf operands into ReductionOps via the
fallback in matchAssociativeReduction. When such a reduction fails to
vectorize, marking every reduction op as analyzed also blocks those leaves,
which may still be valid reduction roots on their own.
Fixes https://github.com/llvm/llvm-project/pull/185320#issuecomment-4925949343
Reviewers: hiraditya, bababuck, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/208511
Commit: db63c56a4f985426a0c44de4da215eb06cd5a278
https://github.com/llvm/llvm-project/commit/db63c56a4f985426a0c44de4da215eb06cd5a278
Author: Midhunesh <midhunesh.p at ibm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M compiler-rt/lib/asan/AIX/asan.link_with_main_exec.txt
M compiler-rt/lib/asan/asan_malloc_linux.cpp
M compiler-rt/test/asan/TestCases/AIX/vec_malloc_calloc.cpp
Log Message:
-----------
[ASan][AIX] Intercept __linux_vec_malloc/__linux_vec_calloc/__linux_realloc (#209359)
On AIX PASE, when `__VEC__` and `_ALL_SOURCE` are defined, the XL
compiler frontend lowers calls to vec_malloc/vec_calloc/realloc to
internal symbols named `__linux_vec_malloc`, `__linux_vec_calloc`, and
`__linux_realloc` instead of the standard
`vec_malloc`/`vec_calloc`/`realloc` names. These symbols were not
intercepted, so allocations made through them bypassed ASan entirely, no
redzone poisoning, no use-after-free or overflow detection.
This adds interceptors for `__linux_vec_malloc`, `__linux_vec_calloc`,
and `__linux_realloc`, following the same pattern as the existing
`vec_malloc`/`vec_calloc` interceptors (#175584): `__linux_vec_malloc`
and `__linux_vec_calloc` route through
`asan_vec_malloc`/`asan_vec_calloc` (16-byte aligned), and
`__linux_realloc` routes through the existing `asan_realloc`.
---------
Co-authored-by: Midhunesh <midhuensh.p at ibm.com>
Commit: e731908c4f84e04a5bfbe2784231f072aac90fe6
https://github.com/llvm/llvm-project/commit/e731908c4f84e04a5bfbe2784231f072aac90fe6
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaConcept.cpp
M clang/test/SemaCXX/concepts-subsumption.cpp
Log Message:
-----------
[Clang] Adjust NTTP depths in IsAtLeastAsConstrained (#209445)
The default transform for NTTP, which is no-op, doesn't help if we need
to adjust their depths when comparing constraints.
Fixes https://github.com/llvm/llvm-project/issues/182671
Commit: 53da348e107f8e6a52625ceab355c6d200a9709a
https://github.com/llvm/llvm-project/commit/53da348e107f8e6a52625ceab355c6d200a9709a
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll
Log Message:
-----------
[LV] Add test showing incorrect trip count materialization (NFC) (#209460)
Add test case showing mis-compile for
https://github.com/llvm/llvm-project/issues/209159.
Commit: 0a5793ba557fb31ea1f847aa353397bb9b88cb18
https://github.com/llvm/llvm-project/commit/0a5793ba557fb31ea1f847aa353397bb9b88cb18
Author: ayrai-gb <ayrai at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
A llvm/test/Transforms/InstCombine/shuffle-cmp-cast-preserve-flags.ll
Log Message:
-----------
[InstCombine] Preserve IR flags when reordering icmp/fcmp/cast through a shuffle (#208627)
InstCombine's `evaluateInDifferentElementOrder` pushes a lane-reordering
`shufflevector` *through* the instruction that produced its input,
rebuilding that instruction on the reordered operands via the `buildNew`
helper — a `switch` with one case per opcode. The binary-operator case
carefully re-applies the original's poison-generating flags
(`nuw`/`nsw`, `exact`, FMF), and the `GetElementPtr` case passes through
its `getNoWrapFlags()`.
The `ICmp`, `FCmp`, and cast cases are the odd ones out. Each is a terse
`return Builder.CreateICmp/CreateFCmp/CreateCast(...)` that copies only
the predicate/opcode, returning the rebuilt instruction with default
flags. As a result a reordered `icmp samesign`, `fcmp nnan ninf`, `zext
nneg`, or `trunc nuw`/`nsw` silently loses its flag, even though the
flag held on the original.
Route each rebuilt instruction through `copyIRFlags(I)`, bringing these
cases in line with the binary-op and GEP cases. `copyIRFlags` transfers
only the flags the source instruction actually carried, so this can
never introduce an unsound promise. This is a missed-optimization fix,
not a miscompile — dropping these flags only makes later passes more
conservative.
Added
`llvm/test/Transforms/InstCombine/shuffle-cmp-cast-preserve-flags.ll`
(`icmp_samesign`, `fcmp_fmf`, `zext_nneg`), which feed the compare/cast
from `insertelement` chains so that `canEvaluateShuffled` permits the
reorder and `buildNew` actually runs, and check that the flag survives
on the rebuilt instruction after the reversing shuffle.
Found via jlebar's X86 LLVM bug-hunt / FuzzX effort:
https://github.com/SemiAnalysisAI/FuzzX/tree/master/x86/bugs/241-instcombine-buildNew-shuffle-reorder-drops-cmp-cast-flags
---------
Co-authored-by: Ayush Rai <ayrai at amd.com>
Commit: 2a1200e08cd1cb0e6744e38a7ec4611d983fb44f
https://github.com/llvm/llvm-project/commit/2a1200e08cd1cb0e6744e38a7ec4611d983fb44f
Author: Akash Banerjee <akash.banerjee at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/lib/Optimizer/OpenMP/AutomapToTargetData.cpp
A flang/test/Lower/OpenMP/declare-target-automap.f90
M flang/test/Transforms/omp-automap-to-target-data.fir
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-host.mlir
M offload/test/offloading/fortran/declare-target-automap.f90
Log Message:
-----------
[Flang][OpenMP] Fix Fortran automap handling (#162501)
This fixes Fortran `declare target enter(automap:...)` handling for
allocatable
descriptors.
- Replace the previous `has_device_addr` target-region rewrite with
explicit
target data operations around allocation/deallocation.
- On allocation, emit:
- descriptor `map(always,to)` to keep the Fortran descriptor present
- storage `map(storage)` for the allocated array data
- `map(attach)` to update the device descriptor base address to the
device data
- On deallocation, delete both the mapped storage and descriptor.
- Add a weak visible offload-entry alias for local/hidden `declare
target to/enter`
globals so libomptarget can associate the host descriptor with the real
device
global without changing the original symbol linkage.
This fixes `offload/test/offloading/fortran/declare-target-automap.f90`
reported broken in #161265.
Co-authored-by: Codex <codex at openai.com>
Commit: e1d7480aabee9ea5b06be8f7902ff2ab23f50647
https://github.com/llvm/llvm-project/commit/e1d7480aabee9ea5b06be8f7902ff2ab23f50647
Author: Benedek Kaibas <82393336+benedekaibas at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
M clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.h
A clang/lib/StaticAnalyzer/Checkers/ReportDanglingPtrDeref.cpp
A clang/test/Analysis/dangling-ptr-deref.cpp
Log Message:
-----------
[analyzer] Implemented the DanglingPtrDeref checker to detect use-after-scope lifetime errors (#209278)
Commit: 8b7b61f099616a3fbeca563b7a1da34279142797
https://github.com/llvm/llvm-project/commit/8b7b61f099616a3fbeca563b7a1da34279142797
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
A llvm/test/tools/llvm-reduce/reduce-instructions-x86-amx.ll
A llvm/test/tools/llvm-reduce/reduce-operands-x86-amx.ll
M llvm/tools/llvm-reduce/deltas/ReduceInstructions.cpp
M llvm/tools/llvm-reduce/deltas/ReduceOperands.cpp
Log Message:
-----------
[llvm-reduce] Avoid invalid replacements with x86_amx type (#209506)
It's not possible to create zero constants of this type, and even
poison constants result in a verifier error when used as an intrinsic
argument.
Commit: d6349588f34bc2f087ba6440049473ecd97853e0
https://github.com/llvm/llvm-project/commit/d6349588f34bc2f087ba6440049473ecd97853e0
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[lldb][Windows] add release notes for the Python private API removal (#209456)
The official lldb releases set `LLDB_EMBED_PYTHON_HOME` to `OFF`
https://github.com/llvm/llvm-project/blob/9582f71a3b5f71e871bee0062e641f3587e0ae23/llvm/utils/release/build_llvm_release.bat#L213
meaning that lldb on Windows does not use the private Python API by
default. Users are free to use any Python version they want. Add a
release note for this.
Commit: de4bb53abe61dec8482f91b39ce3dac6ab0d5cd9
https://github.com/llvm/llvm-project/commit/de4bb53abe61dec8482f91b39ce3dac6ab0d5cd9
Author: lntue <lntue at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libc/test/src/sys/mman/linux/posix_madvise_test.cpp
Log Message:
-----------
[libc] Fix posix_madvise_test for riscv32 bot. (#209504)
Commit: e217dcb8de5dd83b307fe8b95b43de11a7d894ab
https://github.com/llvm/llvm-project/commit/e217dcb8de5dd83b307fe8b95b43de11a7d894ab
Author: George Burgess IV <george.burgess.iv at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
Log Message:
-----------
[mlir] fix builders by moving var into assert (#209494)
non-asserts builders are failing since `vecTy` is unused aside from this
one assertion: https://lab.llvm.org/buildbot/#/builders/228/builds/4754
Since side-effects here are uninteresting, move the entire expr into the
assert, per CodingStandards.md
Fix-forward for #199700
Commit: 05aba69f4d8ee34179b0658c57280064a724f039
https://github.com/llvm/llvm-project/commit/05aba69f4d8ee34179b0658c57280064a724f039
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
A llvm/test/tools/llvm-reduce/reduce-operands-to-args-x86-amx.ll
M llvm/tools/llvm-reduce/deltas/ReduceOperandsToArgs.cpp
Log Message:
-----------
[llvm-reduce] Avoid another invalid x86_amx replacement (#209509)
Commit: 7cd1a8361376525a6094b0b365d5e726f014cde6
https://github.com/llvm/llvm-project/commit/7cd1a8361376525a6094b0b365d5e726f014cde6
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/tools/lldb-dap/DAPSessionManager.cpp
Log Message:
-----------
[lldb-dap] Simplify DAPSessionManager GetInstance (#209264)
We don't need the `std::call_once` as this guaranteed to be [thread safe
and initialised
once](https://en.cppreference.com/cpp/language/storage_duration#Static_block_variables)
since c++11.
Commit: 2ff357b2e1b9aed337a50478af2469fd9fd7442d
https://github.com/llvm/llvm-project/commit/2ff357b2e1b9aed337a50478af2469fd9fd7442d
Author: Joel Walker <theagingboy05 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Support/KnownBits.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sdiv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-udiv.mir
M llvm/test/CodeGen/X86/udiv_fix.ll
M llvm/test/CodeGen/X86/udiv_fix_sat.ll
M llvm/test/Transforms/InstCombine/known-bits.ll
Log Message:
-----------
[KnownBits] Use min non-zero divisor and quotient lower bound in udiv (#209360)
`KnownBits::udiv` was discarding information in two cases. This tightens
both:
- A zero divisor is UB, so when the divisor's known bits permit zero,
use the smallest non-zero value as the minimum divisor instead of
bailing out.
- Compute a lower bound on the quotient (`MinNum / MaxDenom`) and keep
the leading bits it shares with the upper bound, the same way
`ConstantRange::toKnownBits` does.
Both follow from the quotient being monotonic in each operand, with all
four operand bounds attainable.
`KnownBitsTest.BinaryExhaustive` passes with no unsound results, and an
exhaustive width-4 check drops suboptimal outputs from 1790 to 864.
Regenerated the affected MIR and InstCombine tests; two X86 fixed-point
tests lose now-redundant instructions.
Assisted by Claude (Anthropic).
Commit: 132ba0d21e9f53671906af6b0a8343245b4c5021
https://github.com/llvm/llvm-project/commit/132ba0d21e9f53671906af6b0a8343245b4c5021
Author: lianjinfeng2003 <101249452+mygitljf at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
Log Message:
-----------
[CIR][NFC] Update fpclass mask checks (#208975)
I updated the CIR checks to match the formatted `llvm.is.fpclass` masks
introduced by #207653. This fixes the three CIR test failures that
became visible after #208919 restored the CIR build.
Commit: 0530817558e92a99ad3a37372dc42eb165f5f69e
https://github.com/llvm/llvm-project/commit/0530817558e92a99ad3a37372dc42eb165f5f69e
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/__init__.py
R lldb/packages/Python/lldbsuite/test/tools/lldb_dap/dap_types.py
R lldb/packages/Python/lldbsuite/test/tools/lldb_dap/lldb_dap_testcase.py
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session.py
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
A lldb/packages/Python/lldbsuite/test/tools/lldb_dap/testcase.py
A lldb/packages/Python/lldbsuite/test/tools/lldb_dap/types.py
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/utils.py
M lldb/test/API/tools/lldb-dap/exception/TestDAP_exception.py
M lldb/test/API/tools/lldb-dap/exception/asan/TestDAP_asan.py
M lldb/test/API/tools/lldb-dap/exception/cpp/TestDAP_exception_cpp.py
M lldb/test/API/tools/lldb-dap/exception/objc/TestDAP_exception_objc.py
M lldb/test/API/tools/lldb-dap/exception/ubsan/TestDAP_ubsan.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_args.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_basic.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_cwd.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_debuggerRoot.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_disableSTDIO.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_environment_with_array.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_environment_with_object.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_extra_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_failing_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_failing_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_invalid_launch_commands_and_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_invalid_program.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_no_lldbinit_flag.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_shellExpandArguments_disabled.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_shellExpandArguments_enabled.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_sourcePath.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection_and_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stopOnEntry.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_terminate_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_termination.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_version.py
M lldb/test/API/tools/lldb-dap/module-event/TestDAP_module_event.py
M lldb/test/API/tools/lldb-dap/module/TestDAP_module.py
M lldb/test/API/tools/lldb-dap/moduleSymbols/TestDAP_moduleSymbols.py
M lldb/test/API/tools/lldb-dap/stackTrace/TestDAP_stackTrace.py
M lldb/test/API/tools/lldb-dap/stackTraceCompilerGeneratedCode/TestDAP_stackTraceCompilerGeneratedCode.py
M lldb/test/API/tools/lldb-dap/stackTraceDisassemblyDisplay/TestDAP_stackTraceDisassemblyDisplay.py
M lldb/test/API/tools/lldb-dap/stackTraceMissingFunctionName/TestDAP_stackTraceMissingFunctionName.py
M lldb/test/API/tools/lldb-dap/stackTraceMissingModule/TestDAP_stackTraceMissingModule.py
M lldb/test/API/tools/lldb-dap/utils/TestDAPUtils_DAPConnection.py
M lldb/test/API/tools/lldb-dap/utils/TestDAPUtils_EventHistory.py
M lldb/test/API/tools/lldb-dap/utils/TestDAPUtils_Types.py
M lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py
M lldb/test/API/tools/lldb-dap/variables/children/TestDAP_variables_children.py
Log Message:
-----------
[NFC][lldb-dap] Simplify DAP imports. (#209442)
Expose commonly used classes in the lldb_dap package and avoid repeating
the lldb_dap namespace.
Commit: 921361839666196d5b60fc6e57836570ec86665a
https://github.com/llvm/llvm-project/commit/921361839666196d5b60fc6e57836570ec86665a
Author: Nerixyz <nerixdev at outlook.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/source/Plugins/SymbolLocator/SymStore/CMakeLists.txt
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[lldb] Add release note for SymStore and generate settings docs (#209469)
We didn't have a release note for the symstore symbol locator and the
settings weren't included on https://lldb.llvm.org/use/settings.html.
The second part is probably because both were landing at the same time,
so I missed the JSON output there.
Commit: ce72145fd034cdb8abe5d14c5f9e73b8b47a8e6b
https://github.com/llvm/llvm-project/commit/ce72145fd034cdb8abe5d14c5f9e73b8b47a8e6b
Author: Usman Nadeem <mnadeem at qti.qualcomm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AArch64/fold-sext-in-reg-predicate-fixed-length.ll
M llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
Log Message:
-----------
[SelectionDAG] Add GET_ACTIVE_LANE_MASK to ComputeNumSignBits (#208977)
`GET_ACTIVE_LANE_MASK ` acts like `icmp ult` so code is similar to
`SETCC`.
Commit: fdc884f5a5f0921a191bfec3bdf2ac9aae21687a
https://github.com/llvm/llvm-project/commit/fdc884f5a5f0921a191bfec3bdf2ac9aae21687a
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M .github/workflows/containers/github-action-ci-windows/Dockerfile
Log Message:
-----------
[docker][Windows] install libxml2 using vcpkg (#209422)
Since https://github.com/llvm/llvm-project/pull/209258, lldb uses
`lldb-server.exe` by default if libxml2 is available at build time. This
means that lldb-server requires installing libxml2 in the CI
environments to test it.
This patch adds a step to install libxml2 in the docker container used
for lldb pre-merge testing on Windows.
Commit: 7b54498f07642eb8f243664079211528d6a3b0a6
https://github.com/llvm/llvm-project/commit/7b54498f07642eb8f243664079211528d6a3b0a6
Author: Nicolas Miller <nicolas.pierre.miller at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/Hexagon/HexagonPatterns.td
M llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
M llvm/test/CodeGen/Hexagon/fminmax-v67.ll
M llvm/test/CodeGen/Hexagon/fminmax.ll
Log Message:
-----------
[Hexagon] Add lowering for `{max,min}num` (#202938)
Since the floating point requirements for `{max,min}num` are less strict
than the ones for `{max,min}imumnum`, it is fine to lower them to the
same instructions that already meet the requirements for the latter.
This is similar to what the RISC-V backend does for example.
This is also a lot better than generating a standard library call.
Commit: 48c259847d186c4d773407c63393e28d0170666b
https://github.com/llvm/llvm-project/commit/48c259847d186c4d773407c63393e28d0170666b
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll
Log Message:
-----------
[VPlan] Use VPlan::hasTailFolded in materializeConstantVectorTC. (#209502)
The current checks in materializeConstantVectorTripCount miss
tail-folded cases when vectorizing loops with fmax without fast-math
flags. Use recently added hasTailFolded helper to ensure we always bail
out on tail-folded loops.
Fixes https://github.com/llvm/llvm-project/issues/209159.
Commit: a80e98e15a6188f2eed31a70a8834264a2319f81
https://github.com/llvm/llvm-project/commit/a80e98e15a6188f2eed31a70a8834264a2319f81
Author: Mircea Trofin <mtrofin at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/test/CodeGenCUDA/device-stub.cu
Log Message:
-----------
[clang][cuda] Use the source filename for module ID (#209239)
Prior to
[#184065](vscode-file://vscode-app/Applications/Visual%20Studio%20Code.app/Contents/Resources/app/out/vs/code/electron-browser/workbench/workbench.html
"https://github.com/llvm/llvm-project/issues/184065") (relanded in
[#201849](vscode-file://vscode-app/Applications/Visual%20Studio%20Code.app/Contents/Resources/app/out/vs/code/electron-browser/workbench/workbench.html
"https://github.com/llvm/llvm-project/issues/201849")), the code
introduced in https://reviews.llvm.org/D42922 was using the GUID of an
internal linkage GlobalValue to create a module id, which would then be
used in a few cuda-specific places (including creating a symbol name
suffix).
[#184065](vscode-file://vscode-app/Applications/Visual%20Studio%20Code.app/Contents/Resources/app/out/vs/code/electron-browser/workbench/workbench.html
"https://github.com/llvm/llvm-project/issues/184065") assumed the
linkage of that symbol is external - which it isn't - and, thus, all
module IDs computed for this would be identical.
The fix is to not rely on GlobalValue GUIDs in the first place. What is
needed here is a hash that's specific to this module. So we're creating
that and explicitly decoupling that calculation from GlobalValue's
notion of GUIDs.
The change should be safe wrt uniqueness / hash collisions: the old
behavior was computing a hash where the only distinguishing component
was the module's `getSourceFileName`.
FWIW, there's a stronger module ID we could compute, with
`llvm::getUniqueModuleId` (or with a trivial refactoring of it, because
it prepends a ".").
Commit: 97f76580cdb0893d0b4edc7adf703162a23c0a67
https://github.com/llvm/llvm-project/commit/97f76580cdb0893d0b4edc7adf703162a23c0a67
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
M clang/test/CodeGen/memcpy-inline-builtin.c
M clang/test/CodeGen/pr9614.c
Log Message:
-----------
[Clang] Require x86 target for some tests (#209532)
These tests assert behavior about the always-inliner which now requires
a target to be present to check function attribute compatibility for
inlining.
Fix forward for 37b8e765ce4837a7577e6f762bcdffe4b232759c.
Commit: 7d511e4c9dfeed9884bc3e0b76f720e6cc1ad437
https://github.com/llvm/llvm-project/commit/7d511e4c9dfeed9884bc3e0b76f720e6cc1ad437
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-doc/BUILD.gn
R llvm/utils/gn/secondary/clang-tools-extra/clang-doc/markdown/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/unittests/clang-doc/BUILD.gn
Log Message:
-----------
[gn] port 7633d1e7a0f336 (no more clangDocMarkdown) (#209546)
Commit: 1f066996b7cc3715300ee9841e4000cd546d6135
https://github.com/llvm/llvm-project/commit/1f066996b7cc3715300ee9841e4000cd546d6135
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-doc/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/unittests/clang-doc/BUILD.gn
Log Message:
-----------
[gn build] Port 1bd46015ea4e (#209543)
Commit: 6f2cffb15640809fb86e27c807b366c08e790c54
https://github.com/llvm/llvm-project/commit/6f2cffb15640809fb86e27c807b366c08e790c54
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Passes/BUILD.gn
Log Message:
-----------
[gn build] Port 5d5dd83a547e (#209544)
Commit: 2eac996946092e7dc11ef4027c9202734b7e600e
https://github.com/llvm/llvm-project/commit/2eac996946092e7dc11ef4027c9202734b7e600e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/lo16-lo16-physreg-copy-sgpr.mir
M llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
M llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-f64.ll
M llvm/test/CodeGen/AMDGPU/load-global-i1.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i64.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-invariant.ll
M llvm/test/CodeGen/AMDGPU/load-hi16.ll
M llvm/test/CodeGen/AMDGPU/load-lo16.ll
M llvm/test/CodeGen/AMDGPU/load-local-f32-no-ds128.ll
M llvm/test/CodeGen/AMDGPU/load-local-f32.ll
M llvm/test/CodeGen/AMDGPU/load-local-f64.ll
M llvm/test/CodeGen/AMDGPU/load-local-i1.ll
M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
M llvm/test/CodeGen/AMDGPU/load-local-i32.ll
M llvm/test/CodeGen/AMDGPU/load-local-i64.ll
M llvm/test/CodeGen/AMDGPU/load-local-i8.ll
M llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
M llvm/test/CodeGen/AMDGPU/load-local.128.ll
M llvm/test/CodeGen/AMDGPU/load-local.96.ll
M llvm/test/CodeGen/AMDGPU/load-range-metadata-assert.ll
M llvm/test/CodeGen/AMDGPU/load-range-metadata-sign-bits.ll
M llvm/test/CodeGen/AMDGPU/load-saddr-offset-imm.ll
M llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
M llvm/test/CodeGen/AMDGPU/load-store-cnt.ll
M llvm/test/CodeGen/AMDGPU/load-store-opt-addc0.mir
M llvm/test/CodeGen/AMDGPU/load-store-opt-dlc.mir
M llvm/test/CodeGen/AMDGPU/load-store-opt-ds-regclass-constrain.mir
M llvm/test/CodeGen/AMDGPU/load-store-opt-scale-offset.mir
M llvm/test/CodeGen/AMDGPU/load-store-opt-scc.mir
M llvm/test/CodeGen/AMDGPU/load-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/local-64.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/local-atomics.ll
M llvm/test/CodeGen/AMDGPU/local-atomics64.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-memory.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-sort-framerefs.mir
M llvm/test/CodeGen/AMDGPU/local-stack-slot-offset.ll
M llvm/test/CodeGen/AMDGPU/loop-header-align-gfx950.mir
M llvm/test/CodeGen/AMDGPU/loop-idiom.ll
M llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll
M llvm/test/CodeGen/AMDGPU/loop-on-function-argument.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
M llvm/test/CodeGen/AMDGPU/loop_header_nopred.mir
M llvm/test/CodeGen/AMDGPU/lower-brcond-with-xor.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-dead-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-lastuse-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-declaration.ll
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-existing.ll
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll
M llvm/test/CodeGen/AMDGPU/lower-empty-ctor-dtor.ll
M llvm/test/CodeGen/AMDGPU/lower-i1-copies-clear-kills.mir
M llvm/test/CodeGen/AMDGPU/lower-i1-copies-implicit-def-unstructured-loop.mir
M llvm/test/CodeGen/AMDGPU/lower-indirect-lds-references.ll
M llvm/test/CodeGen/AMDGPU/lower-intrinsics-noalias-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-and-module-lds.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-arguments-noalias-call-no-ptr-args.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-lds-constexpr.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-lds-super-align.ll
M llvm/test/CodeGen/AMDGPU/lower-kernel-lds.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-merge.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-with-alias-scope.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-with-noalias.ll
M llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics-threshold.ll
M llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (23) (#209214)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: c8c3c30d5b986450618e77ed1069232a2063a0ae
https://github.com/llvm/llvm-project/commit/c8c3c30d5b986450618e77ed1069232a2063a0ae
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysis/Analyses/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/ScalableStaticAnalysis/BUILD.gn
Log Message:
-----------
[gn build] Port 612e7ca85c53 (#209545)
Commit: c8e2abb23d252da15fc16fcd6f43f9ab7543e02d
https://github.com/llvm/llvm-project/commit/c8e2abb23d252da15fc16fcd6f43f9ab7543e02d
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn
Log Message:
-----------
[gn build] Port a718d2ad092b (#209547)
Commit: 61853bac070678debbd80acf891dd681ceb0c1eb
https://github.com/llvm/llvm-project/commit/61853bac070678debbd80acf891dd681ceb0c1eb
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-doc/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/unittests/clang-doc/BUILD.gn
Log Message:
-----------
[gn build] Port c6ebd7a2ced7 (#209548)
Commit: 26e2b0980e10001174405d4412abd0d86f2e0ff5
https://github.com/llvm/llvm-project/commit/26e2b0980e10001174405d4412abd0d86f2e0ff5
Author: Nico Weber <thakis at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn
Log Message:
-----------
[gn build] Port e1d7480aabee (#209549)
Commit: 77ff300cdfdbafc1abf60a79c32da497616afc1a
https://github.com/llvm/llvm-project/commit/77ff300cdfdbafc1abf60a79c32da497616afc1a
Author: lntue <lntue at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libc/test/src/sys/mman/linux/posix_madvise_test.cpp
Log Message:
-----------
[libc] Fix a typo in posix_madvise_test. (#209523)
Commit: cb83c6a8ba2f17cfb8d01d10722b9c1aa9743328
https://github.com/llvm/llvm-project/commit/cb83c6a8ba2f17cfb8d01d10722b9c1aa9743328
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/test/benchmarks/algorithms/min.bench.cpp
M libcxx/test/benchmarks/algorithms/minmax.bench.cpp
M libcxx/test/benchmarks/algorithms/nonmodifying/search_n.bench.cpp
Log Message:
-----------
[libc++][NFC] Remove unused <cassert> from algorithm benchmarks (#209492)
A few benchmark files were including <cassert> but didn't use it.
Commit: 1a072b5f008321f22e61f744b7474fe52f0ee48c
https://github.com/llvm/llvm-project/commit/1a072b5f008321f22e61f744b7474fe52f0ee48c
Author: Douglas Yung <douglas.yung at sony.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/SystemZ/zos-ppa2.ll
Log Message:
-----------
Fix test that had a check embedded which depended on the current LLVM version number. (#209530)
When the test was refactored, it embedded the current LLVM version
number in one of the check strings so that when I bumped the LLVM
version to 24, the test failed since it was expecting 23 but the
compiler was now generating 23.
Fix this issue by changing the check to a regex so it doesn't need
updating after every LLVM version change.
Commit: 83dc9c6c9a56bc90faa810512e0577e59dc46033
https://github.com/llvm/llvm-project/commit/83dc9c6c9a56bc90faa810512e0577e59dc46033
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Support/CMakeLists.txt
M flang/lib/Optimizer/Support/InitFIR.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
M mlir/include/mlir/Target/LLVMIR/Dialect/All.h
R mlir/include/mlir/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.h
M mlir/lib/Target/LLVMIR/CMakeLists.txt
M mlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt
R mlir/lib/Target/LLVMIR/Dialect/OpenACC/CMakeLists.txt
R mlir/lib/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.cpp
R mlir/test/Target/LLVMIR/openacc-llvm.mlir
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/Support/BUILD.bazel
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/Transforms/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][openacc] Remove OpenACCToLLVMIRTranslation (#209295)
OpenACCToLLVMIRTranslation was designed more than 5 years ago and does
not align with the current upstreaming effort. OpenACC will be converted
to LLVM IR dialect before the translation to LLVM IR so this translation
is obsolete. Remove it to avoid confusion.
Commit: 4697832bae3f891c474fba3c58e852585bd1ff5f
https://github.com/llvm/llvm-project/commit/4697832bae3f891c474fba3c58e852585bd1ff5f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/lower-module-lds-all-indirect-accesses.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr-phi.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-inactive.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-indirect-extern-uses-max-reachable-alignment.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-classify.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-global-scope.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-internal-func.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-internal-multi-user.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-offsets.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-precise-allocate-to-module-struct.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-ambiguous.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-unambiguous.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-used-list.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-zero-size-arr.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds.ll
M llvm/test/CodeGen/AMDGPU/lower-multiple-ctor-dtor.ll
M llvm/test/CodeGen/AMDGPU/lower-noalias-kernargs.ll
M llvm/test/CodeGen/AMDGPU/lower-term-opcodes.mir
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-opt.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/lrint.ll
M llvm/test/CodeGen/AMDGPU/lro-coerce-v4i8-phi-loop.ll
M llvm/test/CodeGen/AMDGPU/lro-phi-samebb-nonlookthrough-store.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/lsr-cost-model-vector-iv.ll
M llvm/test/CodeGen/AMDGPU/lto-lower-module-lds.ll
M llvm/test/CodeGen/AMDGPU/machine-cp-propagation.mir
M llvm/test/CodeGen/AMDGPU/machine-cse-commute-target-flags.mir
M llvm/test/CodeGen/AMDGPU/machine-cse-ssa.mir
M llvm/test/CodeGen/AMDGPU/machine-function-info-cwsr.ll
M llvm/test/CodeGen/AMDGPU/machine-scheduler-rematerialization-scoring.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-revert-slot-monotonicity.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-cycle.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-fence.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-ignorable-exec-use.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-lane-mask.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
M llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir
M llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
M llvm/test/CodeGen/AMDGPU/mad-combine.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/mad_int24.ll
M llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
M llvm/test/CodeGen/AMDGPU/mad_uint24.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-mfma-scale.gfx950.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards.mir
M llvm/test/CodeGen/AMDGPU/mai-inline.ll
M llvm/test/CodeGen/AMDGPU/make-buffer-rsrc-lds-fails.ll
M llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/max3.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/mcexpr-knownbits-assign-crash-gh-issue-110930.ll
M llvm/test/CodeGen/AMDGPU/mcp-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/mcp-implicit-clobber.mir
M llvm/test/CodeGen/AMDGPU/mcp-overlap-after-propagation.mir
M llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
M llvm/test/CodeGen/AMDGPU/med3-knownbits.ll
M llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll
M llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
M llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scoped-aa.ll
M llvm/test/CodeGen/AMDGPU/memcpy_const_compare.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/memmove-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (24) (#209485)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: e255003ae9a942d0d62c5c8405dc45de97f31ca4
https://github.com/llvm/llvm-project/commit/e255003ae9a942d0d62c5c8405dc45de97f31ca4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/memory-legalizer-av-none.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-av-unknown.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-barriers-mmra.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-barriers.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-global.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-local.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-addrspace.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-syncscope.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-lds-dma-volatile-and-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.mir
M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/merge-buffer-gfx12.mir
M llvm/test/CodeGen/AMDGPU/merge-buffer.mir
M llvm/test/CodeGen/AMDGPU/merge-consecutive-wait-alus.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-saddr-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-image-load-gfx10.mir
M llvm/test/CodeGen/AMDGPU/merge-image-load-gfx11.mir
M llvm/test/CodeGen/AMDGPU/merge-image-load-gfx12.mir
M llvm/test/CodeGen/AMDGPU/merge-image-load.mir
M llvm/test/CodeGen/AMDGPU/merge-image-sample-gfx10.mir
M llvm/test/CodeGen/AMDGPU/merge-image-sample-gfx11.mir
M llvm/test/CodeGen/AMDGPU/merge-image-sample-gfx12.mir
M llvm/test/CodeGen/AMDGPU/merge-image-sample.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir
M llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll
M llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.mir
M llvm/test/CodeGen/AMDGPU/merge-s-load.mir
M llvm/test/CodeGen/AMDGPU/merge-sbuffer-load.mir
M llvm/test/CodeGen/AMDGPU/merge-store-crash.ll
M llvm/test/CodeGen/AMDGPU/merge-store-usedef.ll
M llvm/test/CodeGen/AMDGPU/merge-stores.ll
M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx10.mir
M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx11.mir
M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx12.mir
M llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx9.mir
M llvm/test/CodeGen/AMDGPU/merged-bfx-opt.ll
M llvm/test/CodeGen/AMDGPU/mesa3d.ll
M llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-convergent.mir
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select-gfx942.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/min-waves-per-eu-not-respected.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/min3.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (25) (#209486)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 4a2cfd73fdb55b32c3f341b0db589cf1f22c3a70
https://github.com/llvm/llvm-project/commit/4a2cfd73fdb55b32c3f341b0db589cf1f22c3a70
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll
M llvm/test/Transforms/LoopVectorize/AArch64/alias-mask-uniforms.ll
M llvm/test/Transforms/LoopVectorize/AArch64/alias-mask.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-incomplete-chains.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/pr41179.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing-alias-mask.ll
M llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-alias-mask.ll
M llvm/test/Transforms/LoopVectorize/WebAssembly/induction-branch-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/fold-tail-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-opaque-pointers.ll
M llvm/test/Transforms/LoopVectorize/X86/optsize.ll
M llvm/test/Transforms/LoopVectorize/X86/pr48340.ll
M llvm/test/Transforms/LoopVectorize/X86/pr72969.ll
M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/alias-mask-data-tail-folding-style.ll
M llvm/test/Transforms/LoopVectorize/alias-mask-needs-freeze.ll
M llvm/test/Transforms/LoopVectorize/alias-mask-small-index.ll
M llvm/test/Transforms/LoopVectorize/alias-mask.ll
M llvm/test/Transforms/LoopVectorize/hoist-and-sink-mem-ops-with-invariant-pointers.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-different-insert-position.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
M llvm/test/Transforms/LoopVectorize/metadata.ll
M llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/pr45259.ll
M llvm/test/Transforms/LoopVectorize/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll
M llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll
Log Message:
-----------
[VPlan] Expand SCEV ptrtoint/ptrtoaddr casts in VPSCEVExpander. (#209172)
Extend the cast handling in VPSCEVExpander::tryToExpand to also expand
scPtrToInt and scPtrToAddr SCEV expressions to PtrToInt/PtrToAddr
VPInstructions.
This allows pointer-distance expressions (e.g. the runtime-check
difference between two pointers, which contains ptrtoint of each
pointer) to be expanded directly to VPInstructions instead of falling
back to a VPExpandSCEVRecipe.
PR: https://github.com/llvm/llvm-project/pull/209172
Commit: 194f7a360c475fd7da253248a6aade878b52318c
https://github.com/llvm/llvm-project/commit/194f7a360c475fd7da253248a6aade878b52318c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-014bb.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-cfg-with-self-loop.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-phi-merge-distances.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-acyclic-cfg-with-4-self-loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-11blocks.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-15blocks.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop-a.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/if_else_with_loops_nested_in_2_outer_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/inner_cfg_in_2_nested_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/loop_nested_in_3_outer_loops_complex_cfg.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/nested-loops-with-side-exits-a.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/sequence_2_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/simple-loop-3blocks.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_basic_case.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_do_not_spill_restore_inside_loop.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_common_dominator.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader1.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader2.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader3.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader4.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_keep_spilled_reg_live.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_nested_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_in_common_dominator_and_optimize_restores.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_livethrough_reg.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_value_in_exit_block.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/three-tier-ranking-nested-loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/triple-nested-loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/two-sequential-loops.mir
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
M llvm/test/CodeGen/AMDGPU/mir-dynamic-vgpr-block-size-roundtrip.mir
M llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir
M llvm/test/CodeGen/AMDGPU/misched-into-wmma-hazard-shadow.mir
M llvm/test/CodeGen/AMDGPU/misched-killflags.mir
M llvm/test/CodeGen/AMDGPU/missing-store.ll
M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
M llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll
M llvm/test/CodeGen/AMDGPU/mixed_wave32_wave64.ll
M llvm/test/CodeGen/AMDGPU/mmo-target-flags-folding.ll
M llvm/test/CodeGen/AMDGPU/mmra.ll
M llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus.mir
M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/mode-register.mir
M llvm/test/CodeGen/AMDGPU/modf-constant-fold.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll
M llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu-flat.mir
M llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-absdiff.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-lshl_add.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-lshlrev.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll
M llvm/test/CodeGen/AMDGPU/movreld-bug.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
M llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
M llvm/test/CodeGen/AMDGPU/mubuf.ll
M llvm/test/CodeGen/AMDGPU/mul.i16.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multi-call-resource-usage-mcexpr.ll
M llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
M llvm/test/CodeGen/AMDGPU/multi-dword-vgpr-spill.ll
M llvm/test/CodeGen/AMDGPU/multi-use-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/naked-fn-with-frame-pointer.ll
M llvm/test/CodeGen/AMDGPU/nand.ll
M llvm/test/CodeGen/AMDGPU/narrow_math_for_and.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/neg_ashr64_reduce.ll
M llvm/test/CodeGen/AMDGPU/neighboring-mfma-padding.mir
M llvm/test/CodeGen/AMDGPU/nested-calls.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/no-bundle-asm.ll
M llvm/test/CodeGen/AMDGPU/no-corresponding-integer-type.ll
M llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (26) (#209487)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 27dce1908288eb57ce90b7c42fb7046260f39731
https://github.com/llvm/llvm-project/commit/27dce1908288eb57ce90b7c42fb7046260f39731
Author: Caroline Newcombe <caroline.newcombe at hpe.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
A flang/test/Analysis/AliasAnalysis/alias-analysis-omp-private-boxed-wsloop.mlir
A flang/test/Analysis/AliasAnalysis/alias-analysis-omp-private-unboxed-wsloop.mlir
Log Message:
-----------
[flang][OpenMP] Resolve private array source from block-arg owner in alias analysis (#208227)
Part of #208086. `fir::AliasAnalysis::getSource` fails to recognize an
OpenMP private array as an `Allocate` source when its `hlfir.declare` is
nested inside an omp.loop_nest, and conservatively returns `MayAlias`.
This changes `getSource` to resolve the clause-carrying OpenMP op from
the private block argument's owner region, so the private is correctly
classified and does not spuriously alias other objects. Assisted-by: Copilot
Commit: 9c7d1d2fe0d607b0cd5cfca1b8bb9ea6eee374ec
https://github.com/llvm/llvm-project/commit/9c7d1d2fe0d607b0cd5cfca1b8bb9ea6eee374ec
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/test/std/ranges/range.utility/view.interface/view.interface.pass.cpp
Log Message:
-----------
[libc++][ranges][NFC] Format `view.interface.pass.cpp` (#209391)
A prerequisite to #205012
Commit: 4264f9154c9ee153392cce6c90827fa4544bff7e
https://github.com/llvm/llvm-project/commit/4264f9154c9ee153392cce6c90827fa4544bff7e
Author: void_17 <61356189+void2012 at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Support/Windows/DynamicLibrary.inc
Log Message:
-----------
[NFC] Rename misleading `msvcrt` comment in `Windows/DynamicLibrary.inc` (#208884)
The comment in function `DynamicLibrary::HandleSet::DLSym` referred to
the mysterious `msvc.dll` windows standard dynamic library which simply
doesn't exist and `msvcrt.dll` was likely meant, so fix the comments.
Commit: 7618426138aae95561da676a1d1e10ee0392bf78
https://github.com/llvm/llvm-project/commit/7618426138aae95561da676a1d1e10ee0392bf78
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/include/__functional/function.h
Log Message:
-----------
Revert "[libc++][NFC] Inline std::function members into the class body" (#209555)
Reverts llvm/llvm-project#209461
This is breaking LLDB testing bots and it also failed pre-merge CI.
Commit: d454522b4140d7baa9d1be5d0ce2da327104c0d1
https://github.com/llvm/llvm-project/commit/d454522b4140d7baa9d1be5d0ce2da327104c0d1
Author: Usman Nadeem <mnadeem at qti.qualcomm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/CodeGen/AArch64/active_lane_mask.ll
M llvm/test/CodeGen/AArch64/sve-mask-partition.ll
Log Message:
-----------
[AArch64] Tighten conditions for expanding GET_ACTIVE_LANE_MASK (#208962)
Lower to whilelo in more cases.
For fixed-width even if the operands are <32 bits, expanding is going to
be more expensive compared to promoting the operands from a smaller
type.
For SVE I also added lowering for nxv1i1 type as: `nxv2i1 -> extract
nxv1i1.`
Commit: 84199dde7198eabc924e93750063a20ceef26ef2
https://github.com/llvm/llvm-project/commit/84199dde7198eabc924e93750063a20ceef26ef2
Author: Hubert Tong <hubert.reinterpretcast at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
A libunwind/test/.clang-format
Log Message:
-----------
[libunwind][test] Add .clang-format (#209364)
Borrow from `libcxx/test/.clang-format` to avoid `clang-format`
suggestions that are incompatible with `FileCheck`.
Commit: a56f9cefd75cd12802e37a66425b1a57d761a0af
https://github.com/llvm/llvm-project/commit/a56f9cefd75cd12802e37a66425b1a57d761a0af
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir
Log Message:
-----------
[AMDGPU][CodeGen] Pre-commit test for gfx1250 Setreg hazard violation (#209524)
Co-issue optimizations during placement of `S_SET_VGPR_MSB` instructions
can create a situation where a `S_SET_VGPR_MSB` appears directly after a
`S_SETREG_IMM32_B32(MODE)`, silently dropping the former and causing a
hazard violation on gfx1250.
Commit: 79d1db7e00932407c4aa1028632f2c188d14cac8
https://github.com/llvm/llvm-project/commit/79d1db7e00932407c4aa1028632f2c188d14cac8
Author: Garvit Gupta <garvgupt at qti.qualcomm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrPredicates.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
A llvm/test/CodeGen/RISCV/xqcilo-xqcilia-frame-index.ll
Log Message:
-----------
[RISCV] Fold 26-bit frame-index offsets into Xqcilo/Xqcilia load/store/addi (#209315)
Extend frame-index addressing such that the sp-relative offset resolved for a stack access that fits within 26-bit and not 12-bits; folds directly into the wide Xqcilo/Xqcilia instructions. This is achieved by adding the support for the following:
- Adding support for stack accesses to complex pattern `SelectAddrRegImm26` for 26-bit loads and stores
- Adding support for frame index operand to qc.e.addi instruction
- Allowing 26-bit offsets to fold into the loads and store instructions from qcilo/qcilia extension
Commit: 8410006af686f3fb5e8af2705c8aab28c374c13a
https://github.com/llvm/llvm-project/commit/8410006af686f3fb5e8af2705c8aab28c374c13a
Author: Alex Kuleshov <0xAX at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/tools/llvm-mc/Disassembler.cpp
M llvm/tools/llvm-mc/Disassembler.h
M llvm/tools/llvm-mc/llvm-mc.cpp
Log Message:
-----------
[llvm-mc] Remove unused MCRegisterInfo/MCAsmInfo in Disassembler (NFC) (#208483)
Disassembler::disassemble() creates MCRegisterInfo and MCAsmInfo
instances that are no longer used.
Initially, they were introduced in a1bc0f5 to construct MCContext after
MCDisassembler began requiring one, but became dead in 2cb2707.
llvm-mc's main() already creates both objects and passes them into the
MCContext that disassemble() receives, so the error paths here are
unreachable.
Removing these objects also makes the MCTargetOptions parameter unused,
so drop it as well.
Commit: c7a0afe5049a3d4789f34a8d746c6a45d73557b4
https://github.com/llvm/llvm-project/commit/c7a0afe5049a3d4789f34a8d746c6a45d73557b4
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/source/Utility/Policy.cpp
Log Message:
-----------
[lldb] Gate `PolicyStack::Current()` log behind verbose (#209527)
`Process::GetState()` calls `PolicyStack::Get().Current()` on every
prompt redraw, so the previous unconditional LLDB_LOG at the read site
fired on every keypress once `log enable lldb process` was on, drowning
out any other process log output. Keep the dump for when it's actually
wanted, but only fire it if the log is set to verbose.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 4471a0be22e8784a7487e1ce01e9083b50c47116
https://github.com/llvm/llvm-project/commit/4471a0be22e8784a7487e1ce01e9083b50c47116
Author: David Young <davidayoung at meta.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[lldb][bazel] Generate SafeAutoloadPaths.inc in the Bazel overlay (#209454)
The auto-load-paths mechanism added in #187031 generates
SafeAutoloadPaths.inc via a CMake configure_file() of
SafeAutoloadPaths.inc.in (lldb/source/Core/CMakeLists.txt), gated by the
LLDB_SAFE_AUTO_LOAD_PATHS cache variable which defaults to empty.
Debugger.cpp #includes SafeAutoloadPaths.inc, but the Bazel overlay
never modeled the configure_file(), so the header is missing from the
Bazel build of lldb Core.
Reproduce the generation with expand_template (substituting
@SAFE_PATH_ENTRIES@ with "" to match the empty default). Emit the header
under include/ and expose it via includes = ["include"] so the bare
#include resolves, matching how Config.h and Version.inc are handled in
this overlay.
assisted with: claude
I ensured this is valid bazel that Meta can translate into valid BUCK
and build lldb with internally via buck2. This appears to match a few
other template/library pairs.
Commit: 666b87dd01d31cc80f356315c1c2d03974759138
https://github.com/llvm/llvm-project/commit/666b87dd01d31cc80f356315c1c2d03974759138
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
M llvm/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll
M llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir
M llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
M llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
M llvm/test/CodeGen/AMDGPU/nofpclass-call.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/noop-shader-O0.ll
M llvm/test/CodeGen/AMDGPU/nop-data.ll
M llvm/test/CodeGen/AMDGPU/nor-divergent-lanemask.ll
M llvm/test/CodeGen/AMDGPU/nor.ll
M llvm/test/CodeGen/AMDGPU/nsa-reassign.ll
M llvm/test/CodeGen/AMDGPU/nsa-reassign.mir
M llvm/test/CodeGen/AMDGPU/nsa-vmem-hazard.mir
M llvm/test/CodeGen/AMDGPU/object-linking-local-resources.ll
M llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-and-hostcall.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-pipeline.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-unsupported.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf.ll
M llvm/test/CodeGen/AMDGPU/operand-folding.ll
M llvm/test/CodeGen/AMDGPU/operand-spacing.ll
M llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness-wave32.mir
M llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness.mir
M llvm/test/CodeGen/AMDGPU/opt-vgpr-live-range-verifier-error.mir
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.mir
M llvm/test/CodeGen/AMDGPU/optimize-ds-bvh-stack-pre-ra.ll
M llvm/test/CodeGen/AMDGPU/optimize-exec-copies-extra-insts-after-copy.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-alloc-failure.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-no-fold-exec-copy.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-masking-strip-terminator-bits.mir
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/or3.ll
M llvm/test/CodeGen/AMDGPU/overlapping-tuple-copy-implicit-op-failure.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/packed-dependencies.mir
M llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-bf16.ll
M llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/packed-op-sel.ll
M llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable-dvgpr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-dvgpr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx950.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.6-dvgpr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.6.ll
M llvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/pal-userdata-regs.ll
M llvm/test/CodeGen/AMDGPU/partial-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/peephole-fold-imm-multi-use.mir
M llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
M llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir
M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir
M llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
M llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir
M llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
M llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
M llvm/test/CodeGen/AMDGPU/perfhint.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permlane16_opsel.ll
M llvm/test/CodeGen/AMDGPU/permlane16_var-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/phi-av-pressure.ll
M llvm/test/CodeGen/AMDGPU/phi-elim-mli-available.mir
M llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
M llvm/test/CodeGen/AMDGPU/phys-partial-liveness.mir
M llvm/test/CodeGen/AMDGPU/pk-lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/pk_max_f16_literal.ll
M llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
M llvm/test/CodeGen/AMDGPU/post-ra-sched-reset.mir
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
M llvm/test/CodeGen/AMDGPU/postra-bundle-vimage-vsample-gfx12.mir
M llvm/test/CodeGen/AMDGPU/postra-machine-sink-livein-subrange.mir
M llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir
M llvm/test/CodeGen/AMDGPU/postra-norename.mir
M llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
M llvm/test/CodeGen/AMDGPU/postra-sink-update-dependency.mir
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (27) (#209488)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 4473e5fb88c3f222e6042d0c181a113a2d92b8a0
https://github.com/llvm/llvm-project/commit/4473e5fb88c3f222e6042d0c181a113a2d92b8a0
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
M mlir/test/Dialect/XeGPU/propagate-layout.mlir
M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F4.mlir
Log Message:
-----------
[MLIR][XeGPU] Prefer the nearer consumer's layout in LayoutInfo::meet (#208365)
**Summary**
During backward layout propagation a value can be demanded by multiple
consumers with conflicting
layouts. Previously LayoutInfo::meet kept whichever demand was assigned
first, so the winner depended on
the dataflow worklist's visitation order — nondeterministic and often
not what we want.
This changes meet to prefer the layout demanded by the consumer nearer
to the producer in program order.
This tends to preserve a consumer's layout as far up the def chain as
possible, reducing layout
conversions. It is a heuristic hint, not a proven optimum.
- Each op gets a program-order index from a pre-order walk (matching
printed-IR order), so a use inside
an scf.for body is nearer than a use after the loop.
- LayoutInfo carries the demanding op's index in a new programOrder
field. visitOperation sets a
file-scoped currentProgramOrder, and the single-arg LayoutInfo
constructor stamps it automatically.
- meet keeps the smaller programOrder; ties keep lhs.
- Removes a dead LayoutInfo::transpose declaration.
- Adds truncf_prefers_nearer_user in propagate-layout-inst-data.mlir.
- Updates the multiple-use tests in propagate-layout.mlir
(scatter_ops_preserve_load_perm_layout,
binary_op_multiple_uses, if_multiple_uses) to reflect that the nearer
consumer's layout now wins.
- a minor layout fix for simple_mxfp_gemm_quantizeA_F4.mlir
---------
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: 681cc1b9f87b355c8c5f95ee35d6521e62531ceb
https://github.com/llvm/llvm-project/commit/681cc1b9f87b355c8c5f95ee35d6521e62531ceb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir
M llvm/test/CodeGen/AMDGPU/pr51516.mir
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-IR-lowering.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs-IR-lowering.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
M llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/print-pipeline-passes.ll
M llvm/test/CodeGen/AMDGPU/printf-defined.ll
M llvm/test/CodeGen/AMDGPU/printf-existing-format-strings.ll
M llvm/test/CodeGen/AMDGPU/private-access-no-objects.ll
M llvm/test/CodeGen/AMDGPU/private-function.ll
M llvm/test/CodeGen/AMDGPU/prologue-epilogue-markers.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-allocation.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-bitcast-function.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-cfg.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-globals.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-invariant-markers.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-lifetime.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-loadstores.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-max-regs.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-mem-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-multidim.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-negative-index.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-non-byte-sizes.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-non-constant-index.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-placeholder-replacement.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-pointer-array.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-proper-value-replacement.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-scoring.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-strip-abi-opt-attributes.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-subvecs.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-constantexpr-use.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-icmp.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-phi.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-unhandled-intrinsic.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-use-after-erase.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-user-mult.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep-of-gep.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vgpr-ratio.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-volatile.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx10.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx90a.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir
M llvm/test/CodeGen/AMDGPU/promote-vect3-load.ll
M llvm/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll
M llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
M llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag-mubuf.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag-undef-poison.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
M llvm/test/CodeGen/AMDGPU/ptrmask.ll
M llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-register.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll
M llvm/test/CodeGen/AMDGPU/read-write-register-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/read_register.ll
M llvm/test/CodeGen/AMDGPU/readcyclecounter.ll
M llvm/test/CodeGen/AMDGPU/readlane_exec0.mir
M llvm/test/CodeGen/AMDGPU/readsteadycounter.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll
M llvm/test/CodeGen/AMDGPU/recursion.ll
M llvm/test/CodeGen/AMDGPU/recursive-resource-usage-mcexpr.ll
M llvm/test/CodeGen/AMDGPU/recursive_global_initializer.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (28) (#209489)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: b14bf6e583da3e35054bac26c5eef74ff4e717d2
https://github.com/llvm/llvm-project/commit/b14bf6e583da3e35054bac26c5eef74ff4e717d2
Author: AZero13 <gfunni234 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
A llvm/test/Transforms/InstCombine/udiv-isknownnegative.ll
Log Message:
-----------
[InstCombine] Generalize udiv by negative constant fold to handle non-constant values (#209322)
Use isKnownNegative() to catch non constant divisors.
Commit: 6e80f6733abb83ddc0a5447829a050b0497e0fb5
https://github.com/llvm/llvm-project/commit/6e80f6733abb83ddc0a5447829a050b0497e0fb5
Author: Usman Nadeem <mnadeem at qti.qualcomm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/fold-sext-in-reg-predicate-fixed-length.ll
M llvm/test/CodeGen/AArch64/get-active-lane-mask-extract.ll
Log Message:
-----------
[DAGCombiner] Fold extract_vector(get_active_lane_mask(),0) to get_active_lane_mask (#208978)
If we are extracting from the start of the vector, then we can just
rewrite to `get_active_lane_mask` with a new type and the same operands.
Depends on https://github.com/llvm/llvm-project/pull/208962 and
https://github.com/llvm/llvm-project/pull/208977
Commit: 3d7535a03c1a036204a5347a79e9f66eb96ce4bc
https://github.com/llvm/llvm-project/commit/3d7535a03c1a036204a5347a79e9f66eb96ce4bc
Author: Gábor Horváth <xazax.hun at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LiveOrigins.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LoanPropagation.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/MovedLoans.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/Utils.h
M clang/include/clang/Analysis/Analyses/LiveVariables.h
M clang/lib/Analysis/LiveVariables.cpp
M llvm/benchmarks/ImmutableSetBuildBM.cpp
M llvm/benchmarks/ImmutableSetIteratorBM.cpp
M llvm/include/llvm/ADT/ImmutableMap.h
M llvm/include/llvm/ADT/ImmutableSet.h
M llvm/unittests/ADT/ImmutableSetTest.cpp
Log Message:
-----------
[ADT] Make canonicalization a compile-time parameter of ImmutableSet/Map (#209300)
ImmutableSet and ImmutableMap always carried the machinery needed for
tree canonicalization -- a per-node `prev`/`next` cache chain and cached
`digest`, plus the factory-side cache and a runtime `canonicalize` flag
-- even for the many clients that disable it (the Clang dataflow
analyses, e.g. lifetime safety and LiveVariables, for which
canonicalization is a large performance loss). Those clients paid for
state and code paths they never used.
Add a `bool Canonicalize` template parameter (defaulting to true, so
existing users are unaffected) that moves the decision to compile time:
* When disabled, the `prev`/`next` links (empty base) and `digest`
(LLVM_NO_UNIQUE_ADDRESS member) vanish, shrinking a set node from 56 to
40 bytes and a map node from 64 to 40 on 64-bit; `getCanonicalTree`, the
factory cache, and the `destroy()` unlink branch are `if constexpr`-ed
away. Node fields are ordered so the traversal-hot members come first.
* When enabled, the node layout is unchanged, and `operator==`/`!=`
become O(1) pointer comparisons (equal canonical trees share a root, as
with ImmutableList) instead of a structural walk.
The runtime `canonicalize` factory argument is now redundant and
removed; the in-tree non-canonicalizing users are switched to the
template argument.
Node microbenchmark (ImmutableSetBuildBM, non-canonicalizing, -O2):
| Benchmark | Before | After | Speedup |
|--------------------|---------:|---------:|:-------:|
| Build/256 | 20.3 us | 18.3 us | 1.11x |
| Build/4096 | 790 us | 731 us | 1.08x |
| Build/65536 | 18.8 ms | 18.4 ms | 1.02x |
| BuildRemove/256 | 40.7 us | 35.0 us | 1.16x |
| BuildRemove/4096 | 1.46 ms | 1.39 ms | 1.05x |
| BuildRemove/65536 | 34.6 ms | 33.8 ms | 1.02x |
End to end, the smaller node cuts the lifetime-safety analysis peak RSS
by up to ~23% on allocation-dense inputs with neutral-to-positive run
time, and the O(1) equality speeds up a Clang static analyzer run on
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp by ~1.3% (95.1s -> 93.9s).
Assisted by: Claude Opus 4.8
---------
Co-authored-by: Gabor Horvath <gaborh at apple.com>
Commit: 266c25684b32bd43d846f8de1c3a9f358066ffc4
https://github.com/llvm/llvm-project/commit/266c25684b32bd43d846f8de1c3a9f358066ffc4
Author: Mikhail Gudim <mgudim at qti.qualcomm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetFrameLowering.h
M llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
Log Message:
-----------
[CodeGen] Split determineCalleeSaves into smaller functions. (#203981)
The function `getMustPreserveRegisters` - returns the list of registers
that must be preserved by the function.
The function `determineUncondPrologCalleeSaves` - determines which of
the registers reported by `getMustPreserveRegisters` must be saved in
prolog and reloaded in epilog regardless of whether or not they were
modified by the function.
Commit: 3e706075dc1857e88a293b8104c81b31a08f4cd5
https://github.com/llvm/llvm-project/commit/3e706075dc1857e88a293b8104c81b31a08f4cd5
Author: Liza Burakova <liza at chromium.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/include/__pstl/backends/libdispatch.h
Log Message:
-----------
[libc++][pstl] Add missing #pragma GCC system_header to libdispatch.h (#209579)
This adds `#pragma GCC system_header` to libdispatch.h, as removing the
`[system]` attributes in the modulemap surfaced this gap.
Commit: e4a959ffebe24abae49fc93a4f84c58625dabbea
https://github.com/llvm/llvm-project/commit/e4a959ffebe24abae49fc93a4f84c58625dabbea
Author: Florian Mayer <fmayer at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/utils/generate-test-checks.py
Log Message:
-----------
[NFC] [MLIR] fix typo in argument desc (#209587)
Commit: 995b7229bc4a9614669fb57b76c2cddc9fb4db52
https://github.com/llvm/llvm-project/commit/995b7229bc4a9614669fb57b76c2cddc9fb4db52
Author: Scott Linder <scott.linder at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
Log Message:
-----------
[AMDGPU] Fix type for DWARF register number in SIFrameLowering (#209535)
It so happened that using MCRegister here happened to work, but
the encoded dwarf number is definitely not an MCRegister.
Commit: b43a0072fa011ec50c29b683da057730b2682ae2
https://github.com/llvm/llvm-project/commit/b43a0072fa011ec50c29b683da057730b2682ae2
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
Log Message:
-----------
[VPlan] Introduce VPIRFlags::getNWFlagsOrNone (NFC) (#207176)
Similar to getFMFOrNone. Also introduce a default WrapFlagsTy
constructor to go along with it.
Commit: 527396dd7c7370b1649ade49ceb48e48f6f26de1
https://github.com/llvm/llvm-project/commit/527396dd7c7370b1649ade49ceb48e48f6f26de1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/reduce-build-vec-ext-to-ext-build-vec.ll
M llvm/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll
M llvm/test/CodeGen/AMDGPU/reduction.ll
M llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
M llvm/test/CodeGen/AMDGPU/reg-coalescer-subreg-liveness.mir
M llvm/test/CodeGen/AMDGPU/reg-sequence-like-v-pk-mov-b32.mir
M llvm/test/CodeGen/AMDGPU/regalloc-fail-unsatisfiable-overlapping-tuple-hints.mir
M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
M llvm/test/CodeGen/AMDGPU/regalloc-fast-dont-drop-subreg-index-issue61134.mir
M llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.mir
M llvm/test/CodeGen/AMDGPU/regalloc-illegal-eviction-assert.ll
M llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir
M llvm/test/CodeGen/AMDGPU/regalloc-sgpr128-partial-def.mir
M llvm/test/CodeGen/AMDGPU/regalloc-spill-wmma-scale.ll
M llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-64-bit-only-regs.mir
M llvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir
M llvm/test/CodeGen/AMDGPU/register-coalescer--set-undef-full-reg-use-implicit-def-erase-issue109249.mir
M llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
M llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll
M llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
M llvm/test/CodeGen/AMDGPU/reject-agpr-usage-before-gfx908.ll
M llvm/test/CodeGen/AMDGPU/rel32.ll
M llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir
M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12-dvgpr.mir
M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12.mir
M llvm/test/CodeGen/AMDGPU/release-vgprs-spill.ll
M llvm/test/CodeGen/AMDGPU/release-vgprs.mir
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
M llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll
M llvm/test/CodeGen/AMDGPU/remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir
M llvm/test/CodeGen/AMDGPU/remat-smrd.mir
M llvm/test/CodeGen/AMDGPU/remat-sop.mir
M llvm/test/CodeGen/AMDGPU/remat-through-copy.mir
M llvm/test/CodeGen/AMDGPU/remat-vop.mir
M llvm/test/CodeGen/AMDGPU/remove-incompatible-extended-image-insts.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-functions.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-gws.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-s-time.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave32-feature.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave64-feature.ll
M llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
M llvm/test/CodeGen/AMDGPU/remove-not-short-exec-branch-on-unconditional-jump.mir
M llvm/test/CodeGen/AMDGPU/remove-register-flags.mir
M llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-gpr-idx-mode.mir
M llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-special-instructions.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-unused-lanes.ll
M llvm/test/CodeGen/AMDGPU/reorder-stores.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/replace-store-of-insert-load.ll
M llvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/required-export-priority.ll
M llvm/test/CodeGen/AMDGPU/required-export-priority.mir
M llvm/test/CodeGen/AMDGPU/reserved-reg-in-clause.mir
M llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
M llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir
M llvm/test/CodeGen/AMDGPU/resource-usage-dead-function.ll
M llvm/test/CodeGen/AMDGPU/resource-usage-pal.ll
M llvm/test/CodeGen/AMDGPU/ret.ll
M llvm/test/CodeGen/AMDGPU/ret_jump.ll
M llvm/test/CodeGen/AMDGPU/return-with-successors.mir
M llvm/test/CodeGen/AMDGPU/returnaddress.ll
M llvm/test/CodeGen/AMDGPU/rewrite-mfma-form-spill-cost-reset.ll
M llvm/test/CodeGen/AMDGPU/rewrite-out-arguments-address-space.ll
M llvm/test/CodeGen/AMDGPU/rewrite-out-arguments.ll
M llvm/test/CodeGen/AMDGPU/rewrite-undef-for-phi.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-scale-to-agpr.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store-mir.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
M llvm/test/CodeGen/AMDGPU/rotate-add.ll
M llvm/test/CodeGen/AMDGPU/rotl.i64.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.i64.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32-safe.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-id-allocation.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-buffer-load-mmo-offsets.ll
M llvm/test/CodeGen/AMDGPU/s-cluster-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir
M llvm/test/CodeGen/AMDGPU/s_addk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_cmp_0.ll
M llvm/test/CodeGen/AMDGPU/s_code_end.ll
M llvm/test/CodeGen/AMDGPU/s_movk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_or_b32_transformation.ll
M llvm/test/CodeGen/AMDGPU/s_or_saveexec_xor_combine.mir
M llvm/test/CodeGen/AMDGPU/s_uaddo_usubo_pseudo.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/saddsat.ll
M llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (29) (#209558)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: ea56bc30bdabf00e401422f49e9588f1b5ff5e73
https://github.com/llvm/llvm-project/commit/ea56bc30bdabf00e401422f49e9588f1b5ff5e73
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/same-lds-variable-multiple-use-in-one-phi-node.ll
M llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir
M llvm/test/CodeGen/AMDGPU/save-fp.ll
M llvm/test/CodeGen/AMDGPU/scalar-branch-missing-and-exec.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
M llvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll
M llvm/test/CodeGen/AMDGPU/scalarize-insert-subvector.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-scratch.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-post-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-pre-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-dead-def-join.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/sched-image-sample-post-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-ldsdma-mask.mir
M llvm/test/CodeGen/AMDGPU/sched-no-schedmodel.mir
M llvm/test/CodeGen/AMDGPU/sched-prefer-non-mfma.mir
M llvm/test/CodeGen/AMDGPU/sched-setprio.ll
M llvm/test/CodeGen/AMDGPU/sched.group.classification.mir
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_diff_types.mir
M llvm/test/CodeGen/AMDGPU/schedmodel-dummywrite.mir
M llvm/test/CodeGen/AMDGPU/schedule-addrspaces.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg-crash.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/schedule-avoid-spills.ll
M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier-latency.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
M llvm/test/CodeGen/AMDGPU/schedule-ilp-liveness-tracking.mir
M llvm/test/CodeGen/AMDGPU/schedule-ilp.ll
M llvm/test/CodeGen/AMDGPU/schedule-ilp.mir
M llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll
M llvm/test/CodeGen/AMDGPU/schedule-pending-queue.mir
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-lds.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit-clustering.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit2.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit3.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-misched-max-waves.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-no-unclustered-regions.mir
M llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll
M llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll
M llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll
M llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
M llvm/test/CodeGen/AMDGPU/scheduler-rp-calc-one-successor-two-predecessors-bug.ll
M llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll
M llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
M llvm/test/CodeGen/AMDGPU/scratch-pointer-sink.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdivrem24.ll
M llvm/test/CodeGen/AMDGPU/sdwa-commute.ll
M llvm/test/CodeGen/AMDGPU/sdwa-cse.mir
M llvm/test/CodeGen/AMDGPU/sdwa-gfx9.mir
M llvm/test/CodeGen/AMDGPU/sdwa-op64-test.ll
M llvm/test/CodeGen/AMDGPU/sdwa-ops.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-fail.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-sext.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-wave32.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-wave64.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel-dst.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel-src.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
M llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir
M llvm/test/CodeGen/AMDGPU/sdwa-stack.mir
M llvm/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir
M llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll
M llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-int.ll
M llvm/test/CodeGen/AMDGPU/select-constant-xor.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract-legacy.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.legal.f16.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (30) (#209559)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 9035d06155596c1214f302bef2e60b631d38e73a
https://github.com/llvm/llvm-project/commit/9035d06155596c1214f302bef2e60b631d38e73a
Author: Vijay Kandiah <vkandiah at nvidia.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
A flang/test/Fir/CUDA/cuda-managed-descriptor-component.fir
Log Message:
-----------
[flang][cuda] Size managed globals with descriptor components via LLVM Type (#209577)
When we do `-cuda -gpu=unified` (or `managed`) on a derived type with an
allocatable/pointer component, recent change
https://github.com/llvm/llvm-project/pull/209292 implicitly
attributed the component making lowering place the enclosing
derived-type global
in CUF managed memory. `CUFAddConstructor` then sizes that global via
`getTypeSizeAndAlignmentOrCrash`, which has no case for the descriptor
component
(`!fir.box<...>`) and aborts.
With this change, instead of aborting, we fall back to converting the
global to its LLVM type which
inlines the fixed-size descriptors, and query the data layout.
Commit: e3227da7cdb8173c2df465e443a1dc73c71f017b
https://github.com/llvm/llvm-project/commit/e3227da7cdb8173c2df465e443a1dc73c71f017b
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/crash_scatter_load_reorder.ll
Log Message:
-----------
[SLP] Fix ScatterVectorize reorder desyncing scalars from operands
Record the reorder in ReorderIndices instead of permuting the scatter node's
Scalars, keeping them aligned with the per-lane operand list the scheduler
reads.
Fixes #209444
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209594
Commit: 42b67e529c59b77c6dfac9cc5d2b263e752851f6
https://github.com/llvm/llvm-project/commit/42b67e529c59b77c6dfac9cc5d2b263e752851f6
Author: David Young <davidayoung at meta.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/lit/lit/LitConfig.py
A llvm/utils/lit/tests/unit/LitConfig.py
Log Message:
-----------
[lit] Don't crash in _write_message when getsourcefile() returns None (#206957)
LitConfig._write_message currently derives the file to report a
note()/warning()/ error() against with:
file = os.path.abspath(inspect.getsourcefile(f))
inspect.getsourcefile(f) returns None when the calling frame's source is
not on disk and not in linecache -- for example when lit is packaged
into a zip archive, or when a config is exec'd from a synthetic
filename. In that case os.path.abspath(None) raises TypeError: expected
str, bytes or os.PathLike object, not NoneType, which turns an
informational diagnostic into a fatal config-parse crash.
Fall back to inspect.getfile(f), which returns the frame's co_filename
and is always a str, so the diagnostic is emitted (tagged with
co_filename) instead of crashing. Since all tests normally pass
currently on build bots, this new code should never trigger and only
works as a backup in the case I'm running into on a different test infra
running lit tests.
Add a lit unit test covering the None case.
Assisted with- claude
Commit: e0b4701f2621d2542405830008797e3cf319a3f0
https://github.com/llvm/llvm-project/commit/e0b4701f2621d2542405830008797e3cf319a3f0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/select-i1.ll
M llvm/test/CodeGen/AMDGPU/select-load-to-load-select-ptr-combine.ll
M llvm/test/CodeGen/AMDGPU/select-nsz-known-values-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll
M llvm/test/CodeGen/AMDGPU/select-undef.ll
M llvm/test/CodeGen/AMDGPU/select-vectors.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/select64.ll
M llvm/test/CodeGen/AMDGPU/selectcc-opt.ll
M llvm/test/CodeGen/AMDGPU/selectcc.ll
M llvm/test/CodeGen/AMDGPU/sema-v-unsched-bundle.ll
M llvm/test/CodeGen/AMDGPU/sendmsg-m0-hazard.mir
M llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/AMDGPU/set_kill_i1_for_floation_point_comparison.ll
M llvm/test/CodeGen/AMDGPU/setcc-f64-hi32mask.ll
M llvm/test/CodeGen/AMDGPU/setcc-fneg-constant.ll
M llvm/test/CodeGen/AMDGPU/setcc-limit-load-shrink.ll
M llvm/test/CodeGen/AMDGPU/setcc-multiple-use.ll
M llvm/test/CodeGen/AMDGPU/setcc-opt.ll
M llvm/test/CodeGen/AMDGPU/setcc64.ll
M llvm/test/CodeGen/AMDGPU/seto.ll
M llvm/test/CodeGen/AMDGPU/setuo.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/sgpr-count-graphics.ll
M llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
M llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-incorrect-fi-bookkeeping-bug.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spills-empty-prolog-block.mir
M llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.ll
M llvm/test/CodeGen/AMDGPU/shader-addr64-nonuniform.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll
M llvm/test/CodeGen/AMDGPU/shift-select.ll
M llvm/test/CodeGen/AMDGPU/shl-add-to-add-shl.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shl64_reduce.ll
M llvm/test/CodeGen/AMDGPU/shl64_reduce_flags.ll
M llvm/test/CodeGen/AMDGPU/shlN_add.ll
M llvm/test/CodeGen/AMDGPU/shl_add.ll
M llvm/test/CodeGen/AMDGPU/shl_add_constant.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr_csub.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr_global.ll
M llvm/test/CodeGen/AMDGPU/shl_or.ll
M llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/shrink-carry.mir
M llvm/test/CodeGen/AMDGPU/shrink-fma-f64.mir
M llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-implicit-vcclo.mir
M llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
M llvm/test/CodeGen/AMDGPU/shrink-mad-fma-fake16.mir
M llvm/test/CodeGen/AMDGPU/shrink-mad-fma-gfx10.mir
M llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir
M llvm/test/CodeGen/AMDGPU/shrink-true16.mir
M llvm/test/CodeGen/AMDGPU/shrink-v-cmp-wave32-dead-vcc-lo.mir
M llvm/test/CodeGen/AMDGPU/shufflevector-physreg-copy.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v3i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v4i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (31) (#209560)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: d0775bdb7f483b8aa4700b97a65718d5f3c9cfa8
https://github.com/llvm/llvm-project/commit/d0775bdb7f483b8aa4700b97a65718d5f3c9cfa8
Author: lntue <lntue at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libc/src/__support/threads/linux/futex_utils.h
Log Message:
-----------
[libc] Fix potential timespec type mismatch for arm32 targets in futex_utils.h. (#209556)
This causes the arm32 build bots to hang.
Assisted-by: Gemini 3.5 Flash.
Commit: 226b0b59bfca58ef831bd668dcf219a79f11f957
https://github.com/llvm/llvm-project/commit/226b0b59bfca58ef831bd668dcf219a79f11f957
Author: Muhammad Bassiouni <60100307+bassiounix at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/docs/LanguageExtensions.md
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Parse/Parser.h
M clang/lib/Parse/ParseExprCXX.cpp
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Parse/ParseStmt.cpp
A clang/test/C/C2y/n3267.c
M clang/www/c_status.html
Log Message:
-----------
[Clang][C2y] Add support for if declarations (N3356 paper) (#198244)
Add support for _if declarations_ in `C2y` mode by exploiting existing
C++ code.
The only new changes to the code is narrowing the code path to `C` mode
and introduce new errors and warnings for some pitfalls with the syntax
and what is expected from the standard and old language modes.
It should be noted that the first clause in the standard paper can only
be declaration. This means we can't allow expression statement in the
first clause of the condition, and that's the goal of the new
warnings/errors. Also this is different from C++ grammar.
Commit: 21bc62e6688a5dcaf79ebd992e5e4676b287a674
https://github.com/llvm/llvm-project/commit/21bc62e6688a5dcaf79ebd992e5e4676b287a674
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v3i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v4i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v3i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v4i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-kill.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-nested-control-flows.ll
M llvm/test/CodeGen/AMDGPU/si-annotatecfg-multiple-backedges.ll
M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies-av-constrain.mir
M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies-copy-to-sgpr.mir
M llvm/test/CodeGen/AMDGPU/si-fold-aligned-agprs.mir
M llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/si-fold-copy-kills.mir
M llvm/test/CodeGen/AMDGPU/si-fold-kimm.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-bundle.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-commute-same-operands-assert.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-gfx11.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-requires-ssa.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.gfx942.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.mir
M llvm/test/CodeGen/AMDGPU/si-fold-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/si-fold-scalar-add-sub-imm.mir
M llvm/test/CodeGen/AMDGPU/si-fold-scalar-clamp.mir
M llvm/test/CodeGen/AMDGPU/si-init-whole-wave.mir
M llvm/test/CodeGen/AMDGPU/si-insert-hard-clauses-no-nesting.mir
M llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
M llvm/test/CodeGen/AMDGPU/si-instr-info-vopc-exec.mir
M llvm/test/CodeGen/AMDGPU/si-late-branch-lowering-preserve-loop-info.mir
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-preserve-dom-tree.mir
M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies-order-of-phi-incomings.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.ll
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
M llvm/test/CodeGen/AMDGPU/si-lower-wwm-copies.mir
M llvm/test/CodeGen/AMDGPU/si-opt-vgpr-liverange-bug-deadlanes.mir
M llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.ll
M llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.mir
M llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
M llvm/test/CodeGen/AMDGPU/si-pre-emit-peephole-preserve-loop-info.mir
M llvm/test/CodeGen/AMDGPU/si-scheduler-exports.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (32) (#209561)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: fc0b032ba8b56f02e834847ec3e2a6375011017f
https://github.com/llvm/llvm-project/commit/fc0b032ba8b56f02e834847ec3e2a6375011017f
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
R llvm/test/Transforms/SampleProfile/icp_target_feature.ll
Log Message:
-----------
Revert "[PGO][ICP] Prevent indirect call promotion to functions with incompatible target features" (#209572)
Reverts llvm/llvm-project#208774
The failure that caused the revert last time should be fixed by
37b8e765ce4837a7577e6f762bcdffe4b232759c.
Commit: 5245afc014c4d34705bf8734fc835bcbfe9b6f39
https://github.com/llvm/llvm-project/commit/5245afc014c4d34705bf8734fc835bcbfe9b6f39
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/SPIRV/vk-pushconstant-layout.ll
Log Message:
-----------
[NFC][SPIR-V] Remove stale XFAIL in vk-pushconstant-layout.ll (#209447)
Commit: f69342fa200100560c689e0ccdbbc5c3249aee4b
https://github.com/llvm/llvm-project/commit/f69342fa200100560c689e0ccdbbc5c3249aee4b
Author: Mike Kruskal <mkruskal at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_nolibc.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_dl.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_dl.h
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/tsan/go/buildgo.sh
M compiler-rt/test/sanitizer_common/TestCases/Linux/dlopen_image_base.c
Log Message:
-----------
Reland "[compiler-rt] [sanitizer_common] Fix SIGSEGV in ForEachMappedRegion for DSOs with custom image base" (#209576)
Attempt 2 at #206299, fixing a linkage issue with gotsan on older
versions of glibc. Rather than forcing linkage of libdl (which may not
be safe with go), this just disables the dladdr usage under go builds.
This bug only affected MSAN and DFSAN anyway, and the code should be
unused by TSAN.
`ForEachMappedRegion` processes dynamic linker map entries to track
loaded segments. However, it assumes map->l_addr is the address of the
ELF header. For DSOs linked with a custom preferred image base offset
(e.g. -Wl,--image-base=0x4000000), `map->l_addr` contains the relocation
bias: `map->l_addr = actual_load_address - preferred_base`
In this case, map->l_addr points below the first loaded segment in
unmapped or PROT_NONE memory. Doing a read dereference at this address
triggers a SIGSEGV. Add a call to dladdr() on the dynamic section
pointer map->l_ld to obtain the true ELF header base address.
Likely fixes https://github.com/llvm/llvm-project/issues/84482 - which
looks like the exact same stacktrace I was debugging that led me to this
fix
Also looks it may have shown up in
https://github.com/llvm/llvm-project/issues/21068 - my case was also
flaky, and it only shows up if you build the so with custom base address
Assisted-by: Gemini
Commit: 0fae10b74b93723b4a2a53804331696c1b37fe14
https://github.com/llvm/llvm-project/commit/0fae10b74b93723b4a2a53804331696c1b37fe14
Author: Scott Linder <scott.linder at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir
Log Message:
-----------
[AMDGPU] Add stackPtrOffsetReg to llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir (#209533)
Prepare for this being observable to the CFA generation code.
Commit: d218bc40aba65687ddc2fb616a154b2799631f0f
https://github.com/llvm/llvm-project/commit/d218bc40aba65687ddc2fb616a154b2799631f0f
Author: Kyungtak Woo <kevinwkt at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/Assembler/thinlto-bad-summary-5.ll
Log Message:
-----------
[ThinLTO] Fix thinlto-bad-summary-5.ll in read-only environments (#209513)
The test thinlto-bad-summary-5.ll was failing in read-only environments
(such as sandboxed test runners) because it attempted to write the
output bitcode file to the same directory as the input file, resulting
in a "Permission denied" error.
Fix this by redirecting the output to /dev/null using `-o /dev/null`.
We cannot use `-disable-output` here because the error we want to
test is triggered inside the BitcodeWriter, which is bypassed when
output is disabled.
assisted by gemini
Commit: fbba327208d7f6994f9a28a51dca3e913e3b444a
https://github.com/llvm/llvm-project/commit/fbba327208d7f6994f9a28a51dca3e913e3b444a
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/cmake/modules/HandleLLVMOptions.cmake
Log Message:
-----------
[CMake] Add -Wl,-z,pack-relative-relocs if supported (#208217)
We should aim to provide a good experience by default. Enable RELR for
PIC builds (which is on by default, even in non-dylib builds) if
supported by the linker (feature-tested) and the libc (currently
hardcoded as glibc 2.36+; musl has no easy way to determine support).
RELR substantially reduces the size of the dynamic relocations in PIE
executables and shared libraries and therefore also lowers max-rss and
startup time due to fewer page faults.
Commit: fc298ccbc52a9199a2181d30fa6e7189c374c091
https://github.com/llvm/llvm-project/commit/fc298ccbc52a9199a2181d30fa6e7189c374c091
Author: firmiana <firmiana402 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/source/Expression/DWARFExpression.cpp
M lldb/unittests/Expression/DWARFExpressionTest.cpp
Log Message:
-----------
[lldb] Reject mixed typed DWARF binary operands (#201288)
## Summary
LLDB currently accepts and evaluates some ill-typed DWARF typed binary
operations whose two operands have different base types.
DWARF v5 typed-expression rules require arithmetic/logical and
relational binary operators to operate on operands of the same type,
either the same base type or the generic type. (see [DWARF v5
doc](https://dwarfstd.org/doc/DWARF5.pdf) Section 2.5.1.4)
This patch adds an explicit compatibility check before evaluating the
affected binary operators.
## Example
A DWARF expression illustrating the issue is:
```text
DW_OP_constu 0xff
DW_OP_convert <unsigned char>
DW_OP_constu 0x1
DW_OP_convert <short unsigned int>
DW_OP_plus
DW_OP_stack_value
```
The left operand is typed as unsigned char, while the right operand is
typed as short unsigned int. These are different DWARF base types, so
`DW_OP_plus` should reject the expression instead of evaluating it.
In differential testing, GDB rejects this kind of expression with:
```text
Incompatible types on DWARF stack
```
Before this patch, LLDB continued evaluating the expression and produced
a concrete result through the existing `Scalar` arithmetic path.
## Affected operations
The issue is not specific to DW_OP_plus. The same acceptance pattern was
observed for mixed-base-type typed operands across these binary
operations:
- Arithmetic: `DW_OP_plus`, `DW_OP_minus`, `DW_OP_div`, `DW_OP_mod`
- Bitwise: `DW_OP_and`, `DW_OP_or`, `DW_OP_xor`
- Shifts: `DW_OP_shl`, `DW_OP_shr`, `DW_OP_shra`
- Relations: `DW_OP_lt`, `DW_OP_le`, `DW_OP_gt`, `DW_OP_ge`, `DW_OP_eq`,
`DW_OP_ne`
## Implementation notes
LLDB's DWARF expression stack currently stores `Value` objects, whose
scalar payload is represented by `Scalar`. `Scalar` does not preserve
the original DWARF base type DIE, but it does carry the pieces of
base-type information used by the evaluator:
- scalar kind
- byte size
- integer signedness
This patch therefore checks those `Scalar` properties before dispatching
each affected binary operation to the existing arithmetic/comparison
logic. If the two operands do not match, evaluation now stops with an
error.
This **PR Text** was prepared with assistance from Codex. I reviewed the
PR Text and take responsibility for the contribution.
Commit: 3ba1b70dc2f4920d727ec1e678a79b744ce72b99
https://github.com/llvm/llvm-project/commit/3ba1b70dc2f4920d727ec1e678a79b744ce72b99
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
M llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir
Log Message:
-----------
[AMDGPU][CodeGen] Fix `S_NOP` insertion during `S_SET_VGPR_MSB` placement (#209525)
The issue arises when co-issue optimizations move the initial insertion
position for `S_SET_VGPR_MSB` to an earlier spot, creating a mismatch
with the position used to determine whether a `S_NOP` is needed.
Commit: 0b908e100f3d88232aa3b0190e23e41ca327edf1
https://github.com/llvm/llvm-project/commit/0b908e100f3d88232aa3b0190e23e41ca327edf1
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/test/Driver/msvc-link.c
Log Message:
-----------
[clang][test] Avoid relying on `-fuse-ld=ld` default value for marm64x test (#209597)
Test case added in #209324
Commit: 2c31050a6cf609285b0561b9a7c262fa4cf790c8
https://github.com/llvm/llvm-project/commit/2c31050a6cf609285b0561b9a7c262fa4cf790c8
Author: lntue <lntue at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M .github/workflows/libc-overlay-tests.yml
Log Message:
-----------
[libc][ci] Add qemu armhf overlay tests to precommit CI. (#203369)
Commit: eecd874fba6cef85071f8e02afc81c81e9d352e5
https://github.com/llvm/llvm-project/commit/eecd874fba6cef85071f8e02afc81c81e9d352e5
Author: Hansang Bae <hansang.bae at intel.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M offload/plugins-nextgen/common/src/RecordReplay.cpp
Log Message:
-----------
[Offload] Remove unnecessary assert (#209518)
`uint32_t` is always greater than or equal to zero.
Commit: 04aa50715cafa5f205b44bc88a6f721d296ec91c
https://github.com/llvm/llvm-project/commit/04aa50715cafa5f205b44bc88a6f721d296ec91c
Author: Hans Wennborg <hans at hanshq.net>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/AST/DeclCXX.cpp
M clang/test/CXX/drs/cwg15xx.cpp
M clang/test/CodeGenCXX/devirtualize-virtual-function-calls.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
Revert "[Clang] Allow devirtualization involving array subscripts with constant indices when the pointee type is known [CWG1504] (#207540) (#209596)
It caused miscompiles, see discussion on the PR.
This reverts commit ee24ac00d874ce82eaf36431f9aeb2ad744bc3b8.
Commit: 73615e792dc3116d5c66cb8175039dd6d4840f31
https://github.com/llvm/llvm-project/commit/73615e792dc3116d5c66cb8175039dd6d4840f31
Author: Pawan Nirpal <pnirpal at qti.qualcomm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
A llvm/test/CodeGen/ARM/thumb1-copy-physreg-dbg-value-crash.ll
Log Message:
-----------
[ARM] - Fix Thumb1InstrInfo::copyPhysReg crash on debug instructions during liveness walk. (#209478)
clang asserts when compiling with -mthumb -mcpu=arm926ej-s -O0 -g
(pre-v6 Thumb1, debug info enabled). The crash occurs in
LiveRegUnits::stepBackward which unconditionally asserts that it must
never be called on a debug instruction, but Thumb1InstrInfo::copyPhysReg
walks the basic block backward without skipping DBG_VALUE instructions.
Fixes: https://github.com/llvm/llvm-project/issues/209475
Commit: d089325bad0e85c1be958d54cfbf9d44bf02fcf1
https://github.com/llvm/llvm-project/commit/d089325bad0e85c1be958d54cfbf9d44bf02fcf1
Author: Scott Linder <scott.linder at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-scc-clobber.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
M llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
M llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir
M llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir
M llvm/test/CodeGen/AMDGPU/spillv16.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir
Log Message:
-----------
[AMDGPU] Fix CFI emission when scratch instructions are used to spill (#209534)
4b1cfc5d7c606e "[NFCI][AMDGPU] Final touch before moving to
`GET_SUBTARGETINFO_MACRO` (#177401)" (or more generally the move to
hasFlatScratchEnabled over just enableFlatScratch) was missed during the
CFI upstreaming for AMDGPU, and so we currently define the CFA
incorrectly for the architected flat scratch case.
This incorrect CFI is generated for e.g. gfx942. For such architecture,
the stack pointer (s32) holds a swizzled address (per-lane offset) but
the CFA needs to be an unswizzled address (per-wave).
In the incorrect program, we have a prologue looking like:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_mov_b32 s0, s33
s_mov_b32 s33, s32
[...]
s_add_i32 s32, s32, 16
[...]
(16 is a per-lane offset) but CFA ends up being defined as
DW_CFA_LLVM_def_aspace_cfa: SGPR32 +0 in addrspace6
with addrspace6 being DW_ASPACE_AMDGPU_private_wave. The correct CFA
should instead be:
DW_CFA_def_cfa_expression: DW_OP_regx SGPR32, DW_OP_deref_size 0x4,
DW_OP_lit6, DW_OP_shl, DW_OP_lit6, DW_OP_LLVM_user
DW_OP_LLVM_form_aspace_address
which converts from swizzled to unswizzled.
Deciding which form to use is done in SIFrameLowering::emitDefCFA which
still uses the old ST.enableFlatScratch() instead of
ST.hasFlatScratchEnabled(). This patch fixes this as well as the other
user of enableFlatScratch in createScaledCFAInPrivateWave.
The naming for the "enable-flat-scratch" feature seems unfortunate in
retrospect, although I'm not sure we can change it easily at this point?
CFI generation tested for gfx942 and gfx1031 with ROCgdb's testsuite.
Commit: db9efd93912b71e5ec200549b17391696dcae18f
https://github.com/llvm/llvm-project/commit/db9efd93912b71e5ec200549b17391696dcae18f
Author: Xi Ruoyao <xry111 at xry111.site>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/test/CodeGen/Mips/divrem.ll
Log Message:
-----------
[Mips] Do not emit teq if NoZeroDivCheck in FastISel (#204386)
Fix the issue: -mno-check-zero-division is not respected at -O0 for some
test cases.
Co-authored-by: Folkert de Vries <folkert at folkertdev.nl>
Commit: ae21f63afa4a1d5a6d120bbe194523f3ff316131
https://github.com/llvm/llvm-project/commit/ae21f63afa4a1d5a6d120bbe194523f3ff316131
Author: Ziqing Luo <ziqing_luo at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M .github/workflows/containers/github-action-ci-windows/Dockerfile
M .github/workflows/containers/github-action-ci/Dockerfile
M .github/workflows/libc-overlay-tests.yml
M clang-tools-extra/clang-doc/CMakeLists.txt
M clang-tools-extra/clang-doc/Generators.cpp
M clang-tools-extra/clang-doc/Generators.h
M clang-tools-extra/clang-doc/Representation.h
R clang-tools-extra/clang-doc/YAMLGenerator.cpp
M clang-tools-extra/clang-doc/tool/ClangDocMain.cpp
M clang-tools-extra/clang-tidy/misc/RedundantExpressionCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseScopedLockCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/use-scoped-lock.rst
R clang-tools-extra/test/clang-doc/yaml/builtin_types.cpp
R clang-tools-extra/test/clang-doc/yaml/conversion_function.cpp
R clang-tools-extra/test/clang-doc/yaml/single-file-public.cpp
R clang-tools-extra/test/clang-doc/yaml/single-file.cpp
R clang-tools-extra/test/clang-doc/yaml/templates.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/redundant-expression.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-scoped-lock-warn-on-single-locks-false.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-scoped-lock.cpp
M clang-tools-extra/unittests/clang-doc/CMakeLists.txt
R clang-tools-extra/unittests/clang-doc/YAMLGeneratorTest.cpp
M clang/docs/LanguageExtensions.md
M clang/docs/ReleaseNotes.md
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LiveOrigins.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LoanPropagation.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/MovedLoans.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/Utils.h
M clang/include/clang/Analysis/Analyses/LiveVariables.h
M clang/include/clang/Basic/AArch64CodeGenUtils.h
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/arm_neon.td
M clang/include/clang/Parse/Parser.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/AST/DeclCXX.cpp
M clang/lib/Analysis/LiveVariables.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Format/CMakeLists.txt
M clang/lib/Lex/Preprocessor.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseExprCXX.cpp
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Sema/DeclSpec.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
M clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.h
A clang/lib/StaticAnalyzer/Checkers/ReportDanglingPtrDeref.cpp
A clang/test/Analysis/dangling-ptr-deref.cpp
A clang/test/C/C2y/n3267.c
M clang/test/CXX/drs/cwg15xx.cpp
M clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c
M clang/test/CodeGen/AArch64/neon/fullfp16.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
M clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
M clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
M clang/test/CodeGen/builtins.c
M clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
M clang/test/CodeGen/memcpy-inline-builtin.c
M clang/test/CodeGen/pr9614.c
M clang/test/CodeGenCUDA/device-stub.cu
M clang/test/CodeGenCXX/devirtualize-virtual-function-calls.cpp
M clang/test/Driver/msvc-link.c
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
M clang/test/Parser/cxx-default-args.cpp
M clang/test/Sema/aarch64-neon-target.c
M clang/test/Sema/aarch64-neon-without-target-feature.cpp
M clang/test/SemaCXX/auto-cxx0x.cpp
M clang/test/SemaCXX/concepts-subsumption.cpp
M clang/test/SemaCXX/recovery-expr-type.cpp
A clang/test/SemaTemplate/GH195988.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/unittests/StaticAnalyzer/FalsePositiveRefutationBRVisitorTest.cpp
M clang/www/c_status.html
M clang/www/cxx_dr_status.html
M cmake/Modules/LLVMVersion.cmake
M compiler-rt/lib/asan/AIX/asan.link_with_main_exec.txt
M compiler-rt/lib/asan/asan_malloc_linux.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_dl.cpp
M compiler-rt/test/asan/TestCases/AIX/vec_malloc_calloc.cpp
A cross-project-tests/dtlto/cache-extraction.test
R cross-project-tests/dtlto/cache-serialization.test
M flang-rt/CMakeLists.txt
M flang/docs/ReleaseNotes.md
M flang/include/flang/Optimizer/Dialect/FIROpsSupport.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/OpenMP/AutomapToTargetData.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Support/CMakeLists.txt
M flang/lib/Optimizer/Support/InitFIR.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
M flang/lib/Optimizer/Transforms/FunctionAttr.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Analysis/AliasAnalysis/alias-analysis-omp-private-boxed-wsloop.mlir
A flang/test/Analysis/AliasAnalysis/alias-analysis-omp-private-unboxed-wsloop.mlir
A flang/test/Driver/function-attr-readonly.f90
A flang/test/Evaluate/fold-kind-logical.f90
A flang/test/Evaluate/fold-kind-substring.f90
A flang/test/Evaluate/fold-kind-zero-size.f90
M flang/test/Evaluate/logical-args.f90
A flang/test/Fir/CUDA/cuda-managed-descriptor-component.fir
A flang/test/Lower/CUDA/cuda-implicit-managed-alloc.cuf
A flang/test/Lower/HLFIR/array-ctor-character-kind.f90
M flang/test/Lower/HLFIR/structure-constructor.f90
M flang/test/Lower/Intrinsics/dconjg.f90
M flang/test/Lower/Intrinsics/dimag.f90
M flang/test/Lower/Intrinsics/dreal.f90
A flang/test/Lower/OpenMP/declare-target-automap.f90
M flang/test/Lower/OpenMP/optional-argument-map.f90
M flang/test/Lower/OpenMP/wsloop-unstructured.f90
M flang/test/Lower/achar.f90
M flang/test/Lower/arguments.f90
M flang/test/Lower/call-copy-in-out.f90
M flang/test/Lower/dispatch.f90
A flang/test/Lower/dummy-argument-readonly.f90
M flang/test/Lower/polymorphic-temp.f90
M flang/test/Lower/polymorphic.f90
M flang/test/Lower/select-type.f90
M flang/test/Lower/unsigned-ops.f90
M flang/test/Lower/volatile1.f90
A flang/test/Semantics/modfile84.F90
A flang/test/Semantics/substring-literal-kind.f90
A flang/test/Transforms/function-attrs-readonly.fir
M flang/test/Transforms/omp-automap-to-target-data.fir
M libc/include/llvm-libc-macros/gpu/signal-macros.h
M libc/include/llvm-libc-macros/linux/signal-macros.h
M libc/include/llvm-libc-macros/netinet-in-macros.h
M libc/include/llvm-libc-types/__futex_word.h
M libc/include/sys/prctl.h.def
M libc/src/__support/threads/linux/futex_utils.h
M libc/test/src/signal/sigaction_test.cpp
M libc/test/src/sys/mman/linux/posix_madvise_test.cpp
M libcxx/cmake/Modules/HandleLibCXXABI.cmake
M libcxx/docs/Status/Cxx20Papers.csv
M libcxx/docs/Status/Cxx23Issues.csv
M libcxx/include/__config
M libcxx/include/__pstl/backends/libdispatch.h
M libcxx/src/atomic.cpp
M libcxx/src/include/overridable_function.h
M libcxx/src/new.cpp
M libcxx/test/benchmarks/algorithms/min.bench.cpp
M libcxx/test/benchmarks/algorithms/minmax.bench.cpp
M libcxx/test/benchmarks/algorithms/nonmodifying/search_n.bench.cpp
M libcxx/test/std/ranges/range.utility/view.interface/view.interface.pass.cpp
M libcxxabi/src/stdlib_new_delete.cpp
A libunwind/test/.clang-format
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/MarkLive.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/Writer.cpp
M lld/docs/ReleaseNotes.rst
M lld/docs/ld.lld.1
M lld/test/ELF/dtlto/timetrace.test
M lld/test/ELF/retain-symbols-file.s
M lld/test/ELF/version-script-warn.s
M lldb/bindings/interface/SBTargetDocstrings.i
M lldb/docs/resources/lldbgdbremote.md
M lldb/docs/use/tutorial.md
M lldb/include/lldb/Core/PluginManager.h
M lldb/include/lldb/Utility/Log.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/__init__.py
R lldb/packages/Python/lldbsuite/test/tools/lldb_dap/dap_types.py
R lldb/packages/Python/lldbsuite/test/tools/lldb_dap/lldb_dap_testcase.py
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session.py
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
A lldb/packages/Python/lldbsuite/test/tools/lldb_dap/testcase.py
A lldb/packages/Python/lldbsuite/test/tools/lldb_dap/types.py
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/utils.py
M lldb/source/Breakpoint/Watchpoint.cpp
M lldb/source/Commands/CommandObjectLog.cpp
M lldb/source/Core/PluginManager.cpp
M lldb/source/Expression/DWARFExpression.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/OperatingSystemPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/OperatingSystemPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedBreakpointPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedFrameProviderPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedFramePythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedFramePythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedHookPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPlatformPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPlanPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPythonInterface.h
M lldb/source/Plugins/SymbolLocator/SymStore/CMakeLists.txt
M lldb/source/Utility/Log.cpp
M lldb/source/Utility/Policy.cpp
M lldb/test/API/tools/lldb-dap/exception/TestDAP_exception.py
M lldb/test/API/tools/lldb-dap/exception/asan/TestDAP_asan.py
M lldb/test/API/tools/lldb-dap/exception/cpp/TestDAP_exception_cpp.py
M lldb/test/API/tools/lldb-dap/exception/objc/TestDAP_exception_objc.py
M lldb/test/API/tools/lldb-dap/exception/ubsan/TestDAP_ubsan.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_args.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_basic.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_cwd.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_debuggerRoot.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_disableSTDIO.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_environment_with_array.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_environment_with_object.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_extra_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_failing_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_failing_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_invalid_launch_commands_and_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_invalid_program.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_no_lldbinit_flag.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_shellExpandArguments_disabled.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_shellExpandArguments_enabled.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_sourcePath.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection_and_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stopOnEntry.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_terminate_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_termination.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_version.py
M lldb/test/API/tools/lldb-dap/module-event/TestDAP_module_event.py
M lldb/test/API/tools/lldb-dap/module/TestDAP_module.py
M lldb/test/API/tools/lldb-dap/moduleSymbols/TestDAP_moduleSymbols.py
M lldb/test/API/tools/lldb-dap/stackTrace/TestDAP_stackTrace.py
M lldb/test/API/tools/lldb-dap/stackTraceCompilerGeneratedCode/TestDAP_stackTraceCompilerGeneratedCode.py
M lldb/test/API/tools/lldb-dap/stackTraceDisassemblyDisplay/TestDAP_stackTraceDisassemblyDisplay.py
M lldb/test/API/tools/lldb-dap/stackTraceMissingFunctionName/TestDAP_stackTraceMissingFunctionName.py
M lldb/test/API/tools/lldb-dap/stackTraceMissingModule/TestDAP_stackTraceMissingModule.py
M lldb/test/API/tools/lldb-dap/utils/TestDAPUtils_DAPConnection.py
M lldb/test/API/tools/lldb-dap/utils/TestDAPUtils_EventHistory.py
M lldb/test/API/tools/lldb-dap/utils/TestDAPUtils_Types.py
M lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py
M lldb/test/API/tools/lldb-dap/variables/children/TestDAP_variables_children.py
M lldb/test/Shell/Commands/command-scripting-extension-list.test
M lldb/test/Shell/Register/x86-db-read.test
M lldb/tools/lldb-dap/DAPSessionManager.cpp
M lldb/unittests/Expression/DWARFExpressionTest.cpp
M lldb/unittests/Utility/LogTest.cpp
M llvm/benchmarks/ImmutableSetBuildBM.cpp
M llvm/benchmarks/ImmutableSetIteratorBM.cpp
M llvm/cmake/modules/FindDIASDK.cmake
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CommandGuide/lit.rst
M llvm/docs/LangRef.md
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/ADT/ImmutableMap.h
M llvm/include/llvm/ADT/ImmutableSet.h
M llvm/include/llvm/Analysis/CGSCCPassManager.h
M llvm/include/llvm/Analysis/ModuleSummaryAnalysis.h
M llvm/include/llvm/CodeGen/MachineBlockPlacement.h
M llvm/include/llvm/CodeGen/MachinePassManager.h
M llvm/include/llvm/CodeGen/RegisterCoalescerPass.h
M llvm/include/llvm/CodeGen/Rematerializer.h
M llvm/include/llvm/CodeGen/RenameIndependentSubregs.h
M llvm/include/llvm/CodeGen/TargetFrameLowering.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGen/TwoAddressInstructionPass.h
M llvm/include/llvm/CodeGen/UnreachableBlockElim.h
M llvm/include/llvm/DTLTO/DTLTO.h
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
M llvm/include/llvm/IR/PassManager.h
M llvm/include/llvm/IR/PassManagerInternal.h
M llvm/include/llvm/LTO/LTO.h
M llvm/include/llvm/Object/IRSymtab.h
M llvm/include/llvm/Passes/OptimizationLevel.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/include/llvm/Transforms/IPO/ExpandVariadics.h
M llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
M llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h
M llvm/include/llvm/Transforms/Utils/UnifyLoopExits.h
M llvm/lib/Analysis/InlineCost.cpp
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolutionDivision.cpp
M llvm/lib/Analysis/StackSafetyAnalysis.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
M llvm/lib/DTLTO/DTLTO.cpp
M llvm/lib/DTLTO/DTLTOInputFiles.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Object/ArchiveWriter.cpp
M llvm/lib/Object/OffloadBinary.cpp
M llvm/lib/Passes/CMakeLists.txt
R llvm/lib/Passes/OptimizationLevel.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Support/KnownBits.cpp
M llvm/lib/Support/Windows/DynamicLibrary.inc
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNNSAReassign.h
M llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
M llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h
M llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SILowerControlFlow.h
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
M llvm/lib/Target/AMDGPU/SILowerWWMCopies.h
M llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYTargetStreamer.h
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/Hexagon/HexagonPatterns.td
M llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrPredicates.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/SystemZ/SystemZInstrVector.td
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86WinEHUnwindV3.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/Transforms/IPO/AlwaysInliner.cpp
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
A llvm/test/Assembler/thinlto-bad-summary-5.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-avg.mir
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M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-udiv.mir
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M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/branch-cond-split-fcmp.ll
M llvm/test/CodeGen/AArch64/clmul.ll
M llvm/test/CodeGen/AArch64/fold-sext-in-reg-predicate-fixed-length.ll
M llvm/test/CodeGen/AArch64/get-active-lane-mask-extract.ll
M llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/round-fptoui-sat-scalar.ll
M llvm/test/CodeGen/AArch64/sve-cmp-folds.ll
M llvm/test/CodeGen/AArch64/sve-mask-partition.ll
M llvm/test/CodeGen/AArch64/sve2p1-while-pn-folds.ll
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-014bb.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-cfg-with-self-loop.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-phi-merge-distances.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-acyclic-cfg-with-4-self-loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-11blocks.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-15blocks.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop-a.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/if_else_with_loops_nested_in_2_outer_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/inner_cfg_in_2_nested_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/loop_nested_in_3_outer_loops_complex_cfg.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/nested-loops-with-side-exits-a.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/sequence_2_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/simple-loop-3blocks.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_basic_case.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_do_not_spill_restore_inside_loop.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_common_dominator.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader1.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader2.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader3.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader4.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_keep_spilled_reg_live.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_nested_loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_in_common_dominator_and_optimize_restores.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_livethrough_reg.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_value_in_exit_block.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/three-tier-ranking-nested-loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/triple-nested-loops.mir
M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/two-sequential-loops.mir
A llvm/test/CodeGen/AMDGPU/atomic_optimizations_dpp_lds_expected_active_lanes.ll
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-scc-clobber.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
A llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-hsa.ll
A llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-rel32.mir
A llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr.ll
M llvm/test/CodeGen/AMDGPU/intrinsic-amdgcn-s-alloc-vgpr.ll
M llvm/test/CodeGen/AMDGPU/invalid-cast-load-i1.ll
M llvm/test/CodeGen/AMDGPU/invalid-hidden-kernarg-in-kernel-signature.ll
M llvm/test/CodeGen/AMDGPU/invariant-image-load.ll
M llvm/test/CodeGen/AMDGPU/ipra.ll
M llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/issue121601-combine-concat-vectors-assumes-f16.ll
M llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
M llvm/test/CodeGen/AMDGPU/issue139317-bad-opsel-reg-sequence-fold.ll
M llvm/test/CodeGen/AMDGPU/issue153808-extract-subvector-legalize.ll
M llvm/test/CodeGen/AMDGPU/issue176966-extend-vector-inreg.ll
M llvm/test/CodeGen/AMDGPU/issue48473.mir
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
M llvm/test/CodeGen/AMDGPU/issue98474-assigned-physreg-interference.mir
M llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll
M llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir
M llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/kernarg-size.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
M llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/kill-true-in-return-block.ll
M llvm/test/CodeGen/AMDGPU/known-never-nan.ll
M llvm/test/CodeGen/AMDGPU/known-never-snan.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll
M llvm/test/CodeGen/AMDGPU/large-avgpr-assign-last.mir
M llvm/test/CodeGen/AMDGPU/large-constant-initializer.ll
M llvm/test/CodeGen/AMDGPU/large-phi-search.ll
M llvm/test/CodeGen/AMDGPU/large-work-group-promote-alloca.ll
M llvm/test/CodeGen/AMDGPU/lds-barrier-memoperand.ll
M llvm/test/CodeGen/AMDGPU/lds-bounds.ll
M llvm/test/CodeGen/AMDGPU/lds-branch-vmem-hazard.mir
M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx11.mir
M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx12.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-hazards.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll
M llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll
M llvm/test/CodeGen/AMDGPU/lds-initializer.ll
M llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-agpr.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-callgraph.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-named-barrier.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-typeid.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-named-barrier.ll
M llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/lds-mixed-absolute-addresses-unused.ll
M llvm/test/CodeGen/AMDGPU/lds-mixed-absolute-dynlds.ll
M llvm/test/CodeGen/AMDGPU/lds-no-realign-allocated-variables.ll
M llvm/test/CodeGen/AMDGPU/lds-reject-anonymous-kernels.ll
M llvm/test/CodeGen/AMDGPU/lds-reject-mixed-absolute-addresses.ll
M llvm/test/CodeGen/AMDGPU/lds-relocs.ll
M llvm/test/CodeGen/AMDGPU/lds-run-twice-absolute-md.ll
M llvm/test/CodeGen/AMDGPU/lds-run-twice.ll
M llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx950.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.dead.mir
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-fp-load-invariant.ll
M llvm/test/CodeGen/AMDGPU/legalize-soffset-mbuf.ll
M llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
M llvm/test/CodeGen/AMDGPU/licm-valu.mir
M llvm/test/CodeGen/AMDGPU/licm-wwm.mir
M llvm/test/CodeGen/AMDGPU/limit-soft-clause-reg-pressure.mir
M llvm/test/CodeGen/AMDGPU/literal-constant-like-operand-instruction-size.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/live-interval-bug-in-rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/liveout-implicit-def-subreg-redef-blender-verifier-error.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.add.min.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.addrspacecast.nonnull.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load-last-use.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.lds.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.flat.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-agent.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-basic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-singlethread.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-system.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-wavefront.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-workgroup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f32.fp8.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.e5m3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.off.f32.i4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.pk.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dot4.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.add.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.append.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.async.barrier.arrive.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.fi.b32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.push.pop.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.consume.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-bundle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.br.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.p.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.v.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add-errors.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add-unsupported.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.read.tr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.sub.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.prim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir
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M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
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M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.mir
M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/merge-buffer-gfx12.mir
M llvm/test/CodeGen/AMDGPU/merge-buffer.mir
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M llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-saddr-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
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M llvm/test/CodeGen/AMDGPU/merge-image-load-gfx11.mir
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M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
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M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select-gfx942.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/min-waves-per-eu-not-respected.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/min3.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
M llvm/test/CodeGen/AMDGPU/mir-dynamic-vgpr-block-size-roundtrip.mir
M llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir
M llvm/test/CodeGen/AMDGPU/misched-into-wmma-hazard-shadow.mir
M llvm/test/CodeGen/AMDGPU/misched-killflags.mir
M llvm/test/CodeGen/AMDGPU/missing-store.ll
M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
M llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll
M llvm/test/CodeGen/AMDGPU/mixed_wave32_wave64.ll
M llvm/test/CodeGen/AMDGPU/mmo-target-flags-folding.ll
M llvm/test/CodeGen/AMDGPU/mmra.ll
M llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus.mir
M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/mode-register.mir
M llvm/test/CodeGen/AMDGPU/modf-constant-fold.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll
M llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu-flat.mir
M llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-absdiff.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-lshl_add.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-lshlrev.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll
M llvm/test/CodeGen/AMDGPU/movreld-bug.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
M llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
M llvm/test/CodeGen/AMDGPU/mubuf.ll
M llvm/test/CodeGen/AMDGPU/mul.i16.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multi-call-resource-usage-mcexpr.ll
M llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
M llvm/test/CodeGen/AMDGPU/multi-dword-vgpr-spill.ll
M llvm/test/CodeGen/AMDGPU/multi-use-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/naked-fn-with-frame-pointer.ll
M llvm/test/CodeGen/AMDGPU/nand.ll
M llvm/test/CodeGen/AMDGPU/narrow_math_for_and.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/neg_ashr64_reduce.ll
M llvm/test/CodeGen/AMDGPU/neighboring-mfma-padding.mir
M llvm/test/CodeGen/AMDGPU/nested-calls.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/no-bundle-asm.ll
M llvm/test/CodeGen/AMDGPU/no-corresponding-integer-type.ll
M llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
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M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir
M llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
M llvm/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll
M llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir
M llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
M llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
M llvm/test/CodeGen/AMDGPU/nofpclass-call.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/noop-shader-O0.ll
M llvm/test/CodeGen/AMDGPU/nop-data.ll
M llvm/test/CodeGen/AMDGPU/nor-divergent-lanemask.ll
M llvm/test/CodeGen/AMDGPU/nor.ll
M llvm/test/CodeGen/AMDGPU/nsa-reassign.ll
M llvm/test/CodeGen/AMDGPU/nsa-reassign.mir
M llvm/test/CodeGen/AMDGPU/nsa-vmem-hazard.mir
M llvm/test/CodeGen/AMDGPU/object-linking-local-resources.ll
M llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-and-hostcall.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-pipeline.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-unsupported.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf.ll
M llvm/test/CodeGen/AMDGPU/operand-folding.ll
M llvm/test/CodeGen/AMDGPU/operand-spacing.ll
M llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness-wave32.mir
M llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness.mir
M llvm/test/CodeGen/AMDGPU/opt-vgpr-live-range-verifier-error.mir
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.mir
M llvm/test/CodeGen/AMDGPU/optimize-ds-bvh-stack-pre-ra.ll
M llvm/test/CodeGen/AMDGPU/optimize-exec-copies-extra-insts-after-copy.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-alloc-failure.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-no-fold-exec-copy.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-masking-strip-terminator-bits.mir
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/or3.ll
M llvm/test/CodeGen/AMDGPU/overlapping-tuple-copy-implicit-op-failure.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
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M llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-bf16.ll
M llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/packed-op-sel.ll
M llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable-dvgpr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-dvgpr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx950.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.6-dvgpr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.6.ll
M llvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/pal-userdata-regs.ll
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M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/peephole-fold-imm-multi-use.mir
M llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
M llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir
M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
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M llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
M llvm/test/CodeGen/AMDGPU/perfhint.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permlane16_opsel.ll
M llvm/test/CodeGen/AMDGPU/permlane16_var-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/phi-av-pressure.ll
M llvm/test/CodeGen/AMDGPU/phi-elim-mli-available.mir
M llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
M llvm/test/CodeGen/AMDGPU/phys-partial-liveness.mir
M llvm/test/CodeGen/AMDGPU/pk-lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/pk_max_f16_literal.ll
M llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
M llvm/test/CodeGen/AMDGPU/post-ra-sched-reset.mir
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
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M llvm/test/CodeGen/AMDGPU/postra-bundle-vimage-vsample-gfx12.mir
M llvm/test/CodeGen/AMDGPU/postra-machine-sink-livein-subrange.mir
M llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir
M llvm/test/CodeGen/AMDGPU/postra-norename.mir
M llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
M llvm/test/CodeGen/AMDGPU/postra-sink-update-dependency.mir
M llvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir
M llvm/test/CodeGen/AMDGPU/pr51516.mir
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-IR-lowering.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs-IR-lowering.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
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M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/print-pipeline-passes.ll
M llvm/test/CodeGen/AMDGPU/printf-defined.ll
M llvm/test/CodeGen/AMDGPU/printf-existing-format-strings.ll
M llvm/test/CodeGen/AMDGPU/private-access-no-objects.ll
M llvm/test/CodeGen/AMDGPU/private-function.ll
M llvm/test/CodeGen/AMDGPU/prologue-epilogue-markers.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-allocation.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-bitcast-function.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-cfg.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-globals.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-invariant-markers.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-lifetime.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-loadstores.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-max-regs.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-mem-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-multidim.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-negative-index.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-non-byte-sizes.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-non-constant-index.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-placeholder-replacement.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-pointer-array.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-proper-value-replacement.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-scoring.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-strip-abi-opt-attributes.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-subvecs.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-constantexpr-use.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-icmp.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-phi.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-unhandled-intrinsic.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-use-after-erase.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-user-mult.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep-of-gep.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vgpr-ratio.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-volatile.ll
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M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx90a.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir
M llvm/test/CodeGen/AMDGPU/promote-vect3-load.ll
M llvm/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll
M llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
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M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag-mubuf.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag-undef-poison.ll
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M llvm/test/CodeGen/AMDGPU/ptrmask.ll
M llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-register.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll
M llvm/test/CodeGen/AMDGPU/read-write-register-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/read_register.ll
M llvm/test/CodeGen/AMDGPU/readcyclecounter.ll
M llvm/test/CodeGen/AMDGPU/readlane_exec0.mir
M llvm/test/CodeGen/AMDGPU/readsteadycounter.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll
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M llvm/test/CodeGen/AMDGPU/recursive-resource-usage-mcexpr.ll
M llvm/test/CodeGen/AMDGPU/recursive_global_initializer.ll
M llvm/test/CodeGen/AMDGPU/reduce-build-vec-ext-to-ext-build-vec.ll
M llvm/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll
M llvm/test/CodeGen/AMDGPU/reduction.ll
M llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll
M llvm/test/CodeGen/AMDGPU/reg-coalescer-subreg-liveness.mir
M llvm/test/CodeGen/AMDGPU/reg-sequence-like-v-pk-mov-b32.mir
M llvm/test/CodeGen/AMDGPU/regalloc-fail-unsatisfiable-overlapping-tuple-hints.mir
M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
M llvm/test/CodeGen/AMDGPU/regalloc-fast-dont-drop-subreg-index-issue61134.mir
M llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.mir
M llvm/test/CodeGen/AMDGPU/regalloc-illegal-eviction-assert.ll
M llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir
M llvm/test/CodeGen/AMDGPU/regalloc-sgpr128-partial-def.mir
M llvm/test/CodeGen/AMDGPU/regalloc-spill-wmma-scale.ll
M llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-64-bit-only-regs.mir
M llvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir
M llvm/test/CodeGen/AMDGPU/register-coalescer--set-undef-full-reg-use-implicit-def-erase-issue109249.mir
M llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
M llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll
M llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
M llvm/test/CodeGen/AMDGPU/reject-agpr-usage-before-gfx908.ll
M llvm/test/CodeGen/AMDGPU/rel32.ll
M llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir
M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12-dvgpr.mir
M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12.mir
M llvm/test/CodeGen/AMDGPU/release-vgprs-spill.ll
M llvm/test/CodeGen/AMDGPU/release-vgprs.mir
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
M llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll
M llvm/test/CodeGen/AMDGPU/remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir
M llvm/test/CodeGen/AMDGPU/remat-smrd.mir
M llvm/test/CodeGen/AMDGPU/remat-sop.mir
M llvm/test/CodeGen/AMDGPU/remat-through-copy.mir
M llvm/test/CodeGen/AMDGPU/remat-vop.mir
M llvm/test/CodeGen/AMDGPU/remove-incompatible-extended-image-insts.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-functions.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-gws.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-s-time.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave32-feature.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave64-feature.ll
M llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
M llvm/test/CodeGen/AMDGPU/remove-not-short-exec-branch-on-unconditional-jump.mir
M llvm/test/CodeGen/AMDGPU/remove-register-flags.mir
M llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-gpr-idx-mode.mir
M llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-special-instructions.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-unused-lanes.ll
M llvm/test/CodeGen/AMDGPU/reorder-stores.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/replace-store-of-insert-load.ll
M llvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/required-export-priority.ll
M llvm/test/CodeGen/AMDGPU/required-export-priority.mir
M llvm/test/CodeGen/AMDGPU/reserved-reg-in-clause.mir
M llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
M llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir
M llvm/test/CodeGen/AMDGPU/resource-usage-dead-function.ll
M llvm/test/CodeGen/AMDGPU/resource-usage-pal.ll
M llvm/test/CodeGen/AMDGPU/ret.ll
M llvm/test/CodeGen/AMDGPU/ret_jump.ll
M llvm/test/CodeGen/AMDGPU/return-with-successors.mir
M llvm/test/CodeGen/AMDGPU/returnaddress.ll
M llvm/test/CodeGen/AMDGPU/rewrite-mfma-form-spill-cost-reset.ll
M llvm/test/CodeGen/AMDGPU/rewrite-out-arguments-address-space.ll
M llvm/test/CodeGen/AMDGPU/rewrite-out-arguments.ll
M llvm/test/CodeGen/AMDGPU/rewrite-undef-for-phi.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-scale-to-agpr.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store-mir.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
M llvm/test/CodeGen/AMDGPU/rotate-add.ll
M llvm/test/CodeGen/AMDGPU/rotl.i64.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.i64.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32-safe.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-id-allocation.ll
M llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-buffer-load-mmo-offsets.ll
M llvm/test/CodeGen/AMDGPU/s-cluster-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir
M llvm/test/CodeGen/AMDGPU/s_addk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_cmp_0.ll
M llvm/test/CodeGen/AMDGPU/s_code_end.ll
M llvm/test/CodeGen/AMDGPU/s_movk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_or_b32_transformation.ll
M llvm/test/CodeGen/AMDGPU/s_or_saveexec_xor_combine.mir
M llvm/test/CodeGen/AMDGPU/s_uaddo_usubo_pseudo.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/saddsat.ll
M llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
M llvm/test/CodeGen/AMDGPU/same-lds-variable-multiple-use-in-one-phi-node.ll
M llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir
M llvm/test/CodeGen/AMDGPU/save-fp.ll
M llvm/test/CodeGen/AMDGPU/scalar-branch-missing-and-exec.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
M llvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll
M llvm/test/CodeGen/AMDGPU/scalarize-insert-subvector.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-scratch.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-post-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-pre-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-dead-def-join.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/sched-image-sample-post-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-ldsdma-mask.mir
M llvm/test/CodeGen/AMDGPU/sched-no-schedmodel.mir
M llvm/test/CodeGen/AMDGPU/sched-prefer-non-mfma.mir
M llvm/test/CodeGen/AMDGPU/sched-setprio.ll
M llvm/test/CodeGen/AMDGPU/sched.group.classification.mir
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_diff_types.mir
M llvm/test/CodeGen/AMDGPU/schedmodel-dummywrite.mir
M llvm/test/CodeGen/AMDGPU/schedule-addrspaces.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg-crash.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/schedule-avoid-spills.ll
M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier-latency.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
M llvm/test/CodeGen/AMDGPU/schedule-ilp-liveness-tracking.mir
M llvm/test/CodeGen/AMDGPU/schedule-ilp.ll
M llvm/test/CodeGen/AMDGPU/schedule-ilp.mir
M llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll
M llvm/test/CodeGen/AMDGPU/schedule-pending-queue.mir
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-lds.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit-clustering.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit2.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit3.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-misched-max-waves.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-no-unclustered-regions.mir
M llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll
M llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll
M llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll
M llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
M llvm/test/CodeGen/AMDGPU/scheduler-rp-calc-one-successor-two-predecessors-bug.ll
M llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll
M llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
M llvm/test/CodeGen/AMDGPU/scratch-pointer-sink.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdivrem24.ll
M llvm/test/CodeGen/AMDGPU/sdwa-commute.ll
M llvm/test/CodeGen/AMDGPU/sdwa-cse.mir
M llvm/test/CodeGen/AMDGPU/sdwa-gfx9.mir
M llvm/test/CodeGen/AMDGPU/sdwa-op64-test.ll
M llvm/test/CodeGen/AMDGPU/sdwa-ops.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-fail.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-sext.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-wave32.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-wave64.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel-dst.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel-src.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
M llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir
M llvm/test/CodeGen/AMDGPU/sdwa-stack.mir
M llvm/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir
M llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-fp.ll
M llvm/test/CodeGen/AMDGPU/select-cmp-shared-constant-int.ll
M llvm/test/CodeGen/AMDGPU/select-constant-xor.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract-legacy.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.legal.f16.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/select-i1.ll
M llvm/test/CodeGen/AMDGPU/select-load-to-load-select-ptr-combine.ll
M llvm/test/CodeGen/AMDGPU/select-nsz-known-values-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll
M llvm/test/CodeGen/AMDGPU/select-undef.ll
M llvm/test/CodeGen/AMDGPU/select-vectors.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/select64.ll
M llvm/test/CodeGen/AMDGPU/selectcc-opt.ll
M llvm/test/CodeGen/AMDGPU/selectcc.ll
M llvm/test/CodeGen/AMDGPU/sema-v-unsched-bundle.ll
M llvm/test/CodeGen/AMDGPU/sendmsg-m0-hazard.mir
M llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/AMDGPU/set_kill_i1_for_floation_point_comparison.ll
M llvm/test/CodeGen/AMDGPU/setcc-f64-hi32mask.ll
M llvm/test/CodeGen/AMDGPU/setcc-fneg-constant.ll
M llvm/test/CodeGen/AMDGPU/setcc-limit-load-shrink.ll
M llvm/test/CodeGen/AMDGPU/setcc-multiple-use.ll
M llvm/test/CodeGen/AMDGPU/setcc-opt.ll
M llvm/test/CodeGen/AMDGPU/setcc64.ll
M llvm/test/CodeGen/AMDGPU/seto.ll
M llvm/test/CodeGen/AMDGPU/setuo.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/sgpr-count-graphics.ll
M llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
M llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-incorrect-fi-bookkeeping-bug.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spills-empty-prolog-block.mir
M llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.ll
M llvm/test/CodeGen/AMDGPU/shader-addr64-nonuniform.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll
M llvm/test/CodeGen/AMDGPU/shift-select.ll
M llvm/test/CodeGen/AMDGPU/shl-add-to-add-shl.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shl64_reduce.ll
M llvm/test/CodeGen/AMDGPU/shl64_reduce_flags.ll
M llvm/test/CodeGen/AMDGPU/shlN_add.ll
M llvm/test/CodeGen/AMDGPU/shl_add.ll
M llvm/test/CodeGen/AMDGPU/shl_add_constant.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr_csub.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr_global.ll
M llvm/test/CodeGen/AMDGPU/shl_or.ll
M llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/shrink-carry.mir
M llvm/test/CodeGen/AMDGPU/shrink-fma-f64.mir
M llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir
M llvm/test/CodeGen/AMDGPU/shrink-instructions-implicit-vcclo.mir
M llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
M llvm/test/CodeGen/AMDGPU/shrink-mad-fma-fake16.mir
M llvm/test/CodeGen/AMDGPU/shrink-mad-fma-gfx10.mir
M llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir
M llvm/test/CodeGen/AMDGPU/shrink-true16.mir
M llvm/test/CodeGen/AMDGPU/shrink-v-cmp-wave32-dead-vcc-lo.mir
M llvm/test/CodeGen/AMDGPU/shufflevector-physreg-copy.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v3i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v4i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v3i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v4i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v3i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v4i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-kill.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-nested-control-flows.ll
M llvm/test/CodeGen/AMDGPU/si-annotatecfg-multiple-backedges.ll
M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies-av-constrain.mir
M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies-copy-to-sgpr.mir
M llvm/test/CodeGen/AMDGPU/si-fold-aligned-agprs.mir
M llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/si-fold-copy-kills.mir
M llvm/test/CodeGen/AMDGPU/si-fold-kimm.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-bundle.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-commute-same-operands-assert.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-gfx11.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-requires-ssa.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.gfx942.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.mir
M llvm/test/CodeGen/AMDGPU/si-fold-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/si-fold-scalar-add-sub-imm.mir
M llvm/test/CodeGen/AMDGPU/si-fold-scalar-clamp.mir
M llvm/test/CodeGen/AMDGPU/si-init-whole-wave.mir
M llvm/test/CodeGen/AMDGPU/si-insert-hard-clauses-no-nesting.mir
M llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
M llvm/test/CodeGen/AMDGPU/si-instr-info-vopc-exec.mir
M llvm/test/CodeGen/AMDGPU/si-late-branch-lowering-preserve-loop-info.mir
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-preserve-dom-tree.mir
M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies-order-of-phi-incomings.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.ll
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
M llvm/test/CodeGen/AMDGPU/si-lower-wwm-copies.mir
M llvm/test/CodeGen/AMDGPU/si-opt-vgpr-liverange-bug-deadlanes.mir
M llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.ll
M llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.mir
M llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
M llvm/test/CodeGen/AMDGPU/si-pre-emit-peephole-preserve-loop-info.mir
M llvm/test/CodeGen/AMDGPU/si-scheduler-exports.ll
M llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir
M llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir
M llvm/test/CodeGen/AMDGPU/spillv16.mir
M llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir
A llvm/test/CodeGen/ARM/thumb1-copy-physreg-dbg-value-crash.ll
M llvm/test/CodeGen/Hexagon/autohvx/conv-fp-fp.ll
M llvm/test/CodeGen/Hexagon/fminmax-v67.ll
M llvm/test/CodeGen/Hexagon/fminmax.ll
M llvm/test/CodeGen/Mips/divrem.ll
M llvm/test/CodeGen/RISCV/clmul.ll
A llvm/test/CodeGen/RISCV/xqcilo-xqcilia-frame-index.ll
M llvm/test/CodeGen/SPIRV/vk-pushconstant-layout.ll
M llvm/test/CodeGen/SystemZ/vec-max-05.ll
M llvm/test/CodeGen/SystemZ/vec-max-min-zerosplat.ll
M llvm/test/CodeGen/SystemZ/vec-min-05.ll
A llvm/test/CodeGen/SystemZ/vec-strict-pseudo-max.ll
A llvm/test/CodeGen/SystemZ/vec-strict-pseudo-min.ll
M llvm/test/CodeGen/SystemZ/zos-ppa2.ll
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
M llvm/test/CodeGen/X86/bitcnt-false-dep.ll
M llvm/test/CodeGen/X86/bitcnt-load-with-cmov.ll
M llvm/test/CodeGen/X86/bitreverse.ll
A llvm/test/CodeGen/X86/bls-false-dep.ll
M llvm/test/CodeGen/X86/clmul.ll
A llvm/test/CodeGen/X86/compress-false-deps.ll
A llvm/test/CodeGen/X86/expand-false-deps.ll
R llvm/test/CodeGen/X86/pr142937.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt-i64.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt-i64.ll
A llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt.ll
M llvm/test/CodeGen/X86/slow-unaligned-mem.ll
A llvm/test/CodeGen/X86/type-tests-must-be-lowered.ll
M llvm/test/CodeGen/X86/udiv_fix.ll
M llvm/test/CodeGen/X86/udiv_fix_sat.ll
M llvm/test/CodeGen/X86/win64-eh-unwindv3-split-large.ll
M llvm/test/CodeGen/X86/x86-prefer-no-gather-no-scatter.ll
A llvm/test/MC/AMDGPU/amdgcn-target-directive-conflict.s
M llvm/test/MC/AMDGPU/amdgcn-target-directive-subarch-cpu-field.s
M llvm/test/MC/AMDGPU/amdgcn-target-directive-triple-env.s
M llvm/test/MC/AMDGPU/hsa-diag-v4.s
M llvm/test/MC/AMDGPU/hsa-exp.s
M llvm/test/MC/AMDGPU/hsa-gfx12-v4.s
M llvm/test/MC/AMDGPU/hsa-gfx13-v4.s
M llvm/test/MC/AMDGPU/hsa-tg-split.s
M llvm/test/MC/AMDGPU/hsa-v4.s
M llvm/test/MC/AMDGPU/hsa-v5-uses-dynamic-stack.s
M llvm/test/MC/AMDGPU/isa-version-hsa.s
M llvm/test/MC/AMDGPU/isa-version-pal.s
M llvm/test/MC/AMDGPU/isa-version-unk.s
M llvm/test/MC/ELF/AMDGPU/cfi.s
A llvm/test/Object/X86/irsymtab-large-common.ll
M llvm/test/Object/X86/irsymtab.ll
M llvm/test/Transforms/ConstraintElimination/induction-condition-in-loop-exit.ll
M llvm/test/Transforms/ConstraintElimination/loops-header-tested-pointer-cmps.ll
A llvm/test/Transforms/Inline/X86/always-inline-incompatible-target-features.ll
M llvm/test/Transforms/Inline/always-inline-phase-ordering.ll
M llvm/test/Transforms/Inline/byval.ll
M llvm/test/Transforms/InstCombine/known-bits.ll
A llvm/test/Transforms/InstCombine/shuffle-cmp-cast-preserve-flags.ll
A llvm/test/Transforms/InstCombine/udiv-isknownnegative.ll
M llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll
M llvm/test/Transforms/LoopVectorize/AArch64/alias-mask-uniforms.ll
M llvm/test/Transforms/LoopVectorize/AArch64/alias-mask.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-incomplete-chains.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/pr41179.ll
M llvm/test/Transforms/LoopVectorize/RISCV/early-exit-live-out.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-prune-vf.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-access-wide-stride.ll
A llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-unroll.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
M llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing-alias-mask.ll
M llvm/test/Transforms/LoopVectorize/VPlan/RISCV/expand-scev.ll
M llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-alias-mask.ll
M llvm/test/Transforms/LoopVectorize/WebAssembly/induction-branch-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/fold-tail-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-opaque-pointers.ll
M llvm/test/Transforms/LoopVectorize/X86/optsize.ll
M llvm/test/Transforms/LoopVectorize/X86/pr48340.ll
M llvm/test/Transforms/LoopVectorize/X86/pr72969.ll
M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
A llvm/test/Transforms/LoopVectorize/X86/x86-prefer-no-gather.ll
A llvm/test/Transforms/LoopVectorize/X86/x86-prefer-no-scatter.ll
M llvm/test/Transforms/LoopVectorize/alias-mask-data-tail-folding-style.ll
M llvm/test/Transforms/LoopVectorize/alias-mask-needs-freeze.ll
M llvm/test/Transforms/LoopVectorize/alias-mask-small-index.ll
M llvm/test/Transforms/LoopVectorize/alias-mask.ll
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/hoist-and-sink-mem-ops-with-invariant-pointers.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-different-insert-position.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
M llvm/test/Transforms/LoopVectorize/metadata.ll
M llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/pr45259.ll
M llvm/test/Transforms/LoopVectorize/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll
M llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/non-power-of-2-with-adjusted-gathers.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-abs.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-saddo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-ssat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-uaddo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-usat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-div.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fix.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-mul-smulo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-mul-umulo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-mul.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-scmp.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-smax.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-smin.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-ssat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-ssubo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-usat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-usubo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-ucmp.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-umax.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-umin.ll
M llvm/test/Transforms/SLPVectorizer/X86/control-deps-schedule-data-recalculate.ll
A llvm/test/Transforms/SLPVectorizer/X86/crash_scatter_load_reorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/fabs.ll
M llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll
M llvm/test/Transforms/SLPVectorizer/X86/fma.ll
M llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
M llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
M llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
M llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
M llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
M llvm/test/Transforms/SLPVectorizer/X86/fround.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-root-multiuse-same-opcode.ll
M llvm/test/Transforms/SLPVectorizer/X86/shift-ashr.ll
M llvm/test/Transforms/SLPVectorizer/X86/shift-lshr.ll
M llvm/test/Transforms/SLPVectorizer/X86/shift-shl.ll
M llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
M llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
A llvm/test/Transforms/SLPVectorizer/X86/x86-prefer-no-gather.ll
R llvm/test/Transforms/SampleProfile/icp_target_feature.ll
A llvm/test/Verifier/amdgpu-expected-active-lanes.ll
A llvm/test/tools/llvm-ar/zos-write.test
A llvm/test/tools/llvm-reduce/reduce-instructions-x86-amx.ll
A llvm/test/tools/llvm-reduce/reduce-operands-to-args-x86-amx.ll
A llvm/test/tools/llvm-reduce/reduce-operands-x86-amx.ll
M llvm/tools/llvm-ar/llvm-ar.cpp
M llvm/tools/llvm-mc/Disassembler.cpp
M llvm/tools/llvm-mc/Disassembler.h
M llvm/tools/llvm-mc/llvm-mc.cpp
M llvm/tools/llvm-reduce/deltas/ReduceInstructions.cpp
M llvm/tools/llvm-reduce/deltas/ReduceOperands.cpp
M llvm/tools/llvm-reduce/deltas/ReduceOperandsToArgs.cpp
M llvm/unittests/ADT/ImmutableSetTest.cpp
M llvm/unittests/CodeGen/RematerializerTest.cpp
M llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/utils/gn/secondary/clang-tools-extra/clang-doc/BUILD.gn
R llvm/utils/gn/secondary/clang-tools-extra/clang-doc/markdown/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/unittests/clang-doc/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysis/Analyses/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/ScalableStaticAnalysis/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Passes/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn
M llvm/utils/gn/secondary/llvm/version.gni
M llvm/utils/lit/lit/LitConfig.py
M llvm/utils/lit/lit/__init__.py
M llvm/utils/lit/lit/builtin_commands/cat.py
M llvm/utils/lit/lit/cl_arguments.py
M llvm/utils/lit/lit/main.py
M llvm/utils/lit/lit/util.py
A llvm/utils/lit/tests/Inputs/time-tests/b.txt
A llvm/utils/lit/tests/Inputs/time-tests/c.txt
M llvm/utils/lit/tests/time-tests.py
A llvm/utils/lit/tests/unit/LitConfig.py
M llvm/utils/mlgo-utils/mlgo/__init__.py
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPUOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
M mlir/include/mlir/TableGen/Format.h
M mlir/include/mlir/Target/LLVMIR/Dialect/All.h
R mlir/include/mlir/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.h
M mlir/lib/Conversion/EmitCCommon/TypeConverter.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/lib/Conversion/NVGPUToNVVM/CMakeLists.txt
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/NVGPU/IR/NVGPUDialect.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCRecipeMaterialization.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/lib/Target/LLVMIR/CMakeLists.txt
M mlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp
R mlir/lib/Target/LLVMIR/Dialect/OpenACC/CMakeLists.txt
R mlir/lib/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Conversion/FuncToEmitC/func-to-emitc-failed.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-dealloc.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-load-store.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-copy.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-failed.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc.mlir
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-extf-large.mlir
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-extf.mlir
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-truncf-large.mlir
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-truncf.mlir
M mlir/test/Dialect/LLVMIR/nvvm.mlir
A mlir/test/Dialect/NVGPU/nvgpu-extf-invalid.mlir
A mlir/test/Dialect/NVGPU/nvgpu-truncf-invalid.mlir
M mlir/test/Dialect/OpenACC/acc-recipe-materialization-reduction.mlir
M mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
M mlir/test/Dialect/XeGPU/propagate-layout.mlir
M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F4.mlir
M mlir/test/Target/LLVMIR/Import/function-attributes.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
M mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-host.mlir
R mlir/test/Target/LLVMIR/openacc-llvm.mlir
M mlir/utils/generate-test-checks.py
M offload/plugins-nextgen/common/src/RecordReplay.cpp
M offload/test/offloading/fortran/declare-target-automap.f90
M openmp/runtime/src/kmp_utility.cpp
M orc-rt/include/orc-rt-c/Logging.h
M orc-rt/include/orc-rt/AllocAction.h
M orc-rt/include/orc-rt/Compiler.h
R orc-rt/lib/executor/AllocAction.cpp
M orc-rt/lib/executor/CMakeLists.txt
M orc-rt/lib/executor/Logging.cpp
M orc-rt/lib/executor/SimpleNativeMemoryMap.cpp
M orc-rt/test/regression/logging/os_log/delivery.test
M orc-rt/test/tools/orc-rt-log-check.cpp
M orc-rt/test/unit/AllocActionTest.cpp
M orc-rt/test/unit/CMakeLists.txt
M orc-rt/test/unit/CommonTestUtils.h
A orc-rt/test/unit/CompilerTest.cpp
M orc-rt/test/unit/ErrorTest.cpp
M orc-rt/test/unit/LoggingTest.cpp
M polly/lib/Support/RegisterPasses.cpp
M utils/bazel/llvm-project-overlay/clang-tools-extra/clang-doc/BUILD.bazel
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/Support/BUILD.bazel
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/Transforms/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/ziqingluo/PR-179151882
Compare: https://github.com/llvm/llvm-project/compare/486a7ad427b2...ae21f63afa4a
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