[all-commits] [llvm/llvm-project] 21bc62: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Tue Jul 14 12:16:57 PDT 2026 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 21bc62e6688a5dcaf79ebd992e5e4676b287a674
      https://github.com/llvm/llvm-project/commit/21bc62e6688a5dcaf79ebd992e5e4676b287a674
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-14 (Tue, 14 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v2i64.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v3i64.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v4i64.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v2p0.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v3p0.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v4p0.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v2p3.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v3p3.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v4p3.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v3bf16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v4bf16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v3f16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v4f16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v2f32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v3f32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v4f32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v3i16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v4i16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v2i32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v3i32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v4i32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v2i64.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v3i64.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v4i64.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v2p0.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v3p0.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v4p0.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v2p3.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v3p3.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v4p3.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v2bf16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v3bf16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v4bf16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v2f16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v3f16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v4f16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v2f32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v3f32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v4f32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v3i16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v4i16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v2i32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v3i32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v4i32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v2i64.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v3i64.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v2p0.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v2p3.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v3p3.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v4p3.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cf-kill.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-dbg-info.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-nested-control-flows.ll
    M llvm/test/CodeGen/AMDGPU/si-annotatecfg-multiple-backedges.ll
    M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies-av-constrain.mir
    M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies-copy-to-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-aligned-agprs.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-copy-kills.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-kimm.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-operands-bundle.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-operands-commute-same-operands-assert.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-operands-gfx11.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-operands-requires-ssa.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.gfx942.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-reg-sequence.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-scalar-add-sub-imm.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-scalar-clamp.mir
    M llvm/test/CodeGen/AMDGPU/si-init-whole-wave.mir
    M llvm/test/CodeGen/AMDGPU/si-insert-hard-clauses-no-nesting.mir
    M llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
    M llvm/test/CodeGen/AMDGPU/si-instr-info-vopc-exec.mir
    M llvm/test/CodeGen/AMDGPU/si-late-branch-lowering-preserve-loop-info.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-preserve-dom-tree.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies-order-of-phi-incomings.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.ll
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-wwm-copies.mir
    M llvm/test/CodeGen/AMDGPU/si-opt-vgpr-liverange-bug-deadlanes.mir
    M llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.ll
    M llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.mir
    M llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
    M llvm/test/CodeGen/AMDGPU/si-pre-emit-peephole-preserve-loop-info.mir
    M llvm/test/CodeGen/AMDGPU/si-scheduler-exports.ll

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (32) (#209561)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



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