[all-commits] [llvm/llvm-project] e0b470: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Tue Jul 14 12:14:52 PDT 2026 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e0b4701f2621d2542405830008797e3cf319a3f0
      https://github.com/llvm/llvm-project/commit/e0b4701f2621d2542405830008797e3cf319a3f0
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-14 (Tue, 14 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/select-i1.ll
    M llvm/test/CodeGen/AMDGPU/select-load-to-load-select-ptr-combine.ll
    M llvm/test/CodeGen/AMDGPU/select-nsz-known-values-to-fmin-fmax.ll
    M llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll
    M llvm/test/CodeGen/AMDGPU/select-undef.ll
    M llvm/test/CodeGen/AMDGPU/select-vectors.ll
    M llvm/test/CodeGen/AMDGPU/select.f16.ll
    M llvm/test/CodeGen/AMDGPU/select64.ll
    M llvm/test/CodeGen/AMDGPU/selectcc-opt.ll
    M llvm/test/CodeGen/AMDGPU/selectcc.ll
    M llvm/test/CodeGen/AMDGPU/sema-v-unsched-bundle.ll
    M llvm/test/CodeGen/AMDGPU/sendmsg-m0-hazard.mir
    M llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
    M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
    M llvm/test/CodeGen/AMDGPU/set_kill_i1_for_floation_point_comparison.ll
    M llvm/test/CodeGen/AMDGPU/setcc-f64-hi32mask.ll
    M llvm/test/CodeGen/AMDGPU/setcc-fneg-constant.ll
    M llvm/test/CodeGen/AMDGPU/setcc-limit-load-shrink.ll
    M llvm/test/CodeGen/AMDGPU/setcc-multiple-use.ll
    M llvm/test/CodeGen/AMDGPU/setcc-opt.ll
    M llvm/test/CodeGen/AMDGPU/setcc64.ll
    M llvm/test/CodeGen/AMDGPU/seto.ll
    M llvm/test/CodeGen/AMDGPU/setuo.ll
    M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
    M llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
    M llvm/test/CodeGen/AMDGPU/sext-in-reg.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-copy.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-count-graphics.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-incorrect-fi-bookkeeping-bug.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spills-empty-prolog-block.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.ll
    M llvm/test/CodeGen/AMDGPU/shader-addr64-nonuniform.ll
    M llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
    M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
    M llvm/test/CodeGen/AMDGPU/shift-i128.ll
    M llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll
    M llvm/test/CodeGen/AMDGPU/shift-select.ll
    M llvm/test/CodeGen/AMDGPU/shl-add-to-add-shl.ll
    M llvm/test/CodeGen/AMDGPU/shl.ll
    M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
    M llvm/test/CodeGen/AMDGPU/shl64_reduce.ll
    M llvm/test/CodeGen/AMDGPU/shl64_reduce_flags.ll
    M llvm/test/CodeGen/AMDGPU/shlN_add.ll
    M llvm/test/CodeGen/AMDGPU/shl_add.ll
    M llvm/test/CodeGen/AMDGPU/shl_add_constant.ll
    M llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
    M llvm/test/CodeGen/AMDGPU/shl_add_ptr_csub.ll
    M llvm/test/CodeGen/AMDGPU/shl_add_ptr_global.ll
    M llvm/test/CodeGen/AMDGPU/shl_or.ll
    M llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
    M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
    M llvm/test/CodeGen/AMDGPU/shrink-carry.mir
    M llvm/test/CodeGen/AMDGPU/shrink-fma-f64.mir
    M llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir
    M llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir
    M llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir
    M llvm/test/CodeGen/AMDGPU/shrink-instructions-implicit-vcclo.mir
    M llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
    M llvm/test/CodeGen/AMDGPU/shrink-mad-fma-fake16.mir
    M llvm/test/CodeGen/AMDGPU/shrink-mad-fma-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir
    M llvm/test/CodeGen/AMDGPU/shrink-true16.mir
    M llvm/test/CodeGen/AMDGPU/shrink-v-cmp-wave32-dead-vcc-lo.mir
    M llvm/test/CodeGen/AMDGPU/shufflevector-physreg-copy.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v2bf16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v3bf16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v4bf16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v2f16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v3f16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v4f16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v2f32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v3f32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v3i16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v4i16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v2i32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v3i32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (31) (#209560)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications

More information about the All-commits mailing list