[all-commits] [llvm/llvm-project] 666b87: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Tue Jul 14 11:04:04 PDT 2026 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 666b87dd01d31cc80f356315c1c2d03974759138
      https://github.com/llvm/llvm-project/commit/666b87dd01d31cc80f356315c1c2d03974759138
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-14 (Tue, 14 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
    M llvm/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll
    M llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir
    M llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
    M llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
    M llvm/test/CodeGen/AMDGPU/nofpclass-call.ll
    M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
    M llvm/test/CodeGen/AMDGPU/noop-shader-O0.ll
    M llvm/test/CodeGen/AMDGPU/nop-data.ll
    M llvm/test/CodeGen/AMDGPU/nor-divergent-lanemask.ll
    M llvm/test/CodeGen/AMDGPU/nor.ll
    M llvm/test/CodeGen/AMDGPU/nsa-reassign.ll
    M llvm/test/CodeGen/AMDGPU/nsa-reassign.mir
    M llvm/test/CodeGen/AMDGPU/nsa-vmem-hazard.mir
    M llvm/test/CodeGen/AMDGPU/object-linking-local-resources.ll
    M llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
    M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
    M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
    M llvm/test/CodeGen/AMDGPU/omod.ll
    M llvm/test/CodeGen/AMDGPU/opencl-printf-and-hostcall.ll
    M llvm/test/CodeGen/AMDGPU/opencl-printf-pipeline.ll
    M llvm/test/CodeGen/AMDGPU/opencl-printf-unsupported.ll
    M llvm/test/CodeGen/AMDGPU/opencl-printf.ll
    M llvm/test/CodeGen/AMDGPU/operand-folding.ll
    M llvm/test/CodeGen/AMDGPU/operand-spacing.ll
    M llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness-wave32.mir
    M llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness.mir
    M llvm/test/CodeGen/AMDGPU/opt-vgpr-live-range-verifier-error.mir
    M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
    M llvm/test/CodeGen/AMDGPU/optimize-compare.mir
    M llvm/test/CodeGen/AMDGPU/optimize-ds-bvh-stack-pre-ra.ll
    M llvm/test/CodeGen/AMDGPU/optimize-exec-copies-extra-insts-after-copy.mir
    M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-alloc-failure.mir
    M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir
    M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-no-fold-exec-copy.mir
    M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir
    M llvm/test/CodeGen/AMDGPU/optimize-exec-masking-strip-terminator-bits.mir
    M llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
    M llvm/test/CodeGen/AMDGPU/or.ll
    M llvm/test/CodeGen/AMDGPU/or3.ll
    M llvm/test/CodeGen/AMDGPU/overlapping-tuple-copy-implicit-op-failure.ll
    M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
    M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/packed-dependencies.mir
    M llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-bf16.ll
    M llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll
    M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
    M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
    M llvm/test/CodeGen/AMDGPU/packed-op-sel.ll
    M llvm/test/CodeGen/AMDGPU/packed-u64.ll
    M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable-dvgpr.ll
    M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll
    M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-dvgpr.ll
    M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx1250.ll
    M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx950.ll
    M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll
    M llvm/test/CodeGen/AMDGPU/pal-metadata-3.6-dvgpr.ll
    M llvm/test/CodeGen/AMDGPU/pal-metadata-3.6.ll
    M llvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/pal-userdata-regs.ll
    M llvm/test/CodeGen/AMDGPU/partial-forwarding-hazards.mir
    M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
    M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
    M llvm/test/CodeGen/AMDGPU/peephole-fold-imm-multi-use.mir
    M llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
    M llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir
    M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
    M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
    M llvm/test/CodeGen/AMDGPU/perfhint.ll
    M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
    M llvm/test/CodeGen/AMDGPU/permlane16_opsel.ll
    M llvm/test/CodeGen/AMDGPU/permlane16_var-op-sel.ll
    M llvm/test/CodeGen/AMDGPU/permute.ll
    M llvm/test/CodeGen/AMDGPU/permute_i8.ll
    M llvm/test/CodeGen/AMDGPU/phi-av-pressure.ll
    M llvm/test/CodeGen/AMDGPU/phi-elim-mli-available.mir
    M llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
    M llvm/test/CodeGen/AMDGPU/phys-partial-liveness.mir
    M llvm/test/CodeGen/AMDGPU/pk-lshl-add-u64.ll
    M llvm/test/CodeGen/AMDGPU/pk_max_f16_literal.ll
    M llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
    M llvm/test/CodeGen/AMDGPU/post-ra-sched-reset.mir
    M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
    M llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
    M llvm/test/CodeGen/AMDGPU/postra-bundle-vimage-vsample-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/postra-machine-sink-livein-subrange.mir
    M llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir
    M llvm/test/CodeGen/AMDGPU/postra-norename.mir
    M llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll
    M llvm/test/CodeGen/AMDGPU/postra-sink-update-dependency.mir

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (27) (#209488)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



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