[all-commits] [llvm/llvm-project] b9998b: [AMDGPU] Fix CFI emission when scratch instruction...

[Lancelot Six via All-commits]

  Branch: refs/heads/users/slinder1/I837bb34bf19bf2e53ba37706678c8ac506d2732f
  Home:   https://github.com/llvm/llvm-project
  Commit: b9998b83bcbdc91fea091c6312683bca70b985ba
      https://github.com/llvm/llvm-project/commit/b9998b83bcbdc91fea091c6312683bca70b985ba
  Author: Lancelot SIX <lancelot.six at amd.com>
  Date:   2026-07-14 (Tue, 14 Jul 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir
    M llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir
    M llvm/test/CodeGen/AMDGPU/spillv16.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir

  Log Message:
  -----------
  [AMDGPU] Fix CFI emission when scratch instructions are used to spill

4b1cfc5d7c606e "[NFCI][AMDGPU] Final touch before moving to
`GET_SUBTARGETINFO_MACRO` (#177401)" (or more generally the move to
hasFlatScratchEnabled over just enableFlatScratch) was missed during the
CFI upstreaming for AMDGPU, and so we currently define the CFA
incorrectly for the architected flat scratch case.

This incorrect CFI is generated for e.g. gfx942. For such architecture,
the stack pointer (s32) holds a swizzled address (per-lane offset) but
the CFA needs to be an unswizzled address (per-wave).

In the incorrect program, we have a prologue looking like:

        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
        s_mov_b32 s0, s33
        s_mov_b32 s33, s32
        [...]
        s_add_i32 s32, s32, 16
        [...]

(16 is a per-lane offset) but CFA ends up being defined as

    DW_CFA_LLVM_def_aspace_cfa: SGPR32 +0 in addrspace6

with addrspace6 being DW_ASPACE_AMDGPU_private_wave.  The correct CFA
should instead be:

    DW_CFA_def_cfa_expression: DW_OP_regx SGPR32, DW_OP_deref_size 0x4, DW_OP_lit6, DW_OP_shl, DW_OP_lit6, DW_OP_LLVM_user DW_OP_LLVM_form_aspace_address

which converts from swizzled to unswizzled.

Deciding which form to use is done in SIFrameLowering::emitDefCFA which
still uses the old ST.enableFlatScratch() instead of
ST.hasFlatScratchEnabled().  This patch fixes this as well as the other
user of enableFlatScratch in createScaledCFAInPrivateWave.

The naming for the "enable-flat-scratch" feature seems unfortunate in
retrospect, although I'm not sure we can change it easily at this point?

CFI generation tested for gfx942 and gfx1031 with ROCgdb's testsuite.

Change-Id: I837bb34bf19bf2e53ba37706678c8ac506d2732f



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