[all-commits] [llvm/llvm-project] d45452: [AArch64] Tighten conditions for expanding GET_ACT...

[Usman Nadeem via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d454522b4140d7baa9d1be5d0ce2da327104c0d1
      https://github.com/llvm/llvm-project/commit/d454522b4140d7baa9d1be5d0ce2da327104c0d1
  Author: Usman Nadeem <mnadeem at qti.qualcomm.com>
  Date:   2026-07-14 (Tue, 14 Jul 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
    M llvm/test/CodeGen/AArch64/active_lane_mask.ll
    M llvm/test/CodeGen/AArch64/sve-mask-partition.ll

  Log Message:
  -----------
  [AArch64] Tighten conditions for expanding GET_ACTIVE_LANE_MASK (#208962)

Lower to whilelo in more cases.

For fixed-width even if the operands are <32 bits, expanding is going to
be more expensive compared to promoting the operands from a smaller
type.

For SVE I also added lowering for nxv1i1 type as: `nxv2i1 -> extract
nxv1i1.`



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