[all-commits] [llvm/llvm-project] 194f7a: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

Tue Jul 14 10:03:02 PDT 2026

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 194f7a360c475fd7da253248a6aade878b52318c
      https://github.com/llvm/llvm-project/commit/194f7a360c475fd7da253248a6aade878b52318c
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-14 (Tue, 14 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-014bb.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-cfg-with-self-loop.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-phi-merge-distances.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-acyclic-cfg-with-4-self-loops.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-11blocks.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-15blocks.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop-a.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/if_else_with_loops_nested_in_2_outer_loops.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/inner_cfg_in_2_nested_loops.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/loop_nested_in_3_outer_loops_complex_cfg.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/nested-loops-with-side-exits-a.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/sequence_2_loops.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/simple-loop-3blocks.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_basic_case.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_do_not_spill_restore_inside_loop.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_common_dominator.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader1.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader2.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader3.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader4.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_keep_spilled_reg_live.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_nested_loops.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_in_common_dominator_and_optimize_restores.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_livethrough_reg.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_value_in_exit_block.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/three-tier-ranking-nested-loops.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/triple-nested-loops.mir
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/two-sequential-loops.mir
    M llvm/test/CodeGen/AMDGPU/minmax.ll
    M llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
    M llvm/test/CodeGen/AMDGPU/mir-dynamic-vgpr-block-size-roundtrip.mir
    M llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir
    M llvm/test/CodeGen/AMDGPU/misched-into-wmma-hazard-shadow.mir
    M llvm/test/CodeGen/AMDGPU/misched-killflags.mir
    M llvm/test/CodeGen/AMDGPU/missing-store.ll
    M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
    M llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll
    M llvm/test/CodeGen/AMDGPU/mixed_wave32_wave64.ll
    M llvm/test/CodeGen/AMDGPU/mmo-target-flags-folding.ll
    M llvm/test/CodeGen/AMDGPU/mmra.ll
    M llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
    M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
    M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus.mir
    M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.mir
    M llvm/test/CodeGen/AMDGPU/mode-register.mir
    M llvm/test/CodeGen/AMDGPU/modf-constant-fold.ll
    M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
    M llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll
    M llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu-flat.mir
    M llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir
    M llvm/test/CodeGen/AMDGPU/move-to-valu-absdiff.mir
    M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-lshl_add.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-lshlrev.mir
    M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll
    M llvm/test/CodeGen/AMDGPU/movreld-bug.ll
    M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
    M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
    M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
    M llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
    M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll
    M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
    M llvm/test/CodeGen/AMDGPU/mubuf.ll
    M llvm/test/CodeGen/AMDGPU/mul.i16.ll
    M llvm/test/CodeGen/AMDGPU/mul.ll
    M llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
    M llvm/test/CodeGen/AMDGPU/mul_int24.ll
    M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
    M llvm/test/CodeGen/AMDGPU/multi-call-resource-usage-mcexpr.ll
    M llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
    M llvm/test/CodeGen/AMDGPU/multi-dword-vgpr-spill.ll
    M llvm/test/CodeGen/AMDGPU/multi-use-implicit-def.mir
    M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
    M llvm/test/CodeGen/AMDGPU/naked-fn-with-frame-pointer.ll
    M llvm/test/CodeGen/AMDGPU/nand.ll
    M llvm/test/CodeGen/AMDGPU/narrow_math_for_and.ll
    M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
    M llvm/test/CodeGen/AMDGPU/neg_ashr64_reduce.ll
    M llvm/test/CodeGen/AMDGPU/neighboring-mfma-padding.mir
    M llvm/test/CodeGen/AMDGPU/nested-calls.ll
    M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
    M llvm/test/CodeGen/AMDGPU/no-bundle-asm.ll
    M llvm/test/CodeGen/AMDGPU/no-corresponding-integer-type.ll
    M llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
    M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
    M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
    M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (26) (#209487)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)

To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications