[all-commits] [llvm/llvm-project] 469783: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

Tue Jul 14 09:53:39 PDT 2026

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4697832bae3f891c474fba3c58e852585bd1ff5f
      https://github.com/llvm/llvm-project/commit/4697832bae3f891c474fba3c58e852585bd1ff5f
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-14 (Tue, 14 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-all-indirect-accesses.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr-phi.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-inactive.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-indirect-extern-uses-max-reachable-alignment.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-classify.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-global-scope.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-internal-func.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-internal-multi-user.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-offsets.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-precise-allocate-to-module-struct.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-ambiguous.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-unambiguous.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-used-list.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-zero-size-arr.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds.ll
    M llvm/test/CodeGen/AMDGPU/lower-multiple-ctor-dtor.ll
    M llvm/test/CodeGen/AMDGPU/lower-noalias-kernargs.ll
    M llvm/test/CodeGen/AMDGPU/lower-term-opcodes.mir
    M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
    M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-opt.ll
    M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
    M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
    M llvm/test/CodeGen/AMDGPU/lrint.ll
    M llvm/test/CodeGen/AMDGPU/lro-coerce-v4i8-phi-loop.ll
    M llvm/test/CodeGen/AMDGPU/lro-phi-samebb-nonlookthrough-store.ll
    M llvm/test/CodeGen/AMDGPU/lround.ll
    M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
    M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
    M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/lsr-cost-model-vector-iv.ll
    M llvm/test/CodeGen/AMDGPU/lto-lower-module-lds.ll
    M llvm/test/CodeGen/AMDGPU/machine-cp-propagation.mir
    M llvm/test/CodeGen/AMDGPU/machine-cse-commute-target-flags.mir
    M llvm/test/CodeGen/AMDGPU/machine-cse-ssa.mir
    M llvm/test/CodeGen/AMDGPU/machine-function-info-cwsr.ll
    M llvm/test/CodeGen/AMDGPU/machine-scheduler-rematerialization-scoring.mir
    M llvm/test/CodeGen/AMDGPU/machine-scheduler-revert-slot-monotonicity.mir
    M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
    M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
    M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
    M llvm/test/CodeGen/AMDGPU/machine-sink-cycle.mir
    M llvm/test/CodeGen/AMDGPU/machine-sink-fence.ll
    M llvm/test/CodeGen/AMDGPU/machine-sink-ignorable-exec-use.mir
    M llvm/test/CodeGen/AMDGPU/machine-sink-lane-mask.mir
    M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll
    M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.mir
    M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
    M llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir
    M llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
    M llvm/test/CodeGen/AMDGPU/mad-combine.ll
    M llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
    M llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
    M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
    M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
    M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
    M llvm/test/CodeGen/AMDGPU/mad-mix.ll
    M llvm/test/CodeGen/AMDGPU/mad.u16.ll
    M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
    M llvm/test/CodeGen/AMDGPU/mad_int24.ll
    M llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
    M llvm/test/CodeGen/AMDGPU/mad_uint24.ll
    M llvm/test/CodeGen/AMDGPU/madak.ll
    M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
    M llvm/test/CodeGen/AMDGPU/mai-hazards-mfma-scale.gfx950.mir
    M llvm/test/CodeGen/AMDGPU/mai-hazards.mir
    M llvm/test/CodeGen/AMDGPU/mai-inline.ll
    M llvm/test/CodeGen/AMDGPU/make-buffer-rsrc-lds-fails.ll
    M llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
    M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
    M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
    M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
    M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
    M llvm/test/CodeGen/AMDGPU/max.i16.ll
    M llvm/test/CodeGen/AMDGPU/max.ll
    M llvm/test/CodeGen/AMDGPU/max3.ll
    M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
    M llvm/test/CodeGen/AMDGPU/maximumnum.ll
    M llvm/test/CodeGen/AMDGPU/mcexpr-knownbits-assign-crash-gh-issue-110930.ll
    M llvm/test/CodeGen/AMDGPU/mcp-aligned-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/mcp-implicit-clobber.mir
    M llvm/test/CodeGen/AMDGPU/mcp-overlap-after-propagation.mir
    M llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
    M llvm/test/CodeGen/AMDGPU/med3-knownbits.ll
    M llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll
    M llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
    M llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll
    M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
    M llvm/test/CodeGen/AMDGPU/memcpy-param-combinations.ll
    M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
    M llvm/test/CodeGen/AMDGPU/memcpy-scoped-aa.ll
    M llvm/test/CodeGen/AMDGPU/memcpy_const_compare.ll
    M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
    M llvm/test/CodeGen/AMDGPU/memmove-param-combinations.ll
    M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
    M llvm/test/CodeGen/AMDGPU/memmove-var-size.ll

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (24) (#209485)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)

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