[all-commits] [llvm/llvm-project] c09fc4: [libcxx][test] Fingerprint the compiler when memoi...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Tue Jul 14 06:46:53 PDT 2026
Branch: refs/heads/users/alexey-bataev/spr/slpadd-umaxuminsmaxsmin-as-main-opcodes-for-copyables
Home: https://github.com/llvm/llvm-project
Commit: c09fc4b786a3a49c350cecc696e21473c86ba330
https://github.com/llvm/llvm-project/commit/c09fc4b786a3a49c350cecc696e21473c86ba330
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M libcxx/utils/libcxx/test/dsl.py
Log Message:
-----------
[libcxx][test] Fingerprint the compiler when memoizing results (#208311)
This fixes a cache invalidation problem with flag support checks when
rebasing & re-building the just-built clang.
Commit: 9367769576a73771e227a0921b2103792c5a69a9
https://github.com/llvm/llvm-project/commit/9367769576a73771e227a0921b2103792c5a69a9
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M lld/docs/ReleaseNotes.rst
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[docs] Add ARM64X release notes (NFC) (#209249)
Commit: d90f3050c354b264c7156b8180b9ec1ab09c14c7
https://github.com/llvm/llvm-project/commit/d90f3050c354b264c7156b8180b9ec1ab09c14c7
Author: Ziqing Luo <ziqing_luo at apple.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/include/clang/ScalableStaticAnalysis/Analyses/TypeConstrainedPointers/TypeConstrainedPointers.h
M clang/lib/ScalableStaticAnalysis/Analyses/TypeConstrainedPointers/TypeConstrainedPointers.cpp
M clang/test/Analysis/Scalable/TypeConstrainedPointers/type-constrained-pointers.cpp
M clang/unittests/ScalableStaticAnalysis/Analyses/TypeConstrainedPointers/TypeConstrainedPointersExtractorTest.cpp
Log Message:
-----------
[SSAF][TypeConstrainedPointers] Add pointer parameters of 'main' as constrained pointers (#208578)
Similar to some pointer entities of operator new/delete overload
functions, pointer type parameters of the main function shall also
retain its type during clang-reforge transformation.
rdar://179151882
---------
Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
Commit: acbc7e571c3aa6f23672f84f5ea76cd41345a3a2
https://github.com/llvm/llvm-project/commit/acbc7e571c3aa6f23672f84f5ea76cd41345a3a2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
Log Message:
-----------
clang/AMDGPU: Validate -target-cpu in cc1 is valid for the subarch (#206481)
Restrict the reported list of valid target-cpus based on the triple's
subarch. This is more consistent with how other targets validate the
target CPU name. Currently we have split handling validating the target
name for the triple in both the driver and here. The driver based
diagnostic seems to be an amdgpu-ism in 2 different places (though there
is one arm validation emitting the same diagnostic). In the future we could
probably drop those.
Commit: 0661f6636a0a5a79635e99d98a239c2bba4ea2ed
https://github.com/llvm/llvm-project/commit/0661f6636a0a5a79635e99d98a239c2bba4ea2ed
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
A mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsReduction.h
M mlir/lib/Dialect/OpenACC/Utils/CMakeLists.txt
A mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsReduction.cpp
M mlir/unittests/Dialect/OpenACC/CMakeLists.txt
A mlir/unittests/Dialect/OpenACC/OpenACCUtilsReductionTest.cpp
Log Message:
-----------
[mlir][acc] Add reduction utilities for acc to gpu lowering (#209316)
In preparation for the pass that converts `acc.compute_region` to GPU
dialect, this PR adds several utilities which are used in that pass
related to reductions. Doing so to simplify review and to ensure that
unit testing is added for the utilities.
---------
Co-authored-by: Scott Manley <rscottmanley at gmail.com>
Commit: 51b2a5de73637e7d93cc066ced669d5db2bd8775
https://github.com/llvm/llvm-project/commit/51b2a5de73637e7d93cc066ced669d5db2bd8775
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
Log Message:
-----------
[RISCV][P-ext] Fix incorrect shift mask on variable shift instructions. (#209293)
The instructions are defined to read 5 bits regardless of element size.
I think we will also need to change the C intrinsics to allow 5 bit
shift amounts, but we can do that in a separate patch.
Commit: 4743729038650237f094073ad92edaa524a9261f
https://github.com/llvm/llvm-project/commit/4743729038650237f094073ad92edaa524a9261f
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 0661f66 (#209319)
This fixes 0661f6636a0a5a79635e99d98a239c2bba4ea2ed.
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=0661f6636a0a5a79635e99d98a239c2bba4ea2ed
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 5801213a1baaa750dd2c0152ca0e5288d447d908
https://github.com/llvm/llvm-project/commit/5801213a1baaa750dd2c0152ca0e5288d447d908
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
Log Message:
-----------
[ConstraintElim] Check loop pred & invariance before SCEV query (NFC) (#209314)
Move cheap checks (check for loop predecessor and invariance) before
more expensive SCEV queries.
This slightly reduces the number we need to unnecessarily construct SCEV
expressions.
Commit: 8d251a44830c869feb7d7d1db4fec8474f5a7ca8
https://github.com/llvm/llvm-project/commit/8d251a44830c869feb7d7d1db4fec8474f5a7ca8
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
Log Message:
-----------
[RISCV][P-ext] Move v2i16 and v4i8 extract_subvector handling to tablegen. NFC (#208863)
Commit: c6ebd7a2ced7fa3c984a857d6dcb433d95dd014d
https://github.com/llvm/llvm-project/commit/c6ebd7a2ced7fa3c984a857d6dcb433d95dd014d
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang-tools-extra/clang-doc/CMakeLists.txt
M clang-tools-extra/clang-doc/Generators.cpp
M clang-tools-extra/clang-doc/Generators.h
M clang-tools-extra/clang-doc/JSONGenerator.cpp
M clang-tools-extra/clang-doc/MDGenerator.cpp
R clang-tools-extra/clang-doc/MDMustacheGenerator.cpp
M clang-tools-extra/clang-doc/Representation.h
M clang-tools-extra/clang-doc/tool/ClangDocMain.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-doc/basic-project.mustache.test
M clang-tools-extra/test/clang-doc/basic-project.test
M clang-tools-extra/test/clang-doc/md/array-type.cpp
M clang-tools-extra/test/clang-doc/md/builtin_types.cpp
M clang-tools-extra/test/clang-doc/md/class-partial-specialization.cpp
M clang-tools-extra/test/clang-doc/md/comments-in-macros.cpp
M clang-tools-extra/test/clang-doc/md/enum.cpp
M clang-tools-extra/test/clang-doc/md/function-pointer-type.cpp
M clang-tools-extra/test/clang-doc/md/member-function-pointer-type.cpp
M clang-tools-extra/test/clang-doc/md/namespace.cpp
M clang-tools-extra/test/clang-doc/md/nested-pointer-qualifiers.cpp
M clang-tools-extra/test/clang-doc/md/templates.cpp
M clang-tools-extra/unittests/clang-doc/CMakeLists.txt
R clang-tools-extra/unittests/clang-doc/MDGeneratorTest.cpp
Log Message:
-----------
[clang-doc] Remove deprecated Markdown generator (#209071)
Commit: dd77cf572833b0ee31b9516d83cfcc0af932604d
https://github.com/llvm/llvm-project/commit/dd77cf572833b0ee31b9516d83cfcc0af932604d
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/test/Interpreter/pch-pic-mismatch.cpp
Log Message:
-----------
[Clang][Interpreter] Fix pch-pic-mismatch for darwin platforms (#209183)
Darwin enforce PIC by default and ignores all -fno-pic option. We calls
cc1 directly as its PIC level is 0 by default. This fixes the new
introduced test pch-pic-mismatch.cpp
Commit: c70795ccd5f74aad7f3af9490f8b12a92c39c709
https://github.com/llvm/llvm-project/commit/c70795ccd5f74aad7f3af9490f8b12a92c39c709
Author: Farid Zakaria <fmzakari at fb.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/include/llvm/MC/MCTargetOptions.h
M llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/MC/MCTargetOptions.cpp
M llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
A llvm/test/CodeGen/AArch64/large-eh-encoding.ll
A llvm/test/CodeGen/X86/large-eh-encoding.ll
A llvm/test/MC/AArch64/large-eh-encoding.s
A llvm/test/MC/X86/large-eh-encoding.s
Log Message:
-----------
[MC][CodeGen] Add --large-eh-encoding flag for x86_64 & Aarch64 ELF (#174508)
Add a --large-eh-encoding option that forces 8-byte (DW_EH_PE_sdata8)
pointer encodings for all x86_64 & aarch64 ELF EH sections: FDE CFI
encoding, personality, LSDA, and TType encodings.
This is useful for large binaries where .text may exceed 2GB, causing
relocation overflows in .eh_frame and .gcc_except_table even under the
small or medium code model. The cost is purely in section size (a few
extra bytes per FDE/LSDA entry) with no runtime performance impact.
Commit: 2dcec161f68761495cbd24f50cb0f9277600a5ac
https://github.com/llvm/llvm-project/commit/2dcec161f68761495cbd24f50cb0f9277600a5ac
Author: Kazu Hirata <kazu at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/include/llvm/ProfileData/SampleProfReader.h
M llvm/unittests/ProfileData/SampleProfTest.cpp
Log Message:
-----------
[ProfileData] Remove clear() from SampleProfileFuncOffsetTable (NFC) (#209301)
This patch deletes the default constructor of
SampleProfileFuncOffsetTable and removes its clear() method.
SampleProfileFuncOffsetTable is designed to lock its operational mode
(in-memory or on-disk) strictly at construction time and remain valid
throughout its lifetime. By deleting the default constructor and
removing clear(), we ensure that an instance never enters an
uninitialized or cleared state while kept alive.
When SampleProfileReader needs to discard or reload the table, it
resets and replaces the wrapping std::optional directly instead of
clearing the table in-place.
Assisted-by: Antigravity
Commit: 2d142ad3b6c3c105356ead9575c7998c924fc64b
https://github.com/llvm/llvm-project/commit/2d142ad3b6c3c105356ead9575c7998c924fc64b
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/include/lldb/Host/Host.h
M lldb/source/Host/common/Host.cpp
M lldb/source/Host/macosx/objcxx/Host.mm
Log Message:
-----------
[lldb/Host] Add `foreground` argument to `Host::OpenFileInExternalEditor` (#209331)
Add an optional `bool foreground` parameter to
`Host::OpenFileInExternalEditor` so callers can choose whether opening
the file should bring the editor to the foreground.
The macOS implementation maps `foreground=true` to omitting
`kLSLaunchDontSwitch` in the Launch Services flags, so the editor is
brought forward on launch. On non-Apple platforms the stub still returns
`ENOTSUP`; the new parameter is added to its signature so it matches the
declaration.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: d8636be51e34eb221054b1f70f0c73a901849f31
https://github.com/llvm/llvm-project/commit/d8636be51e34eb221054b1f70f0c73a901849f31
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsGPU.h
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsGPU.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsGPUTest.cpp
Log Message:
-----------
[mlir][acc] Add utilities for acc to gpu lowering (#209313)
In preparation for the pass that converts `acc.compute_region` to GPU
dialect, this PR adds several utilities which are used in that pass.
Doing so to simplify review and to ensure that unit testing is added for
each of the utilities.
Commit: 96ad6fc9e86d7cb2dbd0ad1646b40219fd6a8fda
https://github.com/llvm/llvm-project/commit/96ad6fc9e86d7cb2dbd0ad1646b40219fd6a8fda
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/Analysis/OpenACCSupport.h
M mlir/lib/Dialect/OpenACC/Analysis/OpenACCSupport.cpp
Log Message:
-----------
[mlir][acc] Add inline implementation for emitNYI (#209337)
Commit: d3e11d415a7dd7b594a023830df71500a272a8ca
https://github.com/llvm/llvm-project/commit/d3e11d415a7dd7b594a023830df71500a272a8ca
Author: Kewen Meng <Kewen.Meng at amd.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M offload/ci/openmp-offload-amdgpu-libc-runtime.py
Log Message:
-----------
[OpenMP][AMDGPU][CI] Fix libc build (#209336)
This PR attempts to fix the error:
```
llvm-lit: /home/botworker/builds/openmp-offload-amdgpu-runtime-2/llvm.src/llvm/utils/lit/lit/discovery.py:273: warning: input '/home/botworker/builds/openmp-offload-amdgpu-runtime-2/build/llvm.build/runtimes/runtimes-amdgpu-amd-amdhsa-bins/libc/test' contained no tests
error: did not discover any tests for provided path(s)
```
According to lib/test/CMakeList.txt, we need to set
`CMAKE_CROSSCOMPILING_EMULATOR` to avoid early return in the cmake. It
only changes the build script instead of the parent cmake cache file.
Not sure if this is the optimal solution, but it works for us.
Commit: 71a5f82e6dcd2d544d594c21a0bebb35af621ee5
https://github.com/llvm/llvm-project/commit/71a5f82e6dcd2d544d594c21a0bebb35af621ee5
Author: Mike Kruskal <mkruskal at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_nolibc.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_dl.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_dl.h
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/tsan/go/buildgo.sh
M compiler-rt/test/sanitizer_common/TestCases/Linux/dlopen_image_base.c
Log Message:
-----------
[compiler-rt] [sanitizer_common] Fix SIGSEGV in ForEachMappedRegion for DSOs with custom image base (#206299)
`ForEachMappedRegion` processes dynamic linker map entries to track
loaded segments. However, it assumes map->l_addr is the address of the
ELF header. For DSOs linked with a custom preferred image base offset
(e.g. -Wl,--image-base=0x4000000), `map->l_addr` contains the relocation
bias: `map->l_addr = actual_load_address - preferred_base`
In this case, map->l_addr points below the first loaded segment in
unmapped or PROT_NONE memory. Doing a read dereference at this address
triggers a SIGSEGV. Add a call to dladdr() on the dynamic section
pointer map->l_ld to obtain the true ELF header base address.
Likely fixes #84482 - which looks like the exact same stacktrace I was
debugging that led me to this fix
Also looks it may have shown up in #21068 - my case was also flaky, and
it only shows up if you build the so with custom base address
Assisted-by: Gemini
Commit: 311c23c1c611c8677f2131943f24884e0bce7e9d
https://github.com/llvm/llvm-project/commit/311c23c1c611c8677f2131943f24884e0bce7e9d
Author: Wenju He <wenju.he at intel.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/IPO/Attributor.cpp
Log Message:
-----------
[Attributor][NFC] Drop unused arg `AG` from runAttributor*OnFunctions (#209103)
Commit: 68d6e2a5c3991bb87ac65958bd044d268b1f6c30
https://github.com/llvm/llvm-project/commit/68d6e2a5c3991bb87ac65958bd044d268b1f6c30
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/source/Utility/Listener.cpp
Log Message:
-----------
[lldb] update the listener logs (#195850)
Add the event mask the listener is waiting for.
Commit: b5314610b4f318a3986069f3abc65eb6cf3a86fe
https://github.com/llvm/llvm-project/commit/b5314610b4f318a3986069f3abc65eb6cf3a86fe
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/include/clang/Basic/PointerAuthOptions.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/test/CodeGen/ptrauth-init-fini.c
M clang/test/CodeGen/ptrauth-module-flags.c
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64PointerAuth.h
A llvm/test/CodeGen/AArch64/ptrauth-init-fini-autoupgrade.ll
M llvm/test/CodeGen/AArch64/ptrauth-init-fini.ll
Log Message:
-----------
[AArch64][PAC] Handle signing of init/fini pointers in AsmPrinter (#193087)
Move signing of the contents of `@llvm.global_(ctors|dtors)` from Clang
frontend to the AsmPrinter at the end of the backend pipeline.
Signing of the pointers to init/fini functions in the backend fixes
registration of the constructors and destructors performed by the
optimizer or the backend.
This commit introduces two new module flags, `ptrauth-init-fini` and
`ptrauth-init-fini-address-discrimination`, mirroring corresponding
Clang options. The flags are semantically boolean, an absent flag is
treated as having the `false` value and the latter flag requires the
former one. The particular constant discriminator to use is not
configurable via module flags and is hardcoded to the value 0xD9D4 in
the `llvm/lib/Target/AArch64/AArch64PointerAuth.h` file.
Commit: 4d7e653b523027ffb67a6ee7e439392431cbee2d
https://github.com/llvm/llvm-project/commit/4d7e653b523027ffb67a6ee7e439392431cbee2d
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsGPUTest.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsReductionTest.cpp
Log Message:
-----------
[mlir][acc] Fix leaks in cg unit tests (#209339)
Newly added tests are failing valgrind --leak-check=full:
https://github.com/llvm/llvm-project/pull/209313
https://github.com/llvm/llvm-project/pull/209316
This PR resolves the problem by ensuring that the insertion point is set
into an operation that is owned and deleted by the test.
Commit: 14f8cccd02974067d81b173551bc301a33e26429
https://github.com/llvm/llvm-project/commit/14f8cccd02974067d81b173551bc301a33e26429
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang/test/CXX/drs/cwg5xx.cpp
Log Message:
-----------
[clang] Trivial: fix test followup to #208586 (#209340)
Removes the spell-check disable from `clang/test/CXX/drs/cwg5xx.cpp`,
works around spell check noise by renaming a declaration instead.
Commit: 89fc46ec511681a8fa56974295525d960538b88c
https://github.com/llvm/llvm-project/commit/89fc46ec511681a8fa56974295525d960538b88c
Author: Richard Smith <richard at metafoo.co.uk>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/compiler-rt/BUILD.bazel
Log Message:
-----------
Exclude libc math C++ builtins from compiler-rt Bazel overlay (#208861)
In CMake, addtf3.cpp is only compiled when COMPILER_RT_USE_LIBC_MATH is
ON, replacing addtf3.c. In the Bazel overlay, builtins_generic_srcs
globbed all lib/builtins/*.cpp without excluding addtf3.cpp, causing
compile failures when not using libc math.
Assisted-by: Gemini via Antigravity
Commit: 25d50e7a0fe4cf42ca9351fc95528ac3e3c7a463
https://github.com/llvm/llvm-project/commit/25d50e7a0fe4cf42ca9351fc95528ac3e3c7a463
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
R lldb/include/lldb/Interpreter/Interfaces/ScriptedStopHookInterface.h
M lldb/include/lldb/Interpreter/ScriptInterpreter.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/lldb-forward.h
M lldb/source/Plugins/ScriptInterpreter/Python/CMakeLists.txt
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedHookPythonInterface.h
R lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedStopHookPythonInterface.cpp
R lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedStopHookPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
M lldb/source/Target/Target.cpp
Log Message:
-----------
[lldb] Unify `ScriptedStopHookInterface` with `ScriptedHookInterface` (#209341)
`ScriptedHookInterface` already carries a `HandleStop` entry point, so
`ScriptedStopHookInterface` is a proper subset. Delete
`ScriptedStopHookInterface`, `ScriptedStopHookPythonInterface`, and
`ScriptInterpreter::CreateScriptedStopHookInterface`, and route
`Target::StopHookScripted` through `ScriptedHookInterface` /
`CreateScriptedHookInterface` instead.
The `target stop-hook add -P <classname>` command is unchanged; it now
constructs a `ScriptedHookInterface` internally, so any existing
`ScriptedStopHook` subclass keeps working as long as it exposes a
`handle_stop` method. New scripts should subclass `ScriptedHook`
directly (which is a superset).
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 2609cdb07323adac773a1a77e42eb294cd1b815d
https://github.com/llvm/llvm-project/commit/2609cdb07323adac773a1a77e42eb294cd1b815d
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
M llvm/lib/Target/BPF/BPFPassRegistry.def
Log Message:
-----------
[BPF][NewPM] Port SelectionDAG ISel
Similar to MSP430 (f122acf2d0b8c806bfa7be81aea0344bfd6fc225).
This is part of getting BPF to work with the NewPM.
Reviewers: yonghong-song, aeubanks, eddyz87
Pull Request: https://github.com/llvm/llvm-project/pull/207638
Commit: a718d2ad092bec5b7fe81e043ad276cb6ae97a50
https://github.com/llvm/llvm-project/commit/a718d2ad092bec5b7fe81e043ad276cb6ae97a50
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
A llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
M llvm/lib/Target/BPF/BPFTargetMachine.h
M llvm/lib/Target/BPF/CMakeLists.txt
Log Message:
-----------
[BPF][NewPM] Introduce BPFCodeGenPassBuilder
Part of the transition to the NewPM for CodeGen. Similar to
f122acf2d0b8c806bfa7be81aea0344bfd6fc225.
Reviewers: eddyz87, yonghong-song, aeubanks
Pull Request: https://github.com/llvm/llvm-project/pull/207643
Commit: f4d2c6e772e60a05a915b6ecda1bf12e8dd6c2d3
https://github.com/llvm/llvm-project/commit/f4d2c6e772e60a05a915b6ecda1bf12e8dd6c2d3
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp
M llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp
M llvm/lib/Target/BPF/BPFPassRegistry.def
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
M llvm/test/CodeGen/BPF/sink-min-max.ll
Log Message:
-----------
[BPF][NewPM] Port bpf-check-and-opt-ir
Standard pass porting. Part of the effort to make BPF work solely with
the new pass manager.
Reviewers: eddyz87, aeubanks, yonghong-song
Pull Request: https://github.com/llvm/llvm-project/pull/207787
Commit: ce5291e94b55bfb7d3bedd4d82684f50f9782847
https://github.com/llvm/llvm-project/commit/ce5291e94b55bfb7d3bedd4d82684f50f9782847
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp
M llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
M llvm/lib/Target/BPF/BPFPassRegistry.def
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
Log Message:
-----------
[BPF][NewPM] Port BPFMISimplifyPatchablePass
Standard pass porting. Needed to get the BPF backend fully working with
the NewPM.
Reviewers: aeubanks, eddyz87, yonghong-song
Pull Request: https://github.com/llvm/llvm-project/pull/207800
Commit: e7831765ca43e689d66a6e1fea6ac19edd7cc8c7
https://github.com/llvm/llvm-project/commit/e7831765ca43e689d66a6e1fea6ac19edd7cc8c7
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp
M llvm/lib/Target/BPF/BPFMIPeephole.cpp
M llvm/lib/Target/BPF/BPFPassRegistry.def
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
Log Message:
-----------
[BPF][NewPM] Port BPFMIPeephole
Standard pass porting. Needed to make BPF work fully with the NewPM.
Reviewers: eddyz87, yonghong-song, aeubanks
Pull Request: https://github.com/llvm/llvm-project/pull/207805
Commit: 618b65a268a5f0df6405a18cad876f63e5721739
https://github.com/llvm/llvm-project/commit/618b65a268a5f0df6405a18cad876f63e5721739
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/BPFMIPeephole.cpp
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
Log Message:
-----------
[BPF] Split stack argument psuedo expansion into a separate pass
This will make the NewPM implementation cleaner given now the two passes
are either required/optional rather than like BPFMIPreEmitPeepholePass
before, which was partially required (for stack argument psuedo
expansion), and optional for other peephole optimizations. I think this
is also a cleaner design in general.
Reviewers: aeubanks, eddyz87, yonghong-song
Pull Request: https://github.com/llvm/llvm-project/pull/207844
Commit: a5c6a7a6a172fc47e0c608497d7e0fe1166474c1
https://github.com/llvm/llvm-project/commit/a5c6a7a6a172fc47e0c608497d7e0fe1166474c1
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/bindings/python/CMakeLists.txt
M lldb/docs/CMakeLists.txt
A lldb/examples/python/templates/scripted_breakpoint.py
A lldb/examples/python/templates/scripted_hook.py
Log Message:
-----------
[lldb/script] Add scripted extension base-class templates for hooks and breakpoint resolvers (#209311)
This patch adds the Python base-class templates for `ScriptedHook` (a
unified base class that backs both `target hook add -P` and `target
stop-hook add -P`) and `ScriptedBreakpointResolver`, and wires them into
the Python bindings and docs CMake so every scriptable extension kind
has a template that the docs and future tooling can introspect.
The `ScriptedHook` template unifies what used to require separate
subclasses for target hooks and stop hooks: subclasses implement
`handle_stop` (required, so any hook is a valid stop-hook) and
optionally `handle_module_loaded` / `handle_module_unloaded`, which only
fire for hooks registered via `target hook add -P`.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 670816cf58027f1bfea39ec0745b415bea0275a9
https://github.com/llvm/llvm-project/commit/670816cf58027f1bfea39ec0745b415bea0275a9
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp
M llvm/lib/Target/BPF/BPFMIPeephole.cpp
M llvm/lib/Target/BPF/BPFPassRegistry.def
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
Log Message:
-----------
[BPF][NewPM] Port BPFMIExpandStackArgPseudosPass
Standard pass porting. Required to get BPF fully working with the NewPM.
Reviewers: eddyz87, aeubanks, yonghong-song
Pull Request: https://github.com/llvm/llvm-project/pull/207845
Commit: 6cde0bcec417016c82329d55401b0717de65f36d
https://github.com/llvm/llvm-project/commit/6cde0bcec417016c82329d55401b0717de65f36d
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp
M llvm/lib/Target/BPF/BPFMIPeephole.cpp
M llvm/lib/Target/BPF/BPFPassRegistry.def
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
Log Message:
-----------
[BPF][NewPM] Port BPFMIPreEmitPeepholePass
Standard pass porting. This is needed for BPF to fully support the new
pass manager.
Reviewers: eddyz87, yonghong-song, aeubanks
Pull Request: https://github.com/llvm/llvm-project/pull/207847
Commit: 07a4eac758af73bf58b5ec9653a4950187774a18
https://github.com/llvm/llvm-project/commit/07a4eac758af73bf58b5ec9653a4950187774a18
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp
M llvm/lib/Target/BPF/BPFMIChecking.cpp
M llvm/lib/Target/BPF/BPFPassRegistry.def
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
Log Message:
-----------
[BPF][NewPM] Port BPFMIPreEmitCheckingPass
Standard pass porting. Needed to make BPF fully support the NewPM.
Reviewers: yonghong-song, aeubanks, eddyz87
Pull Request: https://github.com/llvm/llvm-project/pull/207850
Commit: 7a756ba8edc8f762b26999008debd62103f8e267
https://github.com/llvm/llvm-project/commit/7a756ba8edc8f762b26999008debd62103f8e267
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPFAsmPrinter.cpp
M llvm/lib/Target/BPF/BPFAsmPrinter.h
M llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp
Log Message:
-----------
[BPF][NewPM] Port AsmPrinter
This is necessary to make the new pass manager fully supported for BPF.
This should be the last patch in the series.
Reviewers: yonghong-song, arsenm, eddyz87
Pull Request: https://github.com/llvm/llvm-project/pull/207854
Commit: 252ad2052409a33eff59a149053ec90f7fae03df
https://github.com/llvm/llvm-project/commit/252ad2052409a33eff59a149053ec90f7fae03df
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M compiler-rt/lib/gwp_asan/optional/backtrace_linux_libc.cpp
Log Message:
-----------
[compiler-rt][GWP-ASan] Use no-op backtrace if execinfo.h missing (#201266)
Guard backtrace_linux_libc.cpp with __has_include(<execinfo.h>) so that
targets without it (e.g. musl libc) get null stubs instead of a build
failure.
Commit: 2b8488ac148f06657aa6ec18f1ee38c79b241635
https://github.com/llvm/llvm-project/commit/2b8488ac148f06657aa6ec18f1ee38c79b241635
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[BPF][ProfCheck] Exclude sink-min-max.ll (#209352)
This was exposed by porting the pass to the NewPM, so just exclude it
for now.
Commit: 4058610aecb6d261f3ea1777dd5c0e531a5cc17e
https://github.com/llvm/llvm-project/commit/4058610aecb6d261f3ea1777dd5c0e531a5cc17e
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
Log Message:
-----------
[Hexagon] Register MachineKCFILegacy pass in LLVMInitializeHexagonTarget (#209245)
Hexagon's target-init function never called
initializeMachineKCFILegacyPass(PR), unlike X86, ARM, AArch64, and
RISCV. Since PassRegistry is process-wide and each target's init
function registers passes as a side effect when linked into the same
binary, whether test/CodeGen/Hexagon/kcfi.ll passed depended on whether
some other target providing that registration was also built into llc,
rather than on Hexagon's own configuration.
Commit: e2c8fa09872cfacba7f73599dcf8557971ebe865
https://github.com/llvm/llvm-project/commit/e2c8fa09872cfacba7f73599dcf8557971ebe865
Author: Amy Kwan <amy.kwan1 at ibm.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Object/ArchiveWriter.cpp
A llvm/test/tools/llvm-ar/zos-write.test
M llvm/tools/llvm-ar/llvm-ar.cpp
Log Message:
-----------
[SystemZ][z/OS] Add z/OS archive writing support (#200087)
This patch implement z/OS archive writing in ArchiveWriter and adds the
option `llvm-ar --format=zos`.
Moreover, This patch teaches `llvm-ar` to emit z/OS-compatible archives
by:
- Detecting GOFF object files as z/OS members
- Writing z/OS member headers and archive magic
- Converting archive headers and symbol-name string tables to EBCDIC
- Emitting z/OS symbol table entries
- Using EBCDIC newline padding bytes
- Add a z/OS-specific workaround for empty symbol tables by emitting a
dummy blank symbol to satisfy binder requirements.
Commit: 6e5c97d417d1ec16c095aba6630995406dde1d87
https://github.com/llvm/llvm-project/commit/6e5c97d417d1ec16c095aba6630995406dde1d87
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt/AllocAction.h
R orc-rt/lib/executor/AllocAction.cpp
M orc-rt/lib/executor/CMakeLists.txt
M orc-rt/lib/executor/SimpleNativeMemoryMap.cpp
M orc-rt/test/unit/AllocActionTest.cpp
M orc-rt/test/unit/CommonTestUtils.h
Log Message:
-----------
[orc-rt] Hoist run-alloc-actions functions, add error reporting. (#209356)
Hoist runFinalizeActions and runDeallocActions into AllocAction.h and
turn them into function templates with a ReportErrorFn argument that
enables error reporting. This is used to report errors from dealloc
actions.
Update SimpleNativeMemoryMap to direct such errors to the Session via
ReportErrorsViaSession.
Add unit tests covering the new error-reporting paths.
Commit: 0c19355a6b3e88fcb98a398845735c6ae19a2142
https://github.com/llvm/llvm-project/commit/0c19355a6b3e88fcb98a398845735c6ae19a2142
Author: Nicolas Miller <nicolas.pierre.miller at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
M llvm/test/CodeGen/Hexagon/autohvx/conv-fp-fp.ll
Log Message:
-----------
[Hexagon] Fix fpround fp32 -> fp16 pattern (#199704)
The pattern was passing hi and lo in the wrong order to `vcvt` causing
the final output after `vdeal` to be incorrect.
Commit: 5b3fbf852e5d72d3a78ff4646a8ddad3c8d50536
https://github.com/llvm/llvm-project/commit/5b3fbf852e5d72d3a78ff4646a8ddad3c8d50536
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lldb/include/lldb/Core/PluginManager.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/Core/PluginManager.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/OperatingSystemPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/OperatingSystemPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedBreakpointPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedFrameProviderPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedFramePythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedFramePythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedHookPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPlatformPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPlanPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPythonInterface.h
M lldb/test/Shell/Commands/command-scripting-extension-list.test
Log Message:
-----------
[lldb] Expand ScriptedExtension coverage across scripted Python interfaces (NFC) (#209307)
Commit: 795a5a9a19bb2b356d82a46426d95f245d1d0049
https://github.com/llvm/llvm-project/commit/795a5a9a19bb2b356d82a46426d95f245d1d0049
Author: Vijay Kandiah <vkandiah at nvidia.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Lower/CUDA/cuda-implicit-managed-alloc.cuf
Log Message:
-----------
[flang][cuda] Implicitly attribute allocatables/pointers under -gpu=unified (#209292)
When `-gpu=unified` is in effect, allocatables and pointers with no
explicit CUDA data attribute were left with no data attribute, and were allocated
as ordinary host memory. Under unified memory, such objects must be
reachable from the device; leaving them as plain host allocations makes device kernels
fault on systems that do not provide transparent host-memory access.
The existing code here already assigned `Managed` implicitly under
`-gpu=managed` (when CUDA Fortran is enabled). This extends that handling to
`-gpu=unified`: prefer the `Unified` attribute where it is legal (host subprogram, main
program, or derived-type component) so generic resolution still selects the unified
specific, and fall back to `Managed` elsewhere (module scope, device
subprograms). Both attributes route allocation through the same managed
allocator, so this keeps the allocation device-accessible while avoiding
spurious `ATTRIBUTES(UNIFIED)` legality errors.
The attribution stays gated on CUDA Fortran being enabled, preserving
the existing behavior for non-CUDA-Fortran translation units.
Commit: b15f9326d21cbd05463fcb34d989bae95982cc9b
https://github.com/llvm/llvm-project/commit/b15f9326d21cbd05463fcb34d989bae95982cc9b
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
A flang/test/Evaluate/fold-kind-logical.f90
A flang/test/Evaluate/fold-kind-substring.f90
A flang/test/Evaluate/fold-kind-zero-size.f90
M flang/test/Evaluate/logical-args.f90
A flang/test/Lower/HLFIR/array-ctor-character-kind.f90
A flang/test/Semantics/modfile84.F90
A flang/test/Semantics/substring-literal-kind.f90
Log Message:
-----------
[flang] Add kind-preservation regression tests (#208760)
These tests pin currently-correct behaviors where the KIND type
parameter of a result must be preserved by constant folding, semantics,
and lowering. They all pass at head; their purpose is to guard against
silent kind loss during future refactoring of the Evaluate library's
type-parameterized machinery (see the discussion on PR #206907, where an
experimental rewrite passed check-flang while dropping kinds in several
places).
Folded LOGICAL operations: `.NOT./.AND./.OR./.EQV./.NEQV.` keep their
operand kind; ANY/ALL/PARITY and logical DOT_PRODUCT results have the
MASK/argument kind (F2023 16.9.14/16.9.16/16.9.148), including for empty
masks where there is no element value to take a kind from; MERGE and
TRANSFER keep the TSOURCE/MOLD kind; STORAGE_SIZE of folded
non-default-kind logicals folds to the right value; the default BOUNDARY
fill element of a folded EOSHIFT has the array's kind; relational
results are default logical regardless of operand kinds; and generic
resolution over LOGICAL kinds is unchanged by folding
(flang/test/Evaluate/fold-kind-logical.f90 and an extension of
flang/test/Evaluate/logical-args.f90).
Empty typed array constructors and zero-size PACK/SPREAD/RESHAPE/UNPACK
results keep the kind (and character length) of their type-spec (F2023
7.8), including across a module file into a separately compiled
consumer, and empty non-default-kind character array constructors lower
with the correct `!fir.char` element type
(flang/test/Evaluate/fold-kind-zero-size.f90,
flang/test/Semantics/modfile84.F90,
flang/test/Lower/HLFIR/array-ctor-character-kind.f90).
A substring of a character literal has the kind of the literal (F2023
9.4.1): KIND() and LEN() fold correctly, and concatenation with a
same-kind literal is accepted
(flang/test/Evaluate/fold-kind-substring.f90,
flang/test/Semantics/substring-literal-kind.f90).
Assisted-by: AI
Commit: b959f7886f0fdbf8f683c11e945cca3f1afca36a
https://github.com/llvm/llvm-project/commit/b959f7886f0fdbf8f683c11e945cca3f1afca36a
Author: Sean Perry <perry at ca.ibm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/utils/lit/lit/builtin_commands/cat.py
Log Message:
-----------
Add text file support for z/OS back in (#209259)
Support for auto conversion of text files was added to cat.py in
https://github.com/llvm/llvm-project/pull/90128. That was accidently
removed in https://github.com/llvm/llvm-project/pull/204711 while
removing some old win32 code. This adds the z/OS support back in.
Commit: 67f5b53995d3e8ce0b062ea73be1fbb9186d6b30
https://github.com/llvm/llvm-project/commit/67f5b53995d3e8ce0b062ea73be1fbb9186d6b30
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M lld/test/ELF/retain-symbols-file.s
Log Message:
-----------
[ELF,test] Improve retain-symbols-file.s (#209366)
Commit: f18e59a195eb253573a26c118d3a09a83acb73ca
https://github.com/llvm/llvm-project/commit/f18e59a195eb253573a26c118d3a09a83acb73ca
Author: Thurston Dang <thurston at google.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_nolibc.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_dl.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_dl.h
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/tsan/go/buildgo.sh
M compiler-rt/test/sanitizer_common/TestCases/Linux/dlopen_image_base.c
Log Message:
-----------
Revert "[compiler-rt] [sanitizer_common] Fix SIGSEGV in ForEachMappedRegion for DSOs with custom image base" (#209371)
Reverts llvm/llvm-project#206299 due to buildbot breakage
(https://github.com/llvm/llvm-project/pull/206299#issuecomment-4964804971)
Commit: c4edd8bde42cf6b1a25839601b75f3865bba6976
https://github.com/llvm/llvm-project/commit/c4edd8bde42cf6b1a25839601b75f3865bba6976
Author: ejose02 <ejose at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/Object/IRSymtab.h
A llvm/test/Object/X86/irsymtab-large-common.ll
M llvm/test/Object/X86/irsymtab.ll
Log Message:
-----------
[Object] Fix irsymtab CommonSize truncation past 4 GiB (#209085)
Fixes #208669
Issue :
With -flto, Fortran COMMON blocks larger than 4 GiB were silently
miscompiled. The linker reserved only the low 32 bits of the declared
size, so stores past that boundary could segfault with no diagnostic.
Root Cause :
storage::Uncommon::CommonSize in the LTO irsymtab was stored as 32-bit
(Word). Sizes above 2^32 bytes were truncated when the symtab was
written and read back at link time.
Fix :
Widen CommonSize to 64-bit and bump irsymtab format version to 4. Added
test to verify symtab records the full size.
Commit: a527c6f0bc9644cf8b13a9fb5a43e81257bedba6
https://github.com/llvm/llvm-project/commit/a527c6f0bc9644cf8b13a9fb5a43e81257bedba6
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/lib/executor/Logging.cpp
Log Message:
-----------
[orc-rt] Statically check logging category/level name array sizes. (#209372)
Add static_asserts to trigger compilation failure if the sizes of these
arrays don't match their respective enum/macro value ranges.
Commit: a70234b00d12aaa7723eb2ae5e8efe3348aeeb37
https://github.com/llvm/llvm-project/commit/a70234b00d12aaa7723eb2ae5e8efe3348aeeb37
Author: Sergey Shcherbinin <sscherbinin at nvidia.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROpsSupport.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/FunctionAttr.cpp
A flang/test/Driver/function-attr-readonly.f90
M flang/test/Lower/HLFIR/structure-constructor.f90
M flang/test/Lower/Intrinsics/dconjg.f90
M flang/test/Lower/Intrinsics/dimag.f90
M flang/test/Lower/Intrinsics/dreal.f90
M flang/test/Lower/OpenMP/optional-argument-map.f90
M flang/test/Lower/OpenMP/wsloop-unstructured.f90
M flang/test/Lower/achar.f90
M flang/test/Lower/arguments.f90
M flang/test/Lower/call-copy-in-out.f90
M flang/test/Lower/dispatch.f90
A flang/test/Lower/dummy-argument-readonly.f90
M flang/test/Lower/polymorphic-temp.f90
M flang/test/Lower/polymorphic.f90
M flang/test/Lower/select-type.f90
M flang/test/Lower/unsigned-ops.f90
M flang/test/Lower/volatile1.f90
A flang/test/Transforms/function-attrs-readonly.fir
Log Message:
-----------
[flang] Propagate INTENT(IN) dummy arguments as readonly (#207732)
Mark eligible `INTENT(IN)` dummy data objects with a `fir.read_only`
argument attribute during lowering, and teach `FunctionAttr` to
translate the marker to LLVM `readonly` for reference arguments when
optimizing for speed.
LLVM FunctionAttrs can infer `readonly` later in the pipeline, but this
happens too late for IPSCCP function specialization.
`FunctionSpecializer::promoteConstantStackValues` requires
`onlyReadsMemory()` before promoting constant by-reference scalar
arguments. Providing `readonly` satisfies this check and allows these
arguments to be promoted, enabling function specialization, including in
non-LTO builds.
For direct-data arguments, restrict propagation to by-reference
non-character intrinsic scalars. Ordinary arrays and derived-type
arguments are excluded because compiler-generated copy-out may write
back through a forwarded dummy argument. LLVM `readonly` does not permit
such writes, even when the stored value is unchanged.
`INTENT(IN)` `POINTER` and `ALLOCATABLE` dummies are supported with
shallow descriptor semantics: `readonly` protects the descriptor
storage, but does not imply that data addressed by the descriptor is
read-only. In particular, a `POINTER` target may still be modified.
Keep `readonly` handling independent from `noalias` and `nocapture`.
`TARGET` arguments may receive `readonly`, but must not receive
`noalias` or `nocapture`. Apply `readonly` to `BIND(C)` definitions
while leaving external C declarations unannotated. `VALUE`,
`ASYNCHRONOUS`, and `VOLATILE` dummy arguments remain excluded.
In our measurements, the enabled function specialization gives a 1.5x
speedup on 548.exchange2 on NVIDIA Neoverse V2 in a non-LTO
configuration.
Update existing lowering tests to account for the new `fir.read_only`
argument attribute, and add focused coverage:
* `dummy-argument-readonly.f90` checks marker emission for supported
scalar and descriptor arguments, excluded cases, and shallow pointer
semantics.
* `function-attrs-readonly.fir` checks translation from `fir.read_only`
to LLVM `readonly`, including `TARGET`, `BIND(C)`, and descriptor
references.
* `function-attr-readonly.f90` checks the optimization-level pipeline
gate and verifies that `readonly` reaches final LLVM IR.
* `call-copy-in-out.f90` checks that ordinary array copy-out cases
remain unmarked and that pointer-target copy-out is compatible with
shallow descriptor `readonly`.
Commit: 44a42e631e5b4e01855750c371dea87fb3927550
https://github.com/llvm/llvm-project/commit/44a42e631e5b4e01855750c371dea87fb3927550
Author: Peiqi Li <voyager.lpq at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang-tools-extra/clang-tidy/misc/RedundantExpressionCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/misc/redundant-expression.cpp
Log Message:
-----------
[clang-tidy] Fix false positive in misc-redundant-expression with type aliases (#198085)
The `misc-redundant-expression` check previously flagged expressions as
redundant if their underlying `DeclRefExpr` pointed to the same
declaration. This caused false positives when comparing identical values
accessed through distinct type aliases.
Following Clang's diagnostic `aka` logic, this patch uses the AST
Printer to stringify and compare the `NestedNameSpecifier` and
`TemplateArguments`. This safely preserves sugared types while natively
normalizing all whitespaces and newlines, ensuring robustness against
multiline formatting changes.
Fixes #145415
Commit: 6de51be4f636eda95e439db50f8463bdf8bde02e
https://github.com/llvm/llvm-project/commit/6de51be4f636eda95e439db50f8463bdf8bde02e
Author: David Green <david.green at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
Log Message:
-----------
[AArch64][GlobalISel] Legalization for bf16 fptosi/fptoui. (#209206)
Similar to other operations, this makes sure we can widen bf16
fptosi/fptoui correctly, promoting the value to a f32. The vector
variants have been proven by exhaustive checking.
Commit: 1bd46015ea4e842091109cd2a491c55c0b455330
https://github.com/llvm/llvm-project/commit/1bd46015ea4e842091109cd2a491c55c0b455330
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M clang-tools-extra/clang-doc/CMakeLists.txt
M clang-tools-extra/clang-doc/Generators.cpp
M clang-tools-extra/clang-doc/Generators.h
M clang-tools-extra/clang-doc/Representation.h
R clang-tools-extra/clang-doc/YAMLGenerator.cpp
M clang-tools-extra/clang-doc/tool/ClangDocMain.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
R clang-tools-extra/test/clang-doc/yaml/builtin_types.cpp
R clang-tools-extra/test/clang-doc/yaml/conversion_function.cpp
R clang-tools-extra/test/clang-doc/yaml/single-file-public.cpp
R clang-tools-extra/test/clang-doc/yaml/single-file.cpp
R clang-tools-extra/test/clang-doc/yaml/templates.cpp
M clang-tools-extra/unittests/clang-doc/CMakeLists.txt
R clang-tools-extra/unittests/clang-doc/YAMLGeneratorTest.cpp
Log Message:
-----------
[clang-doc] Remove the YAML generator (#209350)
The original intent of the YAML generator was to package the
documentation information in a structured and reusable way. It has been
superseded by the JSON generator.
Commit: 05b6b4f1af9f2eb5bebc2cfd10b2fff6bbfab55d
https://github.com/llvm/llvm-project/commit/05b6b4f1af9f2eb5bebc2cfd10b2fff6bbfab55d
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt-c/Logging.h
M orc-rt/lib/executor/Logging.cpp
M orc-rt/test/unit/LoggingTest.cpp
Log Message:
-----------
[orc-rt] Add new ControllerAccess logging category. (#209380)
The orc_rt_log_Category_ControllerAccess category should be used to log
messages from ControllerAccess implementations. E.g.
ORC_RT_LOG(Error, ControllerAccess, "connect() failed with <error>");
Commit: 4d5bc903c8a79fbadb62d8dd1e7cc93ad7a394fd
https://github.com/llvm/llvm-project/commit/4d5bc903c8a79fbadb62d8dd1e7cc93ad7a394fd
Author: Sean Clarke <sclarke at tenstorrent.com>
Date: 2026-07-13 (Mon, 13 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/test/CodeGen/AArch64/clmul.ll
M llvm/test/CodeGen/RISCV/clmul.ll
M llvm/test/CodeGen/X86/clmul.ll
Log Message:
-----------
[SelectionDAG] Improve `CLMUL` lowering for `Promote` types wider than register width (#209265)
For `ISD::CLMUL`, add a check to `PromoteIntRes_CLMUL` to take advantage
of the cross-product expansion in `ExpandIntRes_CLMUL` when possible for
`Promote` types which are wider than the register width (e.g. `i96` for
64-bit registers).
Commit: 8eb6e260047bd2f69d9d2c1f0967ae59f7ec5374
https://github.com/llvm/llvm-project/commit/8eb6e260047bd2f69d9d2c1f0967ae59f7ec5374
Author: Martin Storsjö <martin at martin.st>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M openmp/runtime/src/kmp_utility.cpp
Log Message:
-----------
[openmp] Apply a mingw/64 bit codepath to arm64ec too (#209297)
When targeting arm64ec, neither KMP_ARCH_X86_64 nor KMP_ARCH_AARCH64 is
defined.
This fixes a compilation warning when building openmp for mingw/arm64ec.
Commit: a436e36f5e57e8daabee71fd0cb649c1633e314f
https://github.com/llvm/llvm-project/commit/a436e36f5e57e8daabee71fd0cb649c1633e314f
Author: David Green <david.green at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/round-fptoui-sat-scalar.ll
Log Message:
-----------
[AArch64][GlobalISel] Legalization for bf16 fptosi.sat/fptoui.sat (#209378)
This is the equivalent change to #209206 for fptoi.sat.
Commit: f60650c772485640b57520e91cec9779cc7f27dc
https://github.com/llvm/llvm-project/commit/f60650c772485640b57520e91cec9779cc7f27dc
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
Log Message:
-----------
[BitcodeReader] Lazily read and cache target triple (NFC) (#208175)
Lazily read and cache the target triple from the stream, currently meant
to be used only for upgrading AArch64 memory effects from old bitcode.
Co-authored-by: Caroline Concatto <caroline.concatto at arm.com>
Commit: 69ee6b114ac3d3c6652b39d0d57b292bcfa3a81c
https://github.com/llvm/llvm-project/commit/69ee6b114ac3d3c6652b39d0d57b292bcfa3a81c
Author: WMC <tnwilly at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Dialect/LLVMIR/nvvm.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
Log Message:
-----------
[NVVM] Add FP8 (e4m3/e5m2) support to dense mma.sync (#207307)
## Motivation
I'm adding NVIDIA FP8 mma.sync support in IREE for sm_89/sm_120, and
IREE's codegen lowers through `nvgpu.mma.sync` on this path, which in
turn lowers to `nvvm.mma.sync`. This MLIR-level gap is blocking that
work, so I'm upstreaming the fix here first. This is split into two PRs
per review feedback — this one covers `nvvm.mma.sync` only; a follow-up
PR will add the corresponding `nvgpu.mma.sync` support built on top of
this.
## Description:
`nvvm.mma.sync` (warp-level, dense) don't support FP8 (e4m3/e5m2)
operands, even though the underlying PTX/NVPTX intrinsics have supported
FP8 `mma.sync.m16n8k32` since sm_89. FP8 currently only exists on the
sparse mma path and on warpgroup-level `wgmma`; the warp-level dense
path was never updated.
This adds FP8 (e4m3/e5m2) support to `nvvm.mma.sync`, covering
`m16n8k16` and `m16n8k32`.
## Verification
`$ mlir-opt mlir/test/Dialect/LLVMIR/nvvm.mlir -split-input-file
-verify-diagnostics | FileCheck mlir/test/Dialect/LLVMIR/nvvm.mlir
`
```
%0 = nvvm.mma.sync A[...] B[...] C[...]
{multiplicandAPtxType = #nvvm.mma_type<e4m3>,
multiplicandBPtxType = #nvvm.mma_type<e4m3>,
shape = #nvvm.shape<m = 16, n = 8, k = 32>}
: (i32, i32, f32) -> !llvm.struct<(f32, f32, f32, f32)>
```
`$ mlir-translate -mlir-to-llvmir mlir/test/Target/LLVMIR/nvvmir.mlir
-split-input-file -verify-diagnostics | FileCheck
mlir/test/Target/LLVMIR/nvvmir.mlir
`
```
%8 = call { float, float, float, float } @llvm.nvvm.mma.m16n8k16.row.col.f32.e4m3.e4m3.f32(i32 %0, i32 %1, i32 %2, float %3, float %4, float %5, float %6)
%11 = call { float, float, float, float } @llvm.nvvm.mma.m16n8k32.row.col.f32.e4m3.e5m2.f32(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, float %6, float %7, float %8, float %9)
```
All existing tests in nvvm.mlir (including -verify-diagnostics error
cases) still pass — no regression.
Co-authored with Claude Sonnet 5
Signed-off-by: weimin023 <tnwilly at gmail.com>
Commit: 317efbe4496900a60de09812aa91b1f486b2e795
https://github.com/llvm/llvm-project/commit/317efbe4496900a60de09812aa91b1f486b2e795
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/branch-cond-split-fcmp.ll
M llvm/test/CodeGen/AArch64/sve2p1-while-pn-folds.ll
Log Message:
-----------
[AArch64] Fold CSET + BR_CC into a conditional branch (#207398)
Fold CSETs into conditional branches (rather than lowering to a CSET +
TB[N]Z). This is most useful for lowering loop conditions based on
predicate-as-counter whiles to:
```
whilelo pn8.s, x0, x1, vlx4
b.mi .Lloop
```
Commit: 70496276d0f441999b61e84ca22e59d61fa43582
https://github.com/llvm/llvm-project/commit/70496276d0f441999b61e84ca22e59d61fa43582
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/MarkLive.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/Writer.cpp
M lld/docs/ReleaseNotes.rst
M lld/docs/ld.lld.1
M lld/test/ELF/retain-symbols-file.s
M lld/test/ELF/version-script-warn.s
Log Message:
-----------
[ELF] --retain-symbols-file: keep listed symbols in .symtab, not .dynsym (#209063)
Commit c0fc25307143dd06c12fb2f5ebdb1dade7290ccf (2017) implements
--retain-symbols-file with symbol version machinery
`{local: *; global: listed;}`, which removes unlisted symbols from
.dynsym and leaves .symtab untouched. GNU ld does the opposite: it keeps
only the listed symbols in .symtab and does not touch .dynsym.
Reuse the --discard-{locals,all} mechanism to reimplement the feature,
matching GNU ld.
Use --export-dynamic-symbol or a version script to control .dynsym.
Extend `markUsedSymbols` to mark referenced globals as well, so
--emit-relocs/-r keep a valid symbol index.
Fix #91055
Commit: e8e88dbde96a75ffe0e8bf10ea9481a053292421
https://github.com/llvm/llvm-project/commit/e8e88dbde96a75ffe0e8bf10ea9481a053292421
Author: Harlen Batagelo <hbatagelo at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaTemplateInstantiate.cpp
A clang/test/SemaTemplate/GH195988.cpp
Log Message:
-----------
[clang][sema] Fix crash on class template instantiation when a member variable partial specialization has an invalid primary template (#202006)
Fixes #195988.
For the root cause, consider this reproducer:
https://godbolt.org/z/6jTnvocs4
```cpp
template <typename> struct A {
template <typename U> static B x; // unknown type name 'B'
template <typename U> static int x<U*>;
};
A<int> a;
```
During the instantiation of `A<int>`, the variable template `x` is
skipped because it was marked as an invalid declaration due to the
unknown type `B`. When the partial specialization `x<U*>` is visited
next, the lookup for `x` finds nothing and triggers the assertion:
https://github.com/llvm/llvm-project/blob/2433b06e6dbe3ef015a226620d207a45f7b98c7c/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp#L2538
Fix by instantiating invalid variable templates using the `int` fallback
instead of skipping them.
Commit: aae01919171394ed4a4bf6b2fb82cc0d70561994
https://github.com/llvm/llvm-project/commit/aae01919171394ed4a4bf6b2fb82cc0d70561994
Author: Petr Hosek <phosek at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/src/include/overridable_function.h
Log Message:
-----------
[libcxx] Rename __libcpp_launder to __launder_function_pointer (#209320)
This addresses post-commit feedback raised in #208330.
Commit: 6c6ecb376a940d16e17dae2d40dc076466898860
https://github.com/llvm/llvm-project/commit/6c6ecb376a940d16e17dae2d40dc076466898860
Author: Petr Hosek <phosek at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/src/include/overridable_function.h
M libcxx/src/new.cpp
M libcxxabi/src/stdlib_new_delete.cpp
Log Message:
-----------
[libcxx][libcxxabi] Remove OVERRIDABLE_FUNCTION macro (#209323)
This is no longer needed, we can just use [[gnu::weak]] attribute.
Commit: 9a342c137d4ed8c6d4571ebc5a62f22aa9642278
https://github.com/llvm/llvm-project/commit/9a342c137d4ed8c6d4571ebc5a62f22aa9642278
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/early-exit-live-out.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-prune-vf.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-access-wide-stride.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
M llvm/test/Transforms/LoopVectorize/VPlan/RISCV/expand-scev.ll
Log Message:
-----------
[VPlan] Use VPSCEVExpander in convertToStridedAccesses (#208939)
Expand SCEVs to VPInstructions, falling back to expanding to IR
instructions. Expanding to VPInstructions has the advantage that the
expansion would be made visible to the VPlan optimization pipeline,
allowing existing simplifications to kick in.
Commit: 5514c1eff5fe52d0bcc2c017c0210bd31fd0bf32
https://github.com/llvm/llvm-project/commit/5514c1eff5fe52d0bcc2c017c0210bd31fd0bf32
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/UseScopedLockCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/use-scoped-lock.rst
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-scoped-lock-warn-on-single-locks-false.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-scoped-lock.cpp
Log Message:
-----------
[clang-tidy] Flag consecutive scoped_locks in use-scoped-lock (#209272)
Fixes https://github.com/llvm/llvm-project/issues/209112.
Commit: 94b7d2b4d8d7c8cfa2d09a6aa2bb1d7df81d047c
https://github.com/llvm/llvm-project/commit/94b7d2b4d8d7c8cfa2d09a6aa2bb1d7df81d047c
Author: gtrong <40399865+gtrong at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Parse/ParseDecl.cpp
M clang/test/Parser/cxx-default-args.cpp
Log Message:
-----------
[Clang] Fix error recovery for default arguments (#208868)
Fixes #205718
### Description
This PR fixes an issue where Clang incorrectly skips the creation of a
parameter when an error occurs in a default argument that involves a GNU
statement expression (`({ ... })`).
Previously, if the default expression evaluation failed within a
statement expression, the error recovery was not handled properly,
leading to the parameter being dropped. This fix ensures that the
parameter is correctly created and error recovery proceeds as expected.
### Testing
Added/Updated test cases in
`clang/test/SemaCXX/default-arg-error-recovery.cpp` to cover invalid
default arguments inside statement expressions.
Commit: 9144e3292c6caaeed2ad16b6ed2a2eba620c0257
https://github.com/llvm/llvm-project/commit/9144e3292c6caaeed2ad16b6ed2a2eba620c0257
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/include/clang/Basic/AArch64CodeGenUtils.h
M clang/include/clang/Basic/arm_neon.td
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
M clang/test/Sema/aarch64-neon-target.c
M clang/test/Sema/aarch64-neon-without-target-feature.cpp
Log Message:
-----------
[AArch64][llvm][clang] Rename 9.7 ACLE vmmlaq_f16_f16 to vmmlaq_f16 (#209242)
Rename Armv9.7 ACLE intrinsic `vmmlaq_f16_f16` to `vmmlaq_f16`
as it matches convention better.
See https://github.com/ARM-software/acle/pull/443 for the ACLE change.
Commit: 25ee70e271dd60978f8bfded54198dbe72009847
https://github.com/llvm/llvm-project/commit/25ee70e271dd60978f8bfded54198dbe72009847
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
Log Message:
-----------
[WebAssembly] Fix operands in relaxed_pmin/relaxed_pmax pattern (#209398)
After 56e62e539eb65ebe4ec9fc6de0328fea21ae86fd these should be
operands 0 and 1 instead of 1 and 2.
Also add an explicit SIMD128 check when marking these as legal.
It works fine without it (presumably because the types just aren't
legal), but this makes it more explicit when the operations are
available.
Commit: 95349af763cfc48858fdd40058bd46a11779deb2
https://github.com/llvm/llvm-project/commit/95349af763cfc48858fdd40058bd46a11779deb2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
A llvm/test/MC/AMDGPU/amdgcn-target-directive-conflict.s
M llvm/test/MC/AMDGPU/amdgcn-target-directive-subarch-cpu-field.s
M llvm/test/MC/AMDGPU/amdgcn-target-directive-triple-env.s
M llvm/test/MC/AMDGPU/hsa-diag-v4.s
M llvm/test/MC/AMDGPU/hsa-exp.s
M llvm/test/MC/AMDGPU/hsa-gfx12-v4.s
M llvm/test/MC/AMDGPU/hsa-gfx13-v4.s
M llvm/test/MC/AMDGPU/hsa-tg-split.s
M llvm/test/MC/AMDGPU/hsa-v4.s
M llvm/test/MC/AMDGPU/hsa-v5-uses-dynamic-stack.s
M llvm/test/MC/AMDGPU/isa-version-hsa.s
M llvm/test/MC/AMDGPU/isa-version-pal.s
M llvm/test/MC/AMDGPU/isa-version-unk.s
M llvm/test/MC/ELF/AMDGPU/cfi.s
Log Message:
-----------
AMDGPU: Defer validation of target assembler directives (#207812)
Stop immediately emitting the .amdgcn_target directive from the command
line's target, and wait until any target directives in the file are
encountered. This requires lazily emitting the target directive to before the
point anything is to be emitted. Weaken the validation that the xnack and
sramecc settings match the command line's state, and take the mode from the
target directive
(mutating the tracked target ID state). Liberalize the triple check so that after
#206480, old assembly files will not break on new assembler invocations.
For some reason we have 2 different assembler directives that indicate
the target, .amdgcn_target for amdhsa and .amd_amdgpu_isa for amdpal.
Previously, we would take the target from the command line and then error if the
directive did not exactly match. In order to move away from depending on the xnack
and sramecc subtarget features, start treating the directives as a change of
target, similar to ARM's .cpu and .arch directives.
Both .amdgcn_target and .amd_amdgpu_isa encode full triples, but unlike
.amdgcn_target, the PAL directive does not include xnack or sramecc.
Ideally we would introduce new independent directives for these.
Co-Authored-By: Claude Opus 4.6 <noreply at anthropic.com>
Commit: 2d401082440f16d36a42e5b55c2992f8bab4cb5f
https://github.com/llvm/llvm-project/commit/2d401082440f16d36a42e5b55c2992f8bab4cb5f
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
[GitHub] Install libedit, libxml2 and liblzma to be used in Linux LLDB builds (#209129)
In #188049 we missed some test failures because GitHub CI does not have
libxml2 installed. I checked the logs and found a couple of other things
missing.
In this change I'm adding to the Linux container:
* libedit
* libxml2
* liblzma
I am not adding ncurses because this would enable text user interface
tests that are often unstable. They do run post-commit, and don't change
that often anyway.
I am not adding Lua or TreeSitter because they are more obscure and are
tested somewhere post-commit (in Green Dragon I think).
Commit: f195f4d45dc253192270a4be3f806f2913a071d1
https://github.com/llvm/llvm-project/commit/f195f4d45dc253192270a4be3f806f2913a071d1
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/bindings/interface/SBTargetDocstrings.i
M lldb/docs/use/tutorial.md
M lldb/source/Breakpoint/Watchpoint.cpp
M lldb/test/Shell/Register/x86-db-read.test
Log Message:
-----------
[lldb] Add comma separator in watchpoint description (#209176)
I find it easier to read this way, especially the last "state = enabled type = m" which looks like "enabled type = m" at a glance:
Watchpoint 1: addr = 0xaaaaaaab1018 size = 20 state = enabled type = m
With commas:
Watchpoint 1: addr = 0xaaaaaaab1018, size = 20, state = enabled, type = m
Code breakpoints include commas already:
1: name = 'main', locations = 1, resolved = 1, hit count = 1
1.1: where = test.o`main at test.c:13:15, address = 0x0000aaaaaaaa0714, resolved, hit count = 1
Used the regex "Watchpoint [0-9]+:" to find tests and docs that needed
updating.
Commit: dad3e30521b596cade7e3c516909657c44ed2840
https://github.com/llvm/llvm-project/commit/dad3e30521b596cade7e3c516909657c44ed2840
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/Rematerializer.h
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/unittests/CodeGen/RematerializerTest.cpp
Log Message:
-----------
[CodeGen] Fix incorrect rematerialization rollback order (#197576)
This fixes an issue in the rematerializer's rollbacker wherein adjacent
MIs that were deleted through rematerializations would
sometimes---depending on the exact order in which they were
deleted---not be re-created in their original pre-rematerialization
order. While this does not impact correctness (i.e., use-def relations
are always honored), this goes against the rollbacker's intent to
re-create the MIR exactly as it was pre-rematerializations (up to slot
index changes).
Commit: 5566c87df36cacb1f006535476108dc5e4c8c18f
https://github.com/llvm/llvm-project/commit/5566c87df36cacb1f006535476108dc5e4c8c18f
Author: Victor Campos <victor.campos at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGen/builtins.c
Log Message:
-----------
[Clang] Fix boolean vector bit counting on big-endian targets (#209146)
`__builtin_ctzg` and `__builtin_clzg` (count leading/trailing zeroes)
can accept boolean vectors as arguments. In this case, they operate in
logical vector lane order. However, `EmitBitCountExpr`, used to generate
the argument to those builtins, bitcasts boolean vectors directly to
integer bitfields, whose bit order is reversed on big-endian targets.
This caused libc's SIMD `find_first_set` and `find_last_set` helpers to
count lanes from the wrong end in big-endian mode. But the issue was
general and could affect any user.
This patch normalizes the integer representation with `llvm.bitreverse`
on big-endian targets before emitting bit-count intrinsics. On top of
that, the codegen test has been refactored to run on more targets and to
cover big-endian mode as well.
As a side effect of this change, and because of the way the code is
structured, the bit reverse operation also happens for
`__builtin_popcountg`. For this intrinsic, the integer bitfield's bit
order doesn't matter because it simply counts set bits. However, to make
this change only affect the count leading/trailing intrinsics would be
too intrusive, and in any case, with optimizations enabled, the
pointless bit reversing operation on popcount is optimized away. This
behaviour is covered in the test.
Assisted-by: codex. It was used for the test, not the implementation.
Commit: afac9463c13d6e44f287ee693309497cb79e1e10
https://github.com/llvm/llvm-project/commit/afac9463c13d6e44f287ee693309497cb79e1e10
Author: Mateusz Chudyk <mateusz.chudyk at intel.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
Log Message:
-----------
[GlobalISel] Fix crash in matchCombineInsertVecElts with INLINEASM-de… (#208225)
…fined base
matchCombineInsertVecElts walks the G_INSERT_VECTOR_ELT chain by
following operand 0 of the source-defining instruction. When the base
vector is defined by INLINEASM, operand 0 is the asm string (not a
register), so calling getReg() triggers an assertion:
Assertion `isReg() && "This is not a register operand!"' failed.
Fix by using the mi_match overload that takes a MachineInstr instead of
a Register, which checks the instruction opcode before accessing any
operands.
Commit: 7401694a38d9126bc910d3edf7e04331a66befa4
https://github.com/llvm/llvm-project/commit/7401694a38d9126bc910d3edf7e04331a66befa4
Author: YaFan Tao <765370813 at qq.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
A llvm/test/CodeGen/AMDGPU/atomic_optimizations_dpp_lds_expected_active_lanes.ll
A llvm/test/Verifier/amdgpu-expected-active-lanes.ll
Log Message:
-----------
[AMDGPU] Add threshold for DPP atomic optimizer on LDS atomics (#186762)
Add amdgpu.expected.active.lane metadata which can be applied to operations by a
compiler front-end. Do not apply the DPP atomic optimizer to LDS atomics where
less than five active lanes are expected.
This is an empirically derived threshold based on GFX11 and GFX12 testing.
---------
Co-authored-by: YaFan <YaFan.Tao at amd.com>
Commit: c9610acc5b1d4f49d197a4c8816fb688736963ae
https://github.com/llvm/llvm-project/commit/c9610acc5b1d4f49d197a4c8816fb688736963ae
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYTargetStreamer.h
Log Message:
-----------
[CSKY] Fix build without PCH (#209405)
Commit: 00bf3d6cf36d1c9a910d470814a76a4be1ab1634
https://github.com/llvm/llvm-project/commit/00bf3d6cf36d1c9a910d470814a76a4be1ab1634
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/clang-tools-extra/clang-doc/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 1bd4601 (#209377)
This fixes 1bd46015ea4e842091109cd2a491c55c0b455330.
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=1bd46015ea4e842091109cd2a491c55c0b455330
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 7c151447bc8abceefa3be9e5f1b27b83803d77af
https://github.com/llvm/llvm-project/commit/7c151447bc8abceefa3be9e5f1b27b83803d77af
Author: Folkert de Vries <folkert at folkertdev.nl>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
R llvm/test/CodeGen/X86/pr142937.ll
A llvm/test/CodeGen/X86/type-tests-must-be-lowered.ll
Log Message:
-----------
[SDAG] emit error when `llvm.type.checked.load` is not lowered (#208058)
Fixes https://github.com/llvm/llvm-project/issues/164663
In rust we can enable devirtualization and LTO on a build that actually
builds a library and hence LTO does not really run. That means typed
loads are emitted, but they are not lowered (or cleaned up), which made
us hit an ICE. Giving a slightly better error message, analogous to the
existing one for `Intrinsic::type_test`, seems nice.
I'm putting this together based on
https://github.com/llvm/llvm-project/pull/179249 and
https://github.com/llvm/llvm-project/issues/164663#issuecomment-3433581033.
Commit: a31c941fa7fd9eaea855cff3bb40347c0d22243d
https://github.com/llvm/llvm-project/commit/a31c941fa7fd9eaea855cff3bb40347c0d22243d
Author: David Stuttard <david.stuttard at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
A llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-hsa.ll
A llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-rel32.mir
A llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr.ll
Log Message:
-----------
[AMDGPU] Support global address in V/S_MOV_B64 lowering (#203527)
Hit an issue where V_MOV_B64_PSEUDO had a global, which wasn't
previously handled.
Added support for this, and also for the S_MOV_B64_IMM_PSEUDO to make it
symmetrical.
Claude has been used for this commit, primarily assisting creating a
test.
Commit: d21d602d65bc5f6494da679d004b764e47347b49
https://github.com/llvm/llvm-project/commit/d21d602d65bc5f6494da679d004b764e47347b49
Author: Vikram Hegde <Vikram.Hegde at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/Analysis/ModuleSummaryAnalysis.h
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/Analysis/StackSafetyAnalysis.cpp
M llvm/lib/Passes/PassRegistry.def
Log Message:
-----------
[NPM] Port ImmutableModuleSummaryAnalysis to NPM (#203510)
Required in LTO pipelines
Commit: d4568c9fd15235bd4545a5c57f23bfcb42673f39
https://github.com/llvm/llvm-project/commit/d4568c9fd15235bd4545a5c57f23bfcb42673f39
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
Log Message:
-----------
[mlir][SPIR-V] Collapse TanPattern/TanhPattern into DirectConversionPattern (#203830)
Commit: 6a1f23ab1333ced760666282c23a7afd2db2719e
https://github.com/llvm/llvm-project/commit/6a1f23ab1333ced760666282c23a7afd2db2719e
Author: Vikram Hegde <Vikram.Hegde at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/MachineBlockPlacement.h
M llvm/include/llvm/CodeGen/RegisterCoalescerPass.h
M llvm/include/llvm/CodeGen/RenameIndependentSubregs.h
M llvm/include/llvm/CodeGen/TwoAddressInstructionPass.h
M llvm/include/llvm/CodeGen/UnreachableBlockElim.h
M llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h
M llvm/include/llvm/Transforms/Utils/UnifyLoopExits.h
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.h
M llvm/lib/Target/AMDGPU/GCNNSAReassign.h
M llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
M llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h
M llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h
M llvm/lib/Target/AMDGPU/SILowerControlFlow.h
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
M llvm/lib/Target/AMDGPU/SILowerWWMCopies.h
M llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
Log Message:
-----------
[NPM] Make few more passes required (#203511)
essentially a port of https://github.com/llvm/llvm-project/pull/148115.
matches legacy behaviour. MachineBlockPlacement is made optional since
it is optional in legacy as well. not sure if there was any reason to
make it required in NPM.
Commit: 37d488f15991d8c65666834a7aed14000d1393fa
https://github.com/llvm/llvm-project/commit/37d488f15991d8c65666834a7aed14000d1393fa
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/induction-condition-in-loop-exit.ll
M llvm/test/Transforms/ConstraintElimination/loops-header-tested-pointer-cmps.ll
Log Message:
-----------
[ConstraintElim] Look through post-increment in header EQ/NE compare. (#209199)
Extend the header-controlled induction handling to look through a
post-increment `PN + C` (constant C) on the compared value
For now, the new path is limited to deriving unsigned facts.
Alive2 Proof: https://alive2.llvm.org/ce/z/DCNeSr
PR: https://github.com/llvm/llvm-project/pull/209199
Commit: 922b1a9da0a16e9df23c1a91203cf37c24d5c26d
https://github.com/llvm/llvm-project/commit/922b1a9da0a16e9df23c1a91203cf37c24d5c26d
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/cmake/modules/FindDIASDK.cmake
Log Message:
-----------
Revert "[cmake] Fix VSINSTALLDIR check in FindDIASDK module (#208524)" (#209137)
This reverts commit 4c5e15667fe384e434961fe44cf5950dc309fdf1.
https://github.com/llvm/llvm-project/pull/208524 fixed a flag which
enabled testing with the DIA SDK. This broke all Windows build bots,
because the SDK is not available in the PATH.
Commit: add1925e5ee942794d7d6e8b4d65b32c959d472a
https://github.com/llvm/llvm-project/commit/add1925e5ee942794d7d6e8b4d65b32c959d472a
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] NFCI: Simplify LowerVectorFP_TO_INT_SAT (part 2) (#207199)
This simplifies the logic a bit more, such that the flow of the lowering
is as follows:
* Try to promote if necessary (fp16/bf16 types or src < dst)
* Try to handle natively (satwidth == srcwidth == dstwidth)
* Otherwise use min/max + truncate.
Commit: dbbd4e0de70b62c2e05d8a650ddcdff954ef8d0f
https://github.com/llvm/llvm-project/commit/dbbd4e0de70b62c2e05d8a650ddcdff954ef8d0f
Author: Ralf Jung <post at ralfj.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/docs/LangRef.md
Log Message:
-----------
[LangRef] select: describe behavior for undef and poison (#208724)
The poison semantics is based on
https://llvm.org/docs/UndefinedBehavior.html#propagation-of-poison-through-select.
IMO this definitely should appear in the "semantics" section of the
`select` instruction. If this isn't part of the `select` semantics I
don't know what is.
The undef semantics are based on what Alive does.
Commit: 8c75e8018d52ead8f97648b7b279671b89c59fa0
https://github.com/llvm/llvm-project/commit/8c75e8018d52ead8f97648b7b279671b89c59fa0
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon/fullfp16.c
M clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
Log Message:
-----------
[CIR][AArc64] Add lowering for fp16 intrinsics (multiply extended) (#209222)
This PR adds lowering for the following intrinsic groups:
* https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#multiply-extended-1
It also moves the corresponding tests from:
* clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
to:
* clang/test/CodeGen/AArch64/neon/fullfp16.c
The lowering follows the existing implementation in
CodeGen/TargetBuiltins/ARM.cpp.
Commit: 19401e09c063367a3503ae6cc1a47babfa95f243
https://github.com/llvm/llvm-project/commit/19401e09c063367a3503ae6cc1a47babfa95f243
Author: Andrew Ng <andrew.ng at sony.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/Format/CMakeLists.txt
Log Message:
-----------
[clang-format] Fix `check-format-depends` CMake for Windows (#209205)
Add `find_program` for `touch`. Convert found program paths to native
form and use these paths in the command invocation.
Commit: aa5960600ac38fcd923e69777bad1293f56658d7
https://github.com/llvm/llvm-project/commit/aa5960600ac38fcd923e69777bad1293f56658d7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Object/OffloadBinary.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
Revert "clang-linker-wrapper: Use AMDGPU::TargetID for device-image compatibility" (#209407)
Reverts llvm/llvm-project#209135
This shouldn't be doing logical linking compatibility
Commit: f6393d657271b632de22cdfeaff35cfb3d45bf92
https://github.com/llvm/llvm-project/commit/f6393d657271b632de22cdfeaff35cfb3d45bf92
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/docs/CommandGuide/lit.rst
M llvm/utils/lit/lit/cl_arguments.py
M llvm/utils/lit/lit/main.py
M llvm/utils/lit/lit/util.py
A llvm/utils/lit/tests/Inputs/time-tests/b.txt
A llvm/utils/lit/tests/Inputs/time-tests/c.txt
M llvm/utils/lit/tests/time-tests.py
Log Message:
-----------
[lit] Add configurable slowest-test limit to --time-tests (#208444)
The PR parameterizes `--time-tests`, which was hardcoded to 20 tests. We
now allow `--time-tests=N` or `--time-tests=all`.
The changes still honor the original behavior of `--time-tests`. The
parsing logic could be slightly simpler if `--time-tests` would always
require an explicit number of tests (like `-j`), but that would be a CLI
breaking change.
Commit: 1a8e5b6f594926adaaa0417543773108b7fd737d
https://github.com/llvm/llvm-project/commit/1a8e5b6f594926adaaa0417543773108b7fd737d
Author: Xiaomeng Zhang <zhangxiaomeng at hygon.cn>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86.td
M llvm/test/CodeGen/X86/slow-unaligned-mem.ll
M llvm/test/CodeGen/X86/x86-prefer-no-gather-no-scatter.ll
A llvm/test/Transforms/LoopVectorize/X86/x86-prefer-no-gather.ll
A llvm/test/Transforms/LoopVectorize/X86/x86-prefer-no-scatter.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-abs.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-saddo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-ssat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-uaddo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-usat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-div.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fix.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-mul-smulo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-mul-umulo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-mul.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-scmp.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-smax.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-smin.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-ssat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-ssubo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-usat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-usubo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-ucmp.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-umax.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-umin.ll
M llvm/test/Transforms/SLPVectorizer/X86/fabs.ll
M llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll
M llvm/test/Transforms/SLPVectorizer/X86/fma.ll
M llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
M llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
M llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
M llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
M llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
M llvm/test/Transforms/SLPVectorizer/X86/fround.ll
M llvm/test/Transforms/SLPVectorizer/X86/shift-ashr.ll
M llvm/test/Transforms/SLPVectorizer/X86/shift-lshr.ll
M llvm/test/Transforms/SLPVectorizer/X86/shift-shl.ll
M llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
M llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
A llvm/test/Transforms/SLPVectorizer/X86/x86-prefer-no-gather.ll
Log Message:
-----------
[X86] Add tuning features for Hygon C86-4G-M7 (#205992)
Add TuningPreferNoGather. TuningPreferNoScatter and TuningPrefer256Bit to C864GM7Tuning.
This will improve the performance of the C86-4G-M7.
Commit: 79acf12724942b687b7c777e1dc46dd56ca4d287
https://github.com/llvm/llvm-project/commit/79acf12724942b687b7c777e1dc46dd56ca4d287
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/test/Driver/msvc-link.c
Log Message:
-----------
[clang] Use lld-link by default when -marm64x is specified (#209324)
ARM64X hybrid object files require lld-link, as it is currently the only
linker that supports them.
Commit: f2ada6d997fe4f4854f15f2c880dd740cd2ebb8a
https://github.com/llvm/llvm-project/commit/f2ada6d997fe4f4854f15f2c880dd740cd2ebb8a
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-unroll.ll
Log Message:
-----------
[VPlan] Add test for convertToStridedAccess flag issue. NFC (#209425)
>From the comment in
https://github.com/llvm/llvm-project/pull/209168/changes#r3574524959
Commit: b3f5986138f2f6a65072b6822892afa5d8859cf7
https://github.com/llvm/llvm-project/commit/b3f5986138f2f6a65072b6822892afa5d8859cf7
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
Log Message:
-----------
[clang][CIR][AArch64] Add lowering for conversion intrinsics (#209252)
This PR adds lowering for intrinsic from the following groups:
* https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions
It continues the work started in #190961, #193273 and #199990. This PR
implements the remaining conversions truncating to zero:
* vcvtd_s32_f64
* vcvtd_s64_f64
* vcvtd_u32_f64
* vcvtd_u64_f64
The corresponding tests are moved from:
* clang/test/CodeGen/AArch64/
to:
* clang/test/CodeGen/AArch64/neon/
The lowering follows the existing implementation in
CodeGen/TargetBuiltins/ARM.cpp.
Commit: 95e647c8aa180f946c83d1e6f361989442206f52
https://github.com/llvm/llvm-project/commit/95e647c8aa180f946c83d1e6f361989442206f52
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/intrinsic-amdgcn-s-alloc-vgpr.ll
M llvm/test/CodeGen/AMDGPU/invalid-cast-load-i1.ll
M llvm/test/CodeGen/AMDGPU/invalid-hidden-kernarg-in-kernel-signature.ll
M llvm/test/CodeGen/AMDGPU/invariant-image-load.ll
M llvm/test/CodeGen/AMDGPU/ipra.ll
M llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/issue121601-combine-concat-vectors-assumes-f16.ll
M llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
M llvm/test/CodeGen/AMDGPU/issue139317-bad-opsel-reg-sequence-fold.ll
M llvm/test/CodeGen/AMDGPU/issue153808-extract-subvector-legalize.ll
M llvm/test/CodeGen/AMDGPU/issue176966-extend-vector-inreg.ll
M llvm/test/CodeGen/AMDGPU/issue48473.mir
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
M llvm/test/CodeGen/AMDGPU/issue98474-assigned-physreg-interference.mir
M llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll
M llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir
M llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/kernarg-size.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
M llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/kill-true-in-return-block.ll
M llvm/test/CodeGen/AMDGPU/known-never-nan.ll
M llvm/test/CodeGen/AMDGPU/known-never-snan.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll
M llvm/test/CodeGen/AMDGPU/large-avgpr-assign-last.mir
M llvm/test/CodeGen/AMDGPU/large-constant-initializer.ll
M llvm/test/CodeGen/AMDGPU/large-phi-search.ll
M llvm/test/CodeGen/AMDGPU/large-work-group-promote-alloca.ll
M llvm/test/CodeGen/AMDGPU/lds-barrier-memoperand.ll
M llvm/test/CodeGen/AMDGPU/lds-bounds.ll
M llvm/test/CodeGen/AMDGPU/lds-branch-vmem-hazard.mir
M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx11.mir
M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx12.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-hazards.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll
M llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll
M llvm/test/CodeGen/AMDGPU/lds-initializer.ll
M llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-agpr.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-callgraph.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-named-barrier.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-typeid.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-named-barrier.ll
M llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/lds-mixed-absolute-addresses-unused.ll
M llvm/test/CodeGen/AMDGPU/lds-mixed-absolute-dynlds.ll
M llvm/test/CodeGen/AMDGPU/lds-no-realign-allocated-variables.ll
M llvm/test/CodeGen/AMDGPU/lds-reject-anonymous-kernels.ll
M llvm/test/CodeGen/AMDGPU/lds-reject-mixed-absolute-addresses.ll
M llvm/test/CodeGen/AMDGPU/lds-relocs.ll
M llvm/test/CodeGen/AMDGPU/lds-run-twice-absolute-md.ll
M llvm/test/CodeGen/AMDGPU/lds-run-twice.ll
M llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx950.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.dead.mir
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-fp-load-invariant.ll
M llvm/test/CodeGen/AMDGPU/legalize-soffset-mbuf.ll
M llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
M llvm/test/CodeGen/AMDGPU/licm-valu.mir
M llvm/test/CodeGen/AMDGPU/licm-wwm.mir
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (17) (#209120)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: db8ea12c3918fe10912298b7acfd21269d03cab2
https://github.com/llvm/llvm-project/commit/db8ea12c3918fe10912298b7acfd21269d03cab2
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt-c/Logging.h
M orc-rt/test/regression/logging/os_log/delivery.test
M orc-rt/test/tools/orc-rt-log-check.cpp
M orc-rt/test/unit/LoggingTest.cpp
Log Message:
-----------
[orc-rt] Add ORC_RT_LOG_PUB_S for logging runtime strings. (#209401)
ORC_RT_LOG requires its format to be a string literal, so the specifier
for a runtime C string cannot be written at the call site by hand -- and
it differs by backend: os_log redacts a plain "%s" argument to <private>
unless it carries a "%{public}s" annotation, which libc's printf does
not understand.
Add ORC_RT_LOG_PUB_S, which expands to "%{public}s" on the os_log
backend and plain "%s" everywhere else. Call sites compose it into the
format by literal adjacency, so the format stays a single literal on
every backend:
ORC_RT_LOG(Info, General, "resolved " ORC_RT_LOG_PUB_S, SymbolName);
LoggingTest covers the compile/format-check path (including os_log
builds); the orc-rt-log-check delivery test confirms os_log publishes
the string rather than redacting it to <private>.
Commit: e793eee71340131b7dcbfd5fce2edde84ab4ad5a
https://github.com/llvm/llvm-project/commit/e793eee71340131b7dcbfd5fce2edde84ab4ad5a
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
Log Message:
-----------
[ORC] Add LLLazyJIT destructor with call to endSession. (#209399)
Add an LLLazyJIT destructor with a call to ExecutionSession::endSession.
This ensures that the ExecutionSession's TaskDispatcher is shut down
(and in-flight tasks completed) before LLLazyJIT class members are
destroyed. Failure to do this could lead to use-after-free errors when
using thread-based task dispatch. This was likely the cause of flakiness
in test/ExecutionEngine/OrcLazy/multiple-compile-threads-basic.ll.
rdar://181982834
Commit: 2a6cc991cc691f2cc666483c417f01675321ce2c
https://github.com/llvm/llvm-project/commit/2a6cc991cc691f2cc666483c417f01675321ce2c
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/SystemZ/SystemZInstrVector.td
M llvm/test/CodeGen/SystemZ/vec-max-05.ll
M llvm/test/CodeGen/SystemZ/vec-max-min-zerosplat.ll
M llvm/test/CodeGen/SystemZ/vec-min-05.ll
Log Message:
-----------
[SystemZ] Support pseudo fmin/fmax (#209178)
s390x supports the pseudo fmin/fmax operations (x < y ? x : y and x > y
? x : y) as mode 2 in vfmin/vfmax. As such, we should lower
PSEUDO_FMIN/FMAX to those. Also disable formation of minnum/maxnum in
SDAGBuilder, as it's not useful if we have native support for this
operation.
Commit: a9d295d615a81574eabb3645ed5d2eb5a5f4efd9
https://github.com/llvm/llvm-project/commit/a9d295d615a81574eabb3645ed5d2eb5a5f4efd9
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolutionDivision.cpp
Log Message:
-----------
[SCEVDivision] Add assertion to check operand types match (NFCI) (#204146)
In ScalarEvolutionDivision.h, the `SCEVDivision::divide` operation is
defined as follows:
```
/// Computes the Quotient and Remainder of the division of Numerator by
/// Denominator. We are not actually performing the division here. Instead, we
/// are trying to find SCEV expressions Quotient and Remainder that satisfy:
///
/// Numerator = Denominator * Quotient + Remainder
```
Therefore, I believe it makes sense to enforce that the types of
`Numerator` and `Denominator` are the same.
This patch adds an assertion to verify that restriction.
Commit: 96dcb03caa310852329c4e7ad1d678c024c6ed94
https://github.com/llvm/llvm-project/commit/96dcb03caa310852329c4e7ad1d678c024c6ed94
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
Log Message:
-----------
[NFC][LLVM][CodeGen][SVE] Strengthen the isel definition of AArch64setcc_z. (#209170)
Making all operand types derive from the compare's LHS reduces the
number of types an isel rule must specify, which improves readability.
Commit: 16094a86a6cfe79fa50dcca39b539ab6465b8ac0
https://github.com/llvm/llvm-project/commit/16094a86a6cfe79fa50dcca39b539ab6465b8ac0
Author: Srinivasa Ravi <srinivasar at nvidia.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPUOps.td
M mlir/lib/Conversion/NVGPUToNVVM/CMakeLists.txt
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
M mlir/lib/Dialect/NVGPU/IR/NVGPUDialect.cpp
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-extf-large.mlir
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-extf.mlir
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-truncf-large.mlir
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-truncf.mlir
A mlir/test/Dialect/NVGPU/nvgpu-extf-invalid.mlir
A mlir/test/Dialect/NVGPU/nvgpu-truncf-invalid.mlir
Log Message:
-----------
[MLIR][NVGPU] Add truncf and extf Ops (#199700)
This change adds the `extf` and `truncf` ops to the NVGPU dialect to
support floating-point conversion operations.
These ops support scalar and vector inputs and lower to the corresponding
NVVM ops after padding and chunking the input into `i32` registers.
Commit: c311e7b3d68cb88487c4dbc4029d101e4c19c908
https://github.com/llvm/llvm-project/commit/c311e7b3d68cb88487c4dbc4029d101e4c19c908
Author: Iurii Khosoi <aadaa_fgtaa at pm.me>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/test/CodeGen/X86/bitcnt-false-dep.ll
A llvm/test/CodeGen/X86/bls-false-dep.ll
A llvm/test/CodeGen/X86/compress-false-deps.ll
A llvm/test/CodeGen/X86/expand-false-deps.ll
Log Message:
-----------
[X86] Break false dependencies on Zen 4 and 5 (#206849) (#207079)
Some variants of Zen 5 microarchitectures have a false dependency on the
output register of tzcnt, blsr, blsi and blsmsk instructions. This PR
splits existing tuning feature for the false dependency of tzcnt/lzcnt
and adds a new tuning feature for bls*. The tzcnt and bls* tunings are
enabled by default for Zen 5.
Furthermore, at least some variants of Zen 4 and 5 microarchitectures
appear to have a false dependency on the output register of zero-masked
compress and expand instructions. Tested on Ryzen 9 9950X, Ryzen 9 7950X
and Ryzen AI 7 350, also apparent in uops.info data from Ryzen 5 7600X
and Ryzen 7 9700X (see #206849). This PR adds a new tuning feature for
the false dependency of compress/expand. The tuning is enabled for Zen 4
and Zen 5.
Fixes #206849
Commit: 7de5af16e0e72d6325d3dd63ee619a1cb3bce783
https://github.com/llvm/llvm-project/commit/7de5af16e0e72d6325d3dd63ee619a1cb3bce783
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/test/API/tools/lldb-dap/stackTrace/TestDAP_stackTrace.py
M lldb/test/API/tools/lldb-dap/stackTraceCompilerGeneratedCode/TestDAP_stackTraceCompilerGeneratedCode.py
M lldb/test/API/tools/lldb-dap/stackTraceDisassemblyDisplay/TestDAP_stackTraceDisassemblyDisplay.py
M lldb/test/API/tools/lldb-dap/stackTraceMissingFunctionName/TestDAP_stackTraceMissingFunctionName.py
M lldb/test/API/tools/lldb-dap/stackTraceMissingModule/TestDAP_stackTraceMissingModule.py
Log Message:
-----------
[lldb-dap] Migrate lldb-dap stackTrace tests (#209236)
Migrate
- TestDAP_stackTrace
- TestDAP_stackTraceDisassemblyDisplay
- TestDAP_stackTraceDisassemblyDisplay
- TestDAP_stackTraceMissingFunctionName
- TestDAP_stackTraceMissingModule
Commit: c1ae9eabc8b55aa4e2a06efacca6003ccecf6249
https://github.com/llvm/llvm-project/commit/c1ae9eabc8b55aa4e2a06efacca6003ccecf6249
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] Fixup possibly unused variable warning after #207199 (#209418)
Using [[maybe_unused]] as the variable is only used in asserts which
results in a diagnostic for no-assert builds.
Commit: 64de40e5cbfba35eb4118254326889dabb04bb6c
https://github.com/llvm/llvm-project/commit/64de40e5cbfba35eb4118254326889dabb04bb6c
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/Rematerializer.h
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/unittests/CodeGen/RematerializerTest.cpp
Log Message:
-----------
[CodeGen][AMDGPU] Prepare rematerializer for multi-def remat support (NFC) (#197579)
This makes some NFCs to the rematerializer before adding initial support
for rematerializing registers with multiple defs. The main change is
that, in the representation of (un)rematerializable register
dependencies, we drop references to machine operand indices which lose
meaning in the multi-def case.
Other minor changes listed below.
- Removal of `DefRegion` argument to `Rematerializer::recreateReg`.
Registers are always re-created in their original region so there is no
need to set their region again.
- Removal of `InsertPos` unused argument to
`Rematerializer::postRematerialization`.
- Refactor of how AMDGPU's scheduler checks whether a given register is
rematerializable.
Commit: 9582f71a3b5f71e871bee0062e641f3587e0ae23
https://github.com/llvm/llvm-project/commit/9582f71a3b5f71e871bee0062e641f3587e0ae23
Author: Mikołaj Piróg <mikolaj.maciej.pirog at intel.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86WinEHUnwindV3.cpp
M llvm/test/CodeGen/X86/win64-eh-unwindv3-split-large.ll
Log Message:
-----------
[UnwinderV3] Include padding in spliting calculations (#208458)
As in title. This is achieved by making the pass count split points in
bytes and making the average instruction size a variable.
PR done with usage of Claude Code
Commit: 24c3eaa9ccaffca94e4d82a312fcc4ed13e62476
https://github.com/llvm/llvm-project/commit/24c3eaa9ccaffca94e4d82a312fcc4ed13e62476
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/limit-soft-clause-reg-pressure.mir
M llvm/test/CodeGen/AMDGPU/literal-constant-like-operand-instruction-size.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/live-interval-bug-in-rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/liveout-implicit-def-subreg-redef-blender-verifier-error.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.add.min.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.addrspacecast.nonnull.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load-last-use.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.lds.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.flat.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-agent.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-basic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-singlethread.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-system.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-wavefront.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-workgroup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f32.fp8.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.e5m3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.off.f32.i4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.pk.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dot4.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.add.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.append.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.async.barrier.arrive.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.fi.b32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.push.pop.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.consume.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-bundle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.br.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.p.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.v.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add-errors.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add-unsupported.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.read.tr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.sub.gs.reg.rtn.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (18) (#209121)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping
the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 23a32bcedb91f27ffdac5d6e6bc65a3b19b3b36c
https://github.com/llvm/llvm-project/commit/23a32bcedb91f27ffdac5d6e6bc65a3b19b3b36c
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolutionDivision.cpp
Log Message:
-----------
[SCEVDivision] Remove unnecessary integer casts (NFCI) (#208155)
Since #204146 requires callers of SCEVDivision to pass the numerator and
the denominator with the same type, the bitwidth check in
`visitConstant` no longer makes sense.
Commit: b1c29d83c938183a4fbd706818aa09de7e9eafec
https://github.com/llvm/llvm-project/commit/b1c29d83c938183a4fbd706818aa09de7e9eafec
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/docs/resources/lldbgdbremote.md
Log Message:
-----------
[lldb][docs] Fix some formatting in the packets doc (#209440)
Commit: 03b4714611ab0aab34c7267e0946fb79bf40babe
https://github.com/llvm/llvm-project/commit/03b4714611ab0aab34c7267e0946fb79bf40babe
Author: Sergey Shcherbinin <sscherbinin at nvidia.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/test/Driver/function-attr-readonly.f90
Log Message:
-----------
[flang][NFC] Fix function-attr-readonly test on PowerPC (#209431)
Follow-up fix for the newly added test, which was not exercised on all
targets. PowerPC adds llvm.target_features between the function argument
list and the body. Stop requiring the opening brace to immediately
follow the argument list so that the checks remain target-independent.
Commit: 48636d19ab5e3bf82cbff593a82573e8094abed1
https://github.com/llvm/llvm-project/commit/48636d19ab5e3bf82cbff593a82573e8094abed1
Author: Joel Walker <theagingboy05 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-avg.mir
M llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll
Log Message:
-----------
[GlobalISel] Add G_UAVGFLOOR/G_UAVGCEIL/G_SAVGFLOOR/G_SAVGCEIL to computeKnownBits (#209171)
Add known-bits handling for the averaging (halving add) opcodes G_UAVGFLOOR,
G_UAVGCEIL, G_SAVGFLOOR and G_SAVGCEIL in GISelValueTracking, using the
existing `KnownBits::avg{Floor,Ceil}{S,U}` helpers. This matches
SelectionDAG's handling of the corresponding ISD::AVGFLOOR*/AVGCEIL*
nodes.
This lets GlobalISel drop the redundant masking around hadd/rhadd of
zero-extended operands on AArch64 (see aarch64-known-bits-hadd.ll, where the
GlobalISel output now matches SelectionDAG). The sign-extended cases are
unaffected, since the masking is not redundant there.
Part of #150515.
---
Assisted by Claude (Anthropic).
Commit: cba0124e3c4f0bb5eebf551b049f8e463879642b
https://github.com/llvm/llvm-project/commit/cba0124e3c4f0bb5eebf551b049f8e463879642b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.prim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fract.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.async.from.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.simple.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2b.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2c.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.flt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.pk.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.o.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.getlod.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.x.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.cd.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.cd.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.cd.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.o.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.direct.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.param.load.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (19) (#209122)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: da99ce2fe0f4a185ceb02c9a650ba5efdb208612
https://github.com/llvm/llvm-project/commit/da99ce2fe0f4a185ceb02c9a650ba5efdb208612
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libc/include/llvm-libc-macros/linux/signal-macros.h
M libc/test/src/signal/sigaction_test.cpp
Log Message:
-----------
[libc] Implement SA_NODEFER and SA_RESETHAND signal flags (#209429)
Defined SA_NODEFER and SA_RESETHAND in Linux signal-macros.h.
Added unit tests in sigaction_test.cpp to verify the behavior of the new
flags. Also added a test case for SA_SIGINFO.
Assisted-by: Automated tooling, human reviewed.
Commit: b4b19c8f0cc28c20d98fe2ebcd2e869d0835c8eb
https://github.com/llvm/llvm-project/commit/b4b19c8f0cc28c20d98fe2ebcd2e869d0835c8eb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lerp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.clamp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mbcnt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.form.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.i8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.gfx1251.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.u32.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.msad.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mulhi.i24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mulhi.u24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.bcast.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.down.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.idx.gen.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.up.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.xor.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane32.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.prng.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.xfail.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.xfail.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.m0.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (20) (#209211)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping
the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 5d5dd83a547ea555a8eada2dfd50413c44a3cfe9
https://github.com/llvm/llvm-project/commit/5d5dd83a547ea555a8eada2dfd50413c44a3cfe9
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Passes/Pipelines.cpp
M llvm/include/llvm/Passes/OptimizationLevel.h
M llvm/include/llvm/Transforms/IPO/ExpandVariadics.h
M llvm/lib/Passes/CMakeLists.txt
R llvm/lib/Passes/OptimizationLevel.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M polly/lib/Support/RegisterPasses.cpp
Log Message:
-----------
[Passes] Replace OptimizationLevel with an enum (#209424)
Now that OptimizationLevel no longer has a size dimension, replace it
with a simple enum class.
Commit: 367d196e5cf964a1d89d596e13c89868da8c4d8c
https://github.com/llvm/llvm-project/commit/367d196e5cf964a1d89d596e13c89868da8c4d8c
Author: Anonmiraj <ezzibrahimx at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/Lex/Preprocessor.cpp
Log Message:
-----------
[clang][Diagnostics] Fix check-point recording under default colors (#209355)
`getShowColors() != ShowColorsKind::Off` is also true for the default
Auto, so ordinary non-TTY compiles where colors are never actually
emitted kept recording check points, leaving the original 718aac9f cost
in place.
Commit: ad3c1ef174f9cac5bd0332747226740ce1b16159
https://github.com/llvm/llvm-project/commit/ad3c1ef174f9cac5bd0332747226740ce1b16159
Author: Gábor Horváth <xazax.hun at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/Analysis/LiveVariables.cpp
Log Message:
-----------
[clang][Analysis] Speed up LiveVariables set merge (#209430)
LiveVariables' mergeSets built the union by unconditionally inserting
every element of B into A. Apply the two cheap tricks the
lifetime-safety analysis uses in its dataflow join:
* Return early when both operands are the same tree (an O(1) pointer
comparison), skipping the merge entirely. Merged liveness values are
canonicalized, so two predecessors with identical liveness share the
same tree -- common at confluence points.
* Insert the smaller set into the larger one, so the number of O(log n)
insertions is min(|A|, |B|) rather than always |B|.
The result is unchanged: set union is commutative and order-independent.
On a pathological function (1000 simultaneously-live locals across 5000
control-flow merges of identical sets) the liveness computation is ~18%
faster, essentially all from the identical-set short circuit. On real
translation units the merge is a small fraction of the analysis, so the
effect is within noise (measured neutral on DAGCombiner.cpp and
X86ISelLowering.cpp); this mainly avoids redundant work at unchanged
confluence points and brings the two dataflow analyses' merges into
line.
Assisted by: Claude Opus 4.8
Co-authored-by: Gabor Horvath <gaborh at apple.com>
Commit: edd94b8fbfae72059cbe31c78ac4580056b6bb9a
https://github.com/llvm/llvm-project/commit/edd94b8fbfae72059cbe31c78ac4580056b6bb9a
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M lldb/include/lldb/Utility/Log.h
M lldb/source/Commands/CommandObjectLog.cpp
M lldb/source/Utility/Log.cpp
M lldb/unittests/Utility/LogTest.cpp
Log Message:
-----------
[lldb] Return llvm::Error from DisableLogChannel (#207004)
Follow up to #206479.
llvm:Error better describes the success exor error message states that
we were previously doing with a boolean plus an error stream.
Commit: 42d52dfb9ceae5cb261b6032e50fba512479c7ce
https://github.com/llvm/llvm-project/commit/42d52dfb9ceae5cb261b6032e50fba512479c7ce
Author: Ömer Sinan Ağacan <omeragacan at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
Log Message:
-----------
[SelectionDAG] Update MemOp to distinguish memmove from memcpy (#206005)
Commit: 0c36950dd422b118b29621c4fc3e0c91cfcfd346
https://github.com/llvm/llvm-project/commit/0c36950dd422b118b29621c4fc3e0c91cfcfd346
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 16094a8 (#209435)
This fixes 16094a86a6cfe79fa50dcca39b539ab6465b8ac0.
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=16094a86a6cfe79fa50dcca39b539ab6465b8ac0
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 269820947e948a4e4bd0b3e352b6c2bd77525e83
https://github.com/llvm/llvm-project/commit/269820947e948a4e4bd0b3e352b6c2bd77525e83
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.decperflevel.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.get.waveid.in.workgroup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.incperflevel.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memtime.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.monitor.sleep.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.nop.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sethalt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.inc.wg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.ttracedata.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt_gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.hi.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.iterative.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.ll
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (21) (#209212)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping
the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: f5a55b576add124ef5350d81089eccda7103cb93
https://github.com/llvm/llvm-project/commit/f5a55b576add124ef5350d81089eccda7103cb93
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/include/mlir/TableGen/Format.h
Log Message:
-----------
[MLIR][NFC] Fix tgfmt compilation with MSVC (#209446)
Apparently older MSVC has problems with inferring template argument
types. Provide them explicitly.
Fixes https://github.com/llvm/llvm-project/issues/209303.
Commit: cd75ff08c6baf74114933a927308e8ce581efc70
https://github.com/llvm/llvm-project/commit/cd75ff08c6baf74114933a927308e8ce581efc70
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[VPlan] Type VP(Recipe|Block)Ty SubclassID (NFC) (#209132)
With the advantage that switching over the SubclassID would give better
compile-time diagnostics.
Co-authored-by: Luke Lau <luke at igalia.com>
Commit: 4b32060e213376bf1d014ffc3a462c959d8adc0a
https://github.com/llvm/llvm-project/commit/4b32060e213376bf1d014ffc3a462c959d8adc0a
Author: disservin <disservin.social at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/bitreverse.ll
Log Message:
-----------
[X86] Use BMM for bitreverse without GFNI (#209223)
For the scalar path bitreverse currently doesn't lower to vbitrevb on
AVX512-BMM unless GFNI is specified as well. However, GFNI isn't
required at all for this and only BMM needs to be present.
See https://godbolt.org/z/xr61xYzYr
Commit: 5ae6537bbaf577889fb81f5f8397463b0d0499c3
https://github.com/llvm/llvm-project/commit/5ae6537bbaf577889fb81f5f8397463b0d0499c3
Author: ioana ghiban <ioana.ghiban at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/lib/Conversion/EmitCCommon/TypeConverter.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/test/Conversion/FuncToEmitC/func-to-emitc-failed.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-dealloc.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-load-store.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-copy.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-failed.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc.mlir
Log Message:
-----------
[mlir][EmitC] Add rank-0 MemRef conversion (#205774)
Add rank-0 memref support to MemRefToEmitC and the EmitC TypeConverter,
needed for lowering the models generated by:
- `llvm/lib/Analysis/models/gen-inline-oz-test-model.py`
- `llvm/lib/Analysis/models/gen-regalloc-eviction-test-model.py`
Rank-0 memrefs are no longer rejected by `isMemRefTypeLegalForEmitC`.
The EmitC type converter maps `memref<T>` to `!emitc.ptr<T>`, giving
rank-0 memrefs addressable scalar storage.
`memref.alloc` now allocates one element for rank-0 memrefs.
`memref.dealloc` frees the pointer-backed value. `memref.load` and
`memref.store` lower rank-0 accesses through `emitc.subscript %ptr[0]`,
followed by `emitc.load` or `emitc.assign`. `memref.copy` lowers rank-0
copies as scalar load plus assign.
`memref.alloca` still rejects rank-0 memrefs because this patch only
supports pointer-backed rank-0 lowering.
The pointer recovery helper now accepts both direct `emitc.ptr<T>`
values and pointer values behind `builtin.unrealized_conversion_cast`,
which is needed by dealloc, copy, load, and store depending on where the
value comes from in conversion.
Tests cover rank-0 alloc/dealloc, load/store, alloc-backed load/store,
and copy. Removed cases this patch adds support for (rank-0) from
`func-to-emitc-failed`.
Assisted-by: Codex (refine implementation + tests). I reviewed all code
and tests before submission.
Commit: 2d1bc4fc5d00d6c96307d5375d7259011509faf3
https://github.com/llvm/llvm-project/commit/2d1bc4fc5d00d6c96307d5375d7259011509faf3
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/src/atomic.cpp
Log Message:
-----------
[libc++] Fix usage of constructive interference when we meant destructive (#208804)
We maintain a contention table to implement atomic wait/notify inside
atomic.cpp. Entries in that table are padded to avoid false sharing,
since they are expected to be accessed from multiple threads
concurrently.
However, we used std::hardware_constructive_interference_size for that,
when in reality std::hardware_destructive_interference_size is the one
we need. The semantics of constructive interference are to promote true
sharing for data that should stay colocated, while destructive
interference is to prevent false sharing.
Note that on platforms such as macOS arm64, destructive interference
size is larger than constructive interference size, which means that
this patch may regress the size of the dylib on some platforms. However,
that is required for performance purposes.
Fixes #208305
Commit: bf086335b25387ed7496577eb027531ea287f524
https://github.com/llvm/llvm-project/commit/bf086335b25387ed7496577eb027531ea287f524
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.shuffle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wavefrontsize.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.fmt-error.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.index.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id-unsupported-calling-convention.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.ll
M llvm/test/CodeGen/AMDGPU/llvm.deoptimize.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.modf.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.pow-gfx9.ll
M llvm/test/CodeGen/AMDGPU/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.ll
M llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/lo16-hi16-illegal-copy.mir
M llvm/test/CodeGen/AMDGPU/lo16-hi16-physreg-copy.mir
M llvm/test/CodeGen/AMDGPU/lo16-lo16-physreg-copy-agpr.mir
Log Message:
-----------
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (22) (#209213)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping
the redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 6e515cd0982dbf8db7ab3850b23994396efb40bf
https://github.com/llvm/llvm-project/commit/6e515cd0982dbf8db7ab3850b23994396efb40bf
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[lldb][Windows] add release notes for lldb-server (#209415)
As of https://github.com/llvm/llvm-project/pull/209258,
`lldb-server.exe` is now the default plugin if libxml2 is available at
build time.
This patch adds a release note for this change.
Commit: 98c4ea46bd474bff97c99be0800bd7b310185a29
https://github.com/llvm/llvm-project/commit/98c4ea46bd474bff97c99be0800bd7b310185a29
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/cmake/Modules/HandleLibCXXABI.cmake
Log Message:
-----------
[libc++] Improve diagnostic for libcxxabi missing from the runtimes (#208274)
When libc++ is configured to use libc++abi as an ABI library but
libcxxabi is not part of the runtimes, we'd end up with a confusing
build error about a missing <cxxabi.h> header. Instead, diagnose at
CMake configuration time.
Closes #136480
Commit: 23b3f21fd0fff64644cf60065b971686aab9c1b3
https://github.com/llvm/llvm-project/commit/23b3f21fd0fff64644cf60065b971686aab9c1b3
Author: inquisitivecrystal <open-source at inquisitivecrystal.addy.io>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/docs/Status/Cxx20Papers.csv
M libcxx/docs/Status/Cxx23Issues.csv
Log Message:
-----------
[libc++] Mark LWG3403 as complete (#208866)
LWG3403 specifies that `ranges::ssize` should work on non-range objects
for which `ranges::size` is valid. This has been true in libc++ since
6f1b10d, which first implemented `ranges::ssize` for libc++13. The tests
introduced by that commit are sufficient to verify compliance since they
test calling `ranges::ssize` with various non-range arguments.
In addition to marking LWG3403 as complete, this also updates the status
page entry for P1970R2, the paper that added `ranges::ssize`. P1970R2 was
previously marked complete in libc++15 as an approximation; however, it was
actually complete in libc++13.
Resolves #104280
Commit: cf9a244fb2216fb55b77e1df785f6535b44b3e7f
https://github.com/llvm/llvm-project/commit/cf9a244fb2216fb55b77e1df785f6535b44b3e7f
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libc/include/llvm-libc-macros/gpu/signal-macros.h
M libc/include/llvm-libc-macros/linux/signal-macros.h
M libc/include/llvm-libc-macros/netinet-in-macros.h
M libc/include/llvm-libc-types/__futex_word.h
M libc/include/sys/prctl.h.def
Log Message:
-----------
[libc] Fix non-relative includes of __llvm-libc-common.h (#209412)
This seems to work, but I ran into this problem when trying to expand
hermetic tests.
The hdrgen-generated headers already use relative includes of this file.
Commit: cd943207f38d36528a36009e55f80501da98bcef
https://github.com/llvm/llvm-project/commit/cd943207f38d36528a36009e55f80501da98bcef
Author: Mark Zhuang <mark.zhuang at spacemit.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M flang-rt/CMakeLists.txt
Log Message:
-----------
[flang-rt] Disable tests by default when cross-compiling (#208926)
Cross-compiled tests can't run on the build host and pull in host
dependencies (e.g. LLVMSupport's ZLIB::ZLIB) that break the build.
Fixes #208924
Commit: d64972c91369c6372e23e728881d9c645edeb37d
https://github.com/llvm/llvm-project/commit/d64972c91369c6372e23e728881d9c645edeb37d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
Log Message:
-----------
clang-linker-wrapper: Add additional amdgpu device merging tests (#209428)
Commit: 12ce00a865b09cb72a3ea9a84f9308236a4f6038
https://github.com/llvm/llvm-project/commit/12ce00a865b09cb72a3ea9a84f9308236a4f6038
Author: Ben Dunbobbin <Ben.Dunbobbin at sony.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
A cross-project-tests/dtlto/cache-extraction.test
R cross-project-tests/dtlto/cache-serialization.test
M lld/test/ELF/dtlto/timetrace.test
M llvm/include/llvm/DTLTO/DTLTO.h
M llvm/include/llvm/LTO/LTO.h
M llvm/lib/DTLTO/DTLTO.cpp
M llvm/lib/DTLTO/DTLTOInputFiles.cpp
Log Message:
-----------
[DTLTO] terminology - use extract rather than serialize (#208468)
Change the terminology used for DTLTO from "serialization" to
"extraction" for improved clarity.
Update the DTLTO time-trace scope and tests to match the new wording,
and rename/update related LLD and cross-project DTLTO cache tests.
I have also improved some unrelated wording in the comments and removed
a redundant comment block from the DTLTO class comment.
This terminology improvement was agreed in
https://github.com/llvm/llvm-project/pull/204104. Note that the
documentation already uses this terminology, see:
https://llvm.org/docs/DTLTO.html.
Commit: 226acaf7aeeda64a6e4e55d21f586ffe97a72fc8
https://github.com/llvm/llvm-project/commit/226acaf7aeeda64a6e4e55d21f586ffe97a72fc8
Author: Osama Abdelkader <osama.abdelkader at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/Sema/DeclSpec.cpp
M clang/test/SemaCXX/auto-cxx0x.cpp
Log Message:
-----------
Fix auto type-specifier conflict crash (#209308)
Clear owned type state when an invalid C++ auto/type-specifier conflict
is converted to an error so invalid declarations cannot trip DeclSpec
invariants.
Fixes https://github.com/llvm/llvm-project/issues/209000
Commit: 40152b8767769873a8f0d99b857f07c874cccf4a
https://github.com/llvm/llvm-project/commit/40152b8767769873a8f0d99b857f07c874cccf4a
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M libcxx/include/__functional/function.h
Log Message:
-----------
[libc++][NFC] Inline std::function members into the class body (#209461)
The `std::function` members are incredibly simple to the point where
they are just wrappers around internal functions. We can inline them
into the body to simplify the implementation a bit.
Commit: 8748e5e3ac5d06663c3f2057a71ef19065baebaf
https://github.com/llvm/llvm-project/commit/8748e5e3ac5d06663c3f2057a71ef19065baebaf
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt/Compiler.h
M orc-rt/test/unit/CMakeLists.txt
A orc-rt/test/unit/CompilerTest.cpp
Log Message:
-----------
[orc-rt] Add ORC_RT_UNREACHABLE / ORC_RT_BUILTIN_UNREACHABLE (#209466)
ORC_RT_BUILTIN_UNREACHABLE is an optimizer hint that a location is
unreachable, wrapping __builtin_unreachable / __assume(false). Executing
it is undefined behavior.
ORC_RT_UNREACHABLE(MSG) marks a point the program must never reach. It
aborts with MSG in +Asserts builds; otherwise it lowers to
ORC_RT_BUILTIN_UNREACHABLE.
Adds a CompilerTest unit test covering both the returning-function
compile path and, in +Asserts builds only, the abort behavior via a
death test.
Commit: 2e86804e612fc6d1bace4e08b8404d0ea383d368
https://github.com/llvm/llvm-project/commit/2e86804e612fc6d1bace4e08b8404d0ea383d368
Author: Scott Manley <rscottmanley at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
M mlir/lib/Dialect/OpenACC/Transforms/ACCRecipeMaterialization.cpp
M mlir/test/Dialect/OpenACC/acc-recipe-materialization-reduction.mlir
Log Message:
-----------
[OpenACC] apply seq par dims to reduction variables (#209261)
When the acc.parallel op is "effectively sequential" apply the correct
par dims during recipe materialization of reduction variables
Commit: fba1a4b1292af3e7d08e9678e967ce12795d67d4
https://github.com/llvm/llvm-project/commit/fba1a4b1292af3e7d08e9678e967ce12795d67d4
Author: Hrólf Kraki <janmejayapanda400 at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/lib/Sema/SemaOverload.cpp
M clang/test/SemaCXX/recovery-expr-type.cpp
Log Message:
-----------
[clang] Prevent nested RecoveryExpr in BuildConvertedConstantExpression (#207072)
when BuildConvertedConstantExpression receives an expression that is
already a RecoveryExpr, return it directly instead of wrapping it in
another RecoveryExpr
Fixes #186656
Fixes #202117
Commit: 8518c74b5ef8950b9b604df588f29d9037fe1380
https://github.com/llvm/llvm-project/commit/8518c74b5ef8950b9b604df588f29d9037fe1380
Author: 1sgtpepper <cynejarviszarceno at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/LLVMIR/Import/function-attributes.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[mlir][llvm] Preserve function entry count metadata (#204707)
Fixes #202374.
Preserve LLVM function `!prof` metadata for:
- `synthetic_function_entry_count`
- `function_entry_count` with import GUID operands
The importer represents the entry count, count kind, and trailing import
GUID operands in a single `#llvm.function_entry_count` attribute,
validates malformed operands before mutating the operation, and exports
the metadata through `llvm::Function::setEntryCount`.
Tests cover import, export, malformed metadata operands, synthetic
counts, synthetic counts with trailing operands, import GUID
round-tripping, and raw i64 bit-pattern preservation.
Checks:
- `git diff --check`
- `git clang-format --diff origin/main -- ...`
- `llvm-as -disable-output` smoke check
Codex was used in making this PR.
Commit: 571a27629c1bdf0b63e65a884ffa35c5c3ede767
https://github.com/llvm/llvm-project/commit/571a27629c1bdf0b63e65a884ffa35c5c3ede767
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M orc-rt/test/unit/CMakeLists.txt
Log Message:
-----------
[orc-rt] Sort unit test sources in CMakeLists.txt. NFC. (#209470)
Commit: b26c417dd887aec06f4a09cd23a979b705c59fa2
https://github.com/llvm/llvm-project/commit/b26c417dd887aec06f4a09cd23a979b705c59fa2
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Analysis/InlineCost.cpp
M llvm/test/Transforms/Inline/byval.ll
Log Message:
-----------
[InlineCost] Drop Requirements around ByVal Arguments
The underlying behavior was fixed in
e47359a925b88cd081ea85d10b55b0625d17b212, but given that the example
was marked alwaysinline, it bypassed any legality checks it would have
otherwise hit.
See
https://github.com/llvm/llvm-project/pull/97306#discussion_r1679306183
for discussion around which address space we should be using/legality.
This is necessary to preserve the behavior in
byval-with-non-alloca-addrspace.ll after we enable function attribute
compatibility checks in always-inline.
Reviewers: aeubanks, nikic, arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/209344
Commit: 37b8e765ce4837a7577e6f762bcdffe4b232759c
https://github.com/llvm/llvm-project/commit/37b8e765ce4837a7577e6f762bcdffe4b232759c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Transforms/IPO/AlwaysInliner.cpp
A llvm/test/Transforms/Inline/X86/always-inline-incompatible-target-features.ll
M llvm/test/Transforms/Inline/always-inline-phase-ordering.ll
Log Message:
-----------
[AlwaysInliner] Do not inline on attribute mismatches
7bdca287b102ee935e982613dba2264cbc7a32ad made it so that the inliner
will not inline functions with mismatched target attributes regardless
of the presence of alwaysinline. However, always-inline never actually
called into this function so would still do the illegal thing. I believe
the motivation for not putting it here originally/recently was that
clang does some rudimentary target feature checks, but we should not be
crashing on valid IR, and we do generate IR that caused crashes in ISel
due to this (e.g., ICP in ThinLTO backend actions).
Reviewers: nikic, aeubanks
Pull Request: https://github.com/llvm/llvm-project/pull/209345
Commit: c43967ca744ae2479987c1859df36fbb2fcf0866
https://github.com/llvm/llvm-project/commit/c43967ca744ae2479987c1859df36fbb2fcf0866
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang/unittests/StaticAnalyzer/FalsePositiveRefutationBRVisitorTest.cpp
Log Message:
-----------
[analyzer] Uplift UnSatAtErrorNodeDueToRefinedConstraint test after smarter range inference (#209443)
Commit db28e48d67e3b0c44d88be9ea2d28eca2d239a9a taught
`SymbolicRangeInferrer` to derive the range of
`BO_Add`/`BO_Sub`/`BO_Mul` symbols from their operands via
`inferFromCorners`. This broke
`FalsePositiveRefutationBRVisitorTestBase.UnSatAtErrorNodeDueToRefinedConstraintNoReport`.
The test relied on the analyzer not being able to bound `int y = x + n;`
(with `x:[0,2]`, `n:[1,2]`), so that `reportIfCanBeTrue(y == 5)` created
a false state that only the Z3 crosscheck could refute. Now the analyzer
natively bounds y to `[1,4]`, proves `y == 5` infeasible, and never
emits `CAN_BE_TRUE`, so the non-Z3 assertion lost its second line.
Addition can never produce a gap (the sum of two intervals is a full
interval), so the test's premise is no longer achievable with '+'.
Switch to multiplication: for `x:[0,2]`, `n:[1,2]` the reachable
products are `{0,1,2,4}`, but `inferFromCorners` over-approximates `x*n`
to the contiguous range `[0,4]`. So `y == 3` is inside the inferred
range (native manager returns `UNKNOWN -> CAN_BE_TRUE` emitted without
Z3) yet is genuinely unreachable (Z3 refutes `x*n == 3` -> report
invalidated with crosscheck). This restores the exact refutation-visitor
mechanism the test exercises.
Fixes up #209048.
This issue would have been caught if we had a CI running Z3, like
proposed in #184695.
Assisted-by: Claude Opus 4.8
Commit: fb423ba07c3ff51fda3caa41d8bbb78d50f61906
https://github.com/llvm/llvm-project/commit/fb423ba07c3ff51fda3caa41d8bbb78d50f61906
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
A llvm/test/Assembler/thinlto-bad-summary-5.ll
Log Message:
-----------
[ThinLTO] Error on missing ValueInfo for function definition
We assume that these are available inside of BitcodeWriter
https://github.com/llvm/llvm-project/blob/09796808802f99c30a23bc0f2cd68243764e84ab/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp#L4927,
but do not currently validate this in input IR. This means that when
doing reductions with automated tooling in a non-asserts build, it is
pretty easy to end up with invalid IR that is not caught as invalid.
Reviewers: teresajohnson, mtrofin
Pull Request: https://github.com/llvm/llvm-project/pull/208948
Commit: 6af0a79d7a4e8558e89290df56491521c6730acd
https://github.com/llvm/llvm-project/commit/6af0a79d7a4e8558e89290df56491521c6730acd
Author: Douglas Yung <douglas.yung at sony.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M clang-tools-extra/docs/ReleaseNotes.rst
M clang/docs/ReleaseNotes.md
M cmake/Modules/LLVMVersion.cmake
M flang/docs/ReleaseNotes.md
M libcxx/include/__config
M lld/docs/ReleaseNotes.rst
M llvm/docs/ReleaseNotes.md
M llvm/utils/gn/secondary/llvm/version.gni
M llvm/utils/lit/lit/__init__.py
M llvm/utils/mlgo-utils/mlgo/__init__.py
Log Message:
-----------
Bump version to 24.0.0git (#209473)
Commit: aefba88f46a6e55645c848f58f6ba56944d5ae62
https://github.com/llvm/llvm-project/commit/aefba88f46a6e55645c848f58f6ba56944d5ae62
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/CodeGen/AArch64/sve-cmp-folds.ll
Log Message:
-----------
[LLVM][CodeGen][SVE] Add isel for zext(setcc(x,0,ne)) -> umin(x,1). (#209452)
Commit: 53da48fbaa9e485cb166b9759a6a5e0679867c84
https://github.com/llvm/llvm-project/commit/53da48fbaa9e485cb166b9759a6a5e0679867c84
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-14 (Tue, 14 Jul 2026)
Changed paths:
M .github/workflows/containers/github-action-ci/Dockerfile
M clang-tools-extra/clang-doc/CMakeLists.txt
M clang-tools-extra/clang-doc/Generators.cpp
M clang-tools-extra/clang-doc/Generators.h
M clang-tools-extra/clang-doc/JSONGenerator.cpp
M clang-tools-extra/clang-doc/MDGenerator.cpp
R clang-tools-extra/clang-doc/MDMustacheGenerator.cpp
M clang-tools-extra/clang-doc/Representation.h
R clang-tools-extra/clang-doc/YAMLGenerator.cpp
M clang-tools-extra/clang-doc/tool/ClangDocMain.cpp
M clang-tools-extra/clang-tidy/misc/RedundantExpressionCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseScopedLockCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/use-scoped-lock.rst
M clang-tools-extra/test/clang-doc/basic-project.mustache.test
M clang-tools-extra/test/clang-doc/basic-project.test
M clang-tools-extra/test/clang-doc/md/array-type.cpp
M clang-tools-extra/test/clang-doc/md/builtin_types.cpp
M clang-tools-extra/test/clang-doc/md/class-partial-specialization.cpp
M clang-tools-extra/test/clang-doc/md/comments-in-macros.cpp
M clang-tools-extra/test/clang-doc/md/enum.cpp
M clang-tools-extra/test/clang-doc/md/function-pointer-type.cpp
M clang-tools-extra/test/clang-doc/md/member-function-pointer-type.cpp
M clang-tools-extra/test/clang-doc/md/namespace.cpp
M clang-tools-extra/test/clang-doc/md/nested-pointer-qualifiers.cpp
M clang-tools-extra/test/clang-doc/md/templates.cpp
R clang-tools-extra/test/clang-doc/yaml/builtin_types.cpp
R clang-tools-extra/test/clang-doc/yaml/conversion_function.cpp
R clang-tools-extra/test/clang-doc/yaml/single-file-public.cpp
R clang-tools-extra/test/clang-doc/yaml/single-file.cpp
R clang-tools-extra/test/clang-doc/yaml/templates.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/redundant-expression.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-scoped-lock-warn-on-single-locks-false.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-scoped-lock.cpp
M clang-tools-extra/unittests/clang-doc/CMakeLists.txt
R clang-tools-extra/unittests/clang-doc/MDGeneratorTest.cpp
R clang-tools-extra/unittests/clang-doc/YAMLGeneratorTest.cpp
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/AArch64CodeGenUtils.h
M clang/include/clang/Basic/PointerAuthOptions.h
M clang/include/clang/Basic/arm_neon.td
M clang/include/clang/ScalableStaticAnalysis/Analyses/TypeConstrainedPointers/TypeConstrainedPointers.h
M clang/lib/Analysis/LiveVariables.cpp
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Format/CMakeLists.txt
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Lex/Preprocessor.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/TypeConstrainedPointers/TypeConstrainedPointers.cpp
M clang/lib/Sema/DeclSpec.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/Analysis/Scalable/TypeConstrainedPointers/type-constrained-pointers.cpp
M clang/test/CXX/drs/cwg5xx.cpp
M clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c
M clang/test/CodeGen/AArch64/neon/fullfp16.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
M clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
M clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
M clang/test/CodeGen/builtins.c
M clang/test/CodeGen/ptrauth-init-fini.c
M clang/test/CodeGen/ptrauth-module-flags.c
M clang/test/Driver/msvc-link.c
M clang/test/Interpreter/pch-pic-mismatch.cpp
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
M clang/test/Parser/cxx-default-args.cpp
M clang/test/Sema/aarch64-neon-target.c
M clang/test/Sema/aarch64-neon-without-target-feature.cpp
M clang/test/SemaCXX/auto-cxx0x.cpp
M clang/test/SemaCXX/recovery-expr-type.cpp
A clang/test/SemaTemplate/GH195988.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/unittests/ScalableStaticAnalysis/Analyses/TypeConstrainedPointers/TypeConstrainedPointersExtractorTest.cpp
M clang/unittests/StaticAnalyzer/FalsePositiveRefutationBRVisitorTest.cpp
M cmake/Modules/LLVMVersion.cmake
M compiler-rt/lib/gwp_asan/optional/backtrace_linux_libc.cpp
A cross-project-tests/dtlto/cache-extraction.test
R cross-project-tests/dtlto/cache-serialization.test
M flang-rt/CMakeLists.txt
M flang/docs/ReleaseNotes.md
M flang/include/flang/Optimizer/Dialect/FIROpsSupport.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/FunctionAttr.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Driver/function-attr-readonly.f90
A flang/test/Evaluate/fold-kind-logical.f90
A flang/test/Evaluate/fold-kind-substring.f90
A flang/test/Evaluate/fold-kind-zero-size.f90
M flang/test/Evaluate/logical-args.f90
A flang/test/Lower/CUDA/cuda-implicit-managed-alloc.cuf
A flang/test/Lower/HLFIR/array-ctor-character-kind.f90
M flang/test/Lower/HLFIR/structure-constructor.f90
M flang/test/Lower/Intrinsics/dconjg.f90
M flang/test/Lower/Intrinsics/dimag.f90
M flang/test/Lower/Intrinsics/dreal.f90
M flang/test/Lower/OpenMP/optional-argument-map.f90
M flang/test/Lower/OpenMP/wsloop-unstructured.f90
M flang/test/Lower/achar.f90
M flang/test/Lower/arguments.f90
M flang/test/Lower/call-copy-in-out.f90
M flang/test/Lower/dispatch.f90
A flang/test/Lower/dummy-argument-readonly.f90
M flang/test/Lower/polymorphic-temp.f90
M flang/test/Lower/polymorphic.f90
M flang/test/Lower/select-type.f90
M flang/test/Lower/unsigned-ops.f90
M flang/test/Lower/volatile1.f90
A flang/test/Semantics/modfile84.F90
A flang/test/Semantics/substring-literal-kind.f90
A flang/test/Transforms/function-attrs-readonly.fir
M libc/include/llvm-libc-macros/gpu/signal-macros.h
M libc/include/llvm-libc-macros/linux/signal-macros.h
M libc/include/llvm-libc-macros/netinet-in-macros.h
M libc/include/llvm-libc-types/__futex_word.h
M libc/include/sys/prctl.h.def
M libc/test/src/signal/sigaction_test.cpp
M libcxx/cmake/Modules/HandleLibCXXABI.cmake
M libcxx/docs/Status/Cxx20Papers.csv
M libcxx/docs/Status/Cxx23Issues.csv
M libcxx/include/__config
M libcxx/include/__functional/function.h
M libcxx/src/atomic.cpp
M libcxx/src/include/overridable_function.h
M libcxx/src/new.cpp
M libcxx/utils/libcxx/test/dsl.py
M libcxxabi/src/stdlib_new_delete.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/MarkLive.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/Writer.cpp
M lld/docs/ReleaseNotes.rst
M lld/docs/ld.lld.1
M lld/test/ELF/dtlto/timetrace.test
M lld/test/ELF/retain-symbols-file.s
M lld/test/ELF/version-script-warn.s
M lldb/bindings/interface/SBTargetDocstrings.i
M lldb/bindings/python/CMakeLists.txt
M lldb/docs/CMakeLists.txt
M lldb/docs/resources/lldbgdbremote.md
M lldb/docs/use/tutorial.md
A lldb/examples/python/templates/scripted_breakpoint.py
A lldb/examples/python/templates/scripted_hook.py
M lldb/include/lldb/Core/PluginManager.h
M lldb/include/lldb/Host/Host.h
R lldb/include/lldb/Interpreter/Interfaces/ScriptedStopHookInterface.h
M lldb/include/lldb/Interpreter/ScriptInterpreter.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/Utility/Log.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/include/lldb/lldb-forward.h
M lldb/source/Breakpoint/Watchpoint.cpp
M lldb/source/Commands/CommandObjectLog.cpp
M lldb/source/Core/PluginManager.cpp
M lldb/source/Host/common/Host.cpp
M lldb/source/Host/macosx/objcxx/Host.mm
M lldb/source/Plugins/ScriptInterpreter/Python/CMakeLists.txt
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/OperatingSystemPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/OperatingSystemPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptInterpreterPythonInterfaces.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedBreakpointPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedFrameProviderPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedFramePythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedFramePythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedHookPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedHookPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPlatformPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface.cpp
R lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedStopHookPythonInterface.cpp
R lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedStopHookPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPlanPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
M lldb/source/Target/Target.cpp
M lldb/source/Utility/Listener.cpp
M lldb/source/Utility/Log.cpp
M lldb/test/API/tools/lldb-dap/stackTrace/TestDAP_stackTrace.py
M lldb/test/API/tools/lldb-dap/stackTraceCompilerGeneratedCode/TestDAP_stackTraceCompilerGeneratedCode.py
M lldb/test/API/tools/lldb-dap/stackTraceDisassemblyDisplay/TestDAP_stackTraceDisassemblyDisplay.py
M lldb/test/API/tools/lldb-dap/stackTraceMissingFunctionName/TestDAP_stackTraceMissingFunctionName.py
M lldb/test/API/tools/lldb-dap/stackTraceMissingModule/TestDAP_stackTraceMissingModule.py
M lldb/test/Shell/Commands/command-scripting-extension-list.test
M lldb/test/Shell/Register/x86-db-read.test
M lldb/unittests/Utility/LogTest.cpp
M llvm/cmake/modules/FindDIASDK.cmake
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CommandGuide/lit.rst
M llvm/docs/LangRef.md
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/Analysis/ModuleSummaryAnalysis.h
M llvm/include/llvm/CodeGen/MachineBlockPlacement.h
M llvm/include/llvm/CodeGen/RegisterCoalescerPass.h
M llvm/include/llvm/CodeGen/Rematerializer.h
M llvm/include/llvm/CodeGen/RenameIndependentSubregs.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGen/TwoAddressInstructionPass.h
M llvm/include/llvm/CodeGen/UnreachableBlockElim.h
M llvm/include/llvm/DTLTO/DTLTO.h
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
M llvm/include/llvm/LTO/LTO.h
M llvm/include/llvm/MC/MCTargetOptions.h
M llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
M llvm/include/llvm/Object/IRSymtab.h
M llvm/include/llvm/Passes/OptimizationLevel.h
M llvm/include/llvm/ProfileData/SampleProfReader.h
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/include/llvm/Transforms/IPO/ExpandVariadics.h
M llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h
M llvm/include/llvm/Transforms/Utils/UnifyLoopExits.h
M llvm/lib/Analysis/InlineCost.cpp
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolutionDivision.cpp
M llvm/lib/Analysis/StackSafetyAnalysis.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/DTLTO/DTLTO.cpp
M llvm/lib/DTLTO/DTLTOInputFiles.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/MC/MCTargetOptions.cpp
M llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
M llvm/lib/Object/ArchiveWriter.cpp
M llvm/lib/Object/OffloadBinary.cpp
M llvm/lib/Passes/CMakeLists.txt
R llvm/lib/Passes/OptimizationLevel.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64PointerAuth.h
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h
M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNNSAReassign.h
M llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
M llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h
M llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SILowerControlFlow.h
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
M llvm/lib/Target/AMDGPU/SILowerWWMCopies.h
M llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/BPF/BPF.h
M llvm/lib/Target/BPF/BPFAsmPrinter.cpp
M llvm/lib/Target/BPF/BPFAsmPrinter.h
M llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp
A llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp
M llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
M llvm/lib/Target/BPF/BPFMIChecking.cpp
M llvm/lib/Target/BPF/BPFMIPeephole.cpp
M llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
M llvm/lib/Target/BPF/BPFPassRegistry.def
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
M llvm/lib/Target/BPF/BPFTargetMachine.h
M llvm/lib/Target/BPF/CMakeLists.txt
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYTargetStreamer.h
M llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/SystemZ/SystemZInstrVector.td
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86WinEHUnwindV3.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/Transforms/IPO/AlwaysInliner.cpp
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/Assembler/thinlto-bad-summary-5.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-avg.mir
M llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll
M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/branch-cond-split-fcmp.ll
M llvm/test/CodeGen/AArch64/clmul.ll
A llvm/test/CodeGen/AArch64/large-eh-encoding.ll
A llvm/test/CodeGen/AArch64/ptrauth-init-fini-autoupgrade.ll
M llvm/test/CodeGen/AArch64/ptrauth-init-fini.ll
M llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/round-fptoui-sat-scalar.ll
M llvm/test/CodeGen/AArch64/sve-cmp-folds.ll
M llvm/test/CodeGen/AArch64/sve2p1-while-pn-folds.ll
A llvm/test/CodeGen/AMDGPU/atomic_optimizations_dpp_lds_expected_active_lanes.ll
A llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-hsa.ll
A llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-rel32.mir
A llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr.ll
M llvm/test/CodeGen/AMDGPU/intrinsic-amdgcn-s-alloc-vgpr.ll
M llvm/test/CodeGen/AMDGPU/invalid-cast-load-i1.ll
M llvm/test/CodeGen/AMDGPU/invalid-hidden-kernarg-in-kernel-signature.ll
M llvm/test/CodeGen/AMDGPU/invariant-image-load.ll
M llvm/test/CodeGen/AMDGPU/ipra.ll
M llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/issue121601-combine-concat-vectors-assumes-f16.ll
M llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
M llvm/test/CodeGen/AMDGPU/issue139317-bad-opsel-reg-sequence-fold.ll
M llvm/test/CodeGen/AMDGPU/issue153808-extract-subvector-legalize.ll
M llvm/test/CodeGen/AMDGPU/issue176966-extend-vector-inreg.ll
M llvm/test/CodeGen/AMDGPU/issue48473.mir
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
M llvm/test/CodeGen/AMDGPU/issue98474-assigned-physreg-interference.mir
M llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll
M llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir
M llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/kernarg-size.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
M llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/kill-true-in-return-block.ll
M llvm/test/CodeGen/AMDGPU/known-never-nan.ll
M llvm/test/CodeGen/AMDGPU/known-never-snan.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll
M llvm/test/CodeGen/AMDGPU/large-avgpr-assign-last.mir
M llvm/test/CodeGen/AMDGPU/large-constant-initializer.ll
M llvm/test/CodeGen/AMDGPU/large-phi-search.ll
M llvm/test/CodeGen/AMDGPU/large-work-group-promote-alloca.ll
M llvm/test/CodeGen/AMDGPU/lds-barrier-memoperand.ll
M llvm/test/CodeGen/AMDGPU/lds-bounds.ll
M llvm/test/CodeGen/AMDGPU/lds-branch-vmem-hazard.mir
M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx11.mir
M llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx12.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-hazards.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll
M llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll
M llvm/test/CodeGen/AMDGPU/lds-initializer.ll
M llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-agpr.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-callgraph.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-named-barrier.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-typeid.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen.ll
M llvm/test/CodeGen/AMDGPU/lds-link-time-named-barrier.ll
M llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/lds-mixed-absolute-addresses-unused.ll
M llvm/test/CodeGen/AMDGPU/lds-mixed-absolute-dynlds.ll
M llvm/test/CodeGen/AMDGPU/lds-no-realign-allocated-variables.ll
M llvm/test/CodeGen/AMDGPU/lds-reject-anonymous-kernels.ll
M llvm/test/CodeGen/AMDGPU/lds-reject-mixed-absolute-addresses.ll
M llvm/test/CodeGen/AMDGPU/lds-relocs.ll
M llvm/test/CodeGen/AMDGPU/lds-run-twice-absolute-md.ll
M llvm/test/CodeGen/AMDGPU/lds-run-twice.ll
M llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx950.ll
M llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.dead.mir
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-fp-load-invariant.ll
M llvm/test/CodeGen/AMDGPU/legalize-soffset-mbuf.ll
M llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
M llvm/test/CodeGen/AMDGPU/licm-valu.mir
M llvm/test/CodeGen/AMDGPU/licm-wwm.mir
M llvm/test/CodeGen/AMDGPU/limit-soft-clause-reg-pressure.mir
M llvm/test/CodeGen/AMDGPU/literal-constant-like-operand-instruction-size.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/live-interval-bug-in-rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/liveout-implicit-def-subreg-redef-blender-verifier-error.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.add.min.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.addrspacecast.nonnull.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load-last-use.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.lds.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.flat.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-agent.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-basic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-singlethread.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-system.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-wavefront.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-workgroup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f32.fp8.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.e5m3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.off.f32.i4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.pk.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dot4.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.add.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.append.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.async.barrier.arrive.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.fi.b32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.push.pop.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.consume.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-bundle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.br.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.p.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.v.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add-errors.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add-unsupported.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.read.tr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.sub.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.prim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.idx.gen.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane32.swap.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.prng.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.dwordx3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.shuffle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wavefrontsize.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.fmt-error.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.index.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id-unsupported-calling-convention.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.ll
M llvm/test/CodeGen/AMDGPU/llvm.deoptimize.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.modf.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.pow-gfx9.ll
M llvm/test/CodeGen/AMDGPU/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.ll
M llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/lo16-hi16-illegal-copy.mir
M llvm/test/CodeGen/AMDGPU/lo16-hi16-physreg-copy.mir
M llvm/test/CodeGen/AMDGPU/lo16-lo16-physreg-copy-agpr.mir
M llvm/test/CodeGen/BPF/sink-min-max.ll
M llvm/test/CodeGen/Hexagon/autohvx/conv-fp-fp.ll
M llvm/test/CodeGen/RISCV/clmul.ll
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
M llvm/test/CodeGen/SystemZ/vec-max-05.ll
M llvm/test/CodeGen/SystemZ/vec-max-min-zerosplat.ll
M llvm/test/CodeGen/SystemZ/vec-min-05.ll
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
M llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
M llvm/test/CodeGen/X86/bitcnt-false-dep.ll
M llvm/test/CodeGen/X86/bitreverse.ll
A llvm/test/CodeGen/X86/bls-false-dep.ll
M llvm/test/CodeGen/X86/clmul.ll
A llvm/test/CodeGen/X86/compress-false-deps.ll
A llvm/test/CodeGen/X86/expand-false-deps.ll
A llvm/test/CodeGen/X86/large-eh-encoding.ll
R llvm/test/CodeGen/X86/pr142937.ll
M llvm/test/CodeGen/X86/slow-unaligned-mem.ll
A llvm/test/CodeGen/X86/type-tests-must-be-lowered.ll
M llvm/test/CodeGen/X86/win64-eh-unwindv3-split-large.ll
M llvm/test/CodeGen/X86/x86-prefer-no-gather-no-scatter.ll
A llvm/test/MC/AArch64/large-eh-encoding.s
A llvm/test/MC/AMDGPU/amdgcn-target-directive-conflict.s
M llvm/test/MC/AMDGPU/amdgcn-target-directive-subarch-cpu-field.s
M llvm/test/MC/AMDGPU/amdgcn-target-directive-triple-env.s
M llvm/test/MC/AMDGPU/hsa-diag-v4.s
M llvm/test/MC/AMDGPU/hsa-exp.s
M llvm/test/MC/AMDGPU/hsa-gfx12-v4.s
M llvm/test/MC/AMDGPU/hsa-gfx13-v4.s
M llvm/test/MC/AMDGPU/hsa-tg-split.s
M llvm/test/MC/AMDGPU/hsa-v4.s
M llvm/test/MC/AMDGPU/hsa-v5-uses-dynamic-stack.s
M llvm/test/MC/AMDGPU/isa-version-hsa.s
M llvm/test/MC/AMDGPU/isa-version-pal.s
M llvm/test/MC/AMDGPU/isa-version-unk.s
M llvm/test/MC/ELF/AMDGPU/cfi.s
A llvm/test/MC/X86/large-eh-encoding.s
A llvm/test/Object/X86/irsymtab-large-common.ll
M llvm/test/Object/X86/irsymtab.ll
M llvm/test/Transforms/ConstraintElimination/induction-condition-in-loop-exit.ll
M llvm/test/Transforms/ConstraintElimination/loops-header-tested-pointer-cmps.ll
A llvm/test/Transforms/Inline/X86/always-inline-incompatible-target-features.ll
M llvm/test/Transforms/Inline/always-inline-phase-ordering.ll
M llvm/test/Transforms/Inline/byval.ll
M llvm/test/Transforms/LoopVectorize/RISCV/early-exit-live-out.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-prune-vf.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-access-wide-stride.ll
A llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-unroll.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
M llvm/test/Transforms/LoopVectorize/VPlan/RISCV/expand-scev.ll
A llvm/test/Transforms/LoopVectorize/X86/x86-prefer-no-gather.ll
A llvm/test/Transforms/LoopVectorize/X86/x86-prefer-no-scatter.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-abs.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-saddo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-ssat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-uaddo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add-usat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-add.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-div.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fix.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-mul-smulo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-mul-umulo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-mul.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-scmp.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-smax.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-smin.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-ssat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-ssubo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-usat.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub-usubo.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-sub.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-ucmp.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-umax.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-umin.ll
M llvm/test/Transforms/SLPVectorizer/X86/fabs.ll
M llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll
M llvm/test/Transforms/SLPVectorizer/X86/fma.ll
M llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
M llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
M llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
M llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
M llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
M llvm/test/Transforms/SLPVectorizer/X86/fround.ll
M llvm/test/Transforms/SLPVectorizer/X86/shift-ashr.ll
M llvm/test/Transforms/SLPVectorizer/X86/shift-lshr.ll
M llvm/test/Transforms/SLPVectorizer/X86/shift-shl.ll
M llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
M llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
A llvm/test/Transforms/SLPVectorizer/X86/x86-prefer-no-gather.ll
A llvm/test/Verifier/amdgpu-expected-active-lanes.ll
A llvm/test/tools/llvm-ar/zos-write.test
M llvm/tools/llvm-ar/llvm-ar.cpp
M llvm/unittests/CodeGen/RematerializerTest.cpp
M llvm/unittests/ProfileData/SampleProfTest.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/utils/gn/secondary/llvm/version.gni
M llvm/utils/lit/lit/__init__.py
M llvm/utils/lit/lit/builtin_commands/cat.py
M llvm/utils/lit/lit/cl_arguments.py
M llvm/utils/lit/lit/main.py
M llvm/utils/lit/lit/util.py
A llvm/utils/lit/tests/Inputs/time-tests/b.txt
A llvm/utils/lit/tests/Inputs/time-tests/c.txt
M llvm/utils/lit/tests/time-tests.py
M llvm/utils/mlgo-utils/mlgo/__init__.py
M llvm/utils/profcheck-xfail.txt
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPUOps.td
M mlir/include/mlir/Dialect/OpenACC/Analysis/OpenACCSupport.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsGPU.h
A mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsReduction.h
M mlir/include/mlir/TableGen/Format.h
M mlir/lib/Conversion/EmitCCommon/TypeConverter.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/lib/Conversion/NVGPUToNVVM/CMakeLists.txt
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/NVGPU/IR/NVGPUDialect.cpp
M mlir/lib/Dialect/OpenACC/Analysis/OpenACCSupport.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCRecipeMaterialization.cpp
M mlir/lib/Dialect/OpenACC/Utils/CMakeLists.txt
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsGPU.cpp
A mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsReduction.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Conversion/FuncToEmitC/func-to-emitc-failed.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-dealloc.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-load-store.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-copy.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-failed.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc.mlir
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-extf-large.mlir
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-extf.mlir
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-truncf-large.mlir
A mlir/test/Conversion/NVGPUToNVVM/nvgpu-truncf.mlir
M mlir/test/Dialect/LLVMIR/nvvm.mlir
A mlir/test/Dialect/NVGPU/nvgpu-extf-invalid.mlir
A mlir/test/Dialect/NVGPU/nvgpu-truncf-invalid.mlir
M mlir/test/Dialect/OpenACC/acc-recipe-materialization-reduction.mlir
M mlir/test/Target/LLVMIR/Import/function-attributes.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
M mlir/unittests/Dialect/OpenACC/CMakeLists.txt
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsGPUTest.cpp
A mlir/unittests/Dialect/OpenACC/OpenACCUtilsReductionTest.cpp
M offload/ci/openmp-offload-amdgpu-libc-runtime.py
M openmp/runtime/src/kmp_utility.cpp
M orc-rt/include/orc-rt-c/Logging.h
M orc-rt/include/orc-rt/AllocAction.h
M orc-rt/include/orc-rt/Compiler.h
R orc-rt/lib/executor/AllocAction.cpp
M orc-rt/lib/executor/CMakeLists.txt
M orc-rt/lib/executor/Logging.cpp
M orc-rt/lib/executor/SimpleNativeMemoryMap.cpp
M orc-rt/test/regression/logging/os_log/delivery.test
M orc-rt/test/tools/orc-rt-log-check.cpp
M orc-rt/test/unit/AllocActionTest.cpp
M orc-rt/test/unit/CMakeLists.txt
M orc-rt/test/unit/CommonTestUtils.h
A orc-rt/test/unit/CompilerTest.cpp
M orc-rt/test/unit/LoggingTest.cpp
M polly/lib/Support/RegisterPasses.cpp
M utils/bazel/llvm-project-overlay/clang-tools-extra/clang-doc/BUILD.bazel
M utils/bazel/llvm-project-overlay/compiler-rt/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Rebase, clean up
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/a6ca941ac9b4...53da48fbaa9e
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