[all-commits] [llvm/llvm-project] bf0863: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Tue Jul 14 04:56:12 PDT 2026 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bf086335b25387ed7496577eb027531ea287f524
      https://github.com/llvm/llvm-project/commit/bf086335b25387ed7496577eb027531ea287f524
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-14 (Tue, 14 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot4.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.dwordx3.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.dwordx3.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.trig.preop.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot4.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.shuffle.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wavefrontsize.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.fmt-error.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1251.w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1251.w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.index.gfx1250.w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id-unsupported-calling-convention.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ptr.ll
    M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.cos.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.cos.ll
    M llvm/test/CodeGen/AMDGPU/llvm.deoptimize.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
    M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.err.ll
    M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
    M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
    M llvm/test/CodeGen/AMDGPU/llvm.get.rounding.ll
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
    M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.memcpy.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.modf.ll
    M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
    M llvm/test/CodeGen/AMDGPU/llvm.pow-gfx9.ll
    M llvm/test/CodeGen/AMDGPU/llvm.powi.ll
    M llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
    M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
    M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.rint.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.rint.ll
    M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.round.ll
    M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
    M llvm/test/CodeGen/AMDGPU/llvm.sin.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.sin.ll
    M llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
    M llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
    M llvm/test/CodeGen/AMDGPU/lo16-hi16-illegal-copy.mir
    M llvm/test/CodeGen/AMDGPU/lo16-hi16-physreg-copy.mir
    M llvm/test/CodeGen/AMDGPU/lo16-lo16-physreg-copy-agpr.mir

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (22) (#209213)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to 
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping 
the redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



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