[all-commits] [llvm/llvm-project] 269820: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Tue Jul 14 04:33:11 PDT 2026 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 269820947e948a4e4bd0b3e352b6c2bd77525e83
      https://github.com/llvm/llvm-project/commit/269820947e948a4e4bd0b3e352b6c2bd77525e83
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-14 (Tue, 14 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.decperflevel.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.get.waveid.in.workgroup.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.incperflevel.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memtime.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.monitor.sleep.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.nop.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sethalt.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.inc.wg.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.ttracedata.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.gfx12.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.gfx1250.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt_gfx1250.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.hi.u8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.u16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.u8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.iterative.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot2.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.lds.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.tfe.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.gfx950.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.ll

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (21) (#209212)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to 
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping 
the redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



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