[all-commits] [llvm/llvm-project] 24c3ea: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Tue Jul 14 03:57:30 PDT 2026 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 24c3eaa9ccaffca94e4d82a312fcc4ed13e62476
      https://github.com/llvm/llvm-project/commit/24c3eaa9ccaffca94e4d82a312fcc4ed13e62476
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-14 (Tue, 14 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/limit-soft-clause-reg-pressure.mir
    M llvm/test/CodeGen/AMDGPU/literal-constant-like-operand-instruction-size.ll
    M llvm/test/CodeGen/AMDGPU/literal64.ll
    M llvm/test/CodeGen/AMDGPU/live-interval-bug-in-rename-independent-subregs.mir
    M llvm/test/CodeGen/AMDGPU/liveout-implicit-def-subreg-redef-blender-verifier-error.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.add.min.max.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.addrspacecast.nonnull.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load-last-use.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.lds.err.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.dwordx3.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.id.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.flat.id.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.id.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-agent.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-basic.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-singlethread.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-system.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-wavefront.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-workgroup.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f32.fp8.err.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.e5m3.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.off.f32.i4.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.pk.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dot4.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.add.gs.reg.rtn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.append.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.async.barrier.arrive.b64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.fi.b32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.push.pop.rtn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.rtn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.consume.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-bundle.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.br.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.p.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.v.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add-errors.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add-unsupported.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx11.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.read.tr.gfx950.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.sub.gs.reg.rtn.ll

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (18) (#209121)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to 
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping 
the redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



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