[all-commits] [llvm/llvm-project] 4d5bc9: [SelectionDAG] Improve `CLMUL` lowering for `Promo...

[Sean Clarke via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4d5bc903c8a79fbadb62d8dd1e7cc93ad7a394fd
      https://github.com/llvm/llvm-project/commit/4d5bc903c8a79fbadb62d8dd1e7cc93ad7a394fd
  Author: Sean Clarke <sclarke at tenstorrent.com>
  Date:   2026-07-13 (Mon, 13 Jul 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/test/CodeGen/AArch64/clmul.ll
    M llvm/test/CodeGen/RISCV/clmul.ll
    M llvm/test/CodeGen/X86/clmul.ll

  Log Message:
  -----------
  [SelectionDAG] Improve `CLMUL` lowering for `Promote` types wider than register width (#209265)

For `ISD::CLMUL`, add a check to `PromoteIntRes_CLMUL` to take advantage
of the cross-product expansion in `ExpandIntRes_CLMUL` when possible for
`Promote` types which are wider than the register width (e.g. `i96` for
64-bit registers).



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