[all-commits] [llvm/llvm-project] 51b2a5: [RISCV][P-ext] Fix incorrect shift mask on variabl...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 51b2a5de73637e7d93cc066ced669d5db2bd8775
      https://github.com/llvm/llvm-project/commit/51b2a5de73637e7d93cc066ced669d5db2bd8775
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-07-13 (Mon, 13 Jul 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
    M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
    M llvm/test/CodeGen/RISCV/rvp-simd-64.ll

  Log Message:
  -----------
  [RISCV][P-ext] Fix incorrect shift mask on variable shift instructions. (#209293)

The instructions are defined to read 5 bits regardless of element size.

I think we will also need to change the C intrinsics to allow 5 bit
shift amounts, but we can do that in a separate patch.



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