[all-commits] [llvm/llvm-project] 84804d: [LegalizeTypes] Improve promotion of variable rota...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 84804d9a0bd7fcdaf8d218d3385b58d012c1129e
      https://github.com/llvm/llvm-project/commit/84804d9a0bd7fcdaf8d218d3385b58d012c1129e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-07-13 (Mon, 13 Jul 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/test/CodeGen/AArch64/expand-vector-rot.ll
    M llvm/test/CodeGen/AArch64/fsh.ll
    M llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
    M llvm/test/CodeGen/AMDGPU/rotl.ll
    M llvm/test/CodeGen/AMDGPU/rotr.ll
    M llvm/test/CodeGen/ARM/funnel-shift-rot.ll
    M llvm/test/CodeGen/Mips/funnel-shift-rot.ll
    M llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
    M llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/rotl-rotr.ll

  Log Message:
  -----------
  [LegalizeTypes] Improve promotion of variable rotates. (#208610)

If the promoted type is at least 2x the original type, we can
concat the value with itself into the promoted bits and use a
shl/srl. This is easier than negating the shift amount for the
(or (shl), (srl)) expansion. This is what we do for promoting
funnel shifts and really a rotate is a special case of funnel shift.



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