[all-commits] [llvm/llvm-project] fd3d20: [RISCV] Add SelectAddrRegImm26 isel complex patter...

[Garvit Gupta via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fd3d20f13f4d29eb99ada5fb9c6c87c6dee6ed17
      https://github.com/llvm/llvm-project/commit/fd3d20f13f4d29eb99ada5fb9c6c87c6dee6ed17
  Author: Garvit Gupta <garvgupt at qti.qualcomm.com>
  Date:   2026-07-13 (Mon, 13 Jul 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    A llvm/test/CodeGen/RISCV/xqcilo-addr-regimm26.ll

  Log Message:
  -----------
  [RISCV] Add SelectAddrRegImm26 isel complex pattern for Xqcilo 26-bit load/store (#207363)

Introduce a dedicated SelectAddrRegImm26 ComplexPattern for the Qualcomm
Xqcilo large-offset load/store instructions (qc.e.lw/qc.e.sw), whose
offset
field is 26 bits wide, and use it in the QC48LdPat/QC48StPat patterns
instead
of the generic AddLike + simm26_nosimm12 match.

SelectAddrRegImm26 handles addresses of the form:
- simm12 offsets are left to the standard (shorter/compressible)
load/store.
 - 26-bit (non-simm12) offsets fold directly into qc.e.lw/qc.e.sw.
 - Offsets just outside the 26-bit range are split with ADDI plus a
   folded 26-bit remainder.

Assisted by claude



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