[all-commits] [llvm/llvm-project] 72ab2a: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Mon Jul 13 08:03:26 PDT 2026 

  Branch: refs/heads/users/arsenm/llvm/amdgpu-migrate-tests-subarch-22
  Home:   https://github.com/llvm/llvm-project
  Commit: 72ab2a023e9972af6d44b33e2635b18b766a33f6
      https://github.com/llvm/llvm-project/commit/72ab2a023e9972af6d44b33e2635b18b766a33f6
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-13 (Mon, 13 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/lo16-lo16-physreg-copy-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
    M llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
    M llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
    M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
    M llvm/test/CodeGen/AMDGPU/load-global-f64.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i1.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i64.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
    M llvm/test/CodeGen/AMDGPU/load-global-invariant.ll
    M llvm/test/CodeGen/AMDGPU/load-hi16.ll
    M llvm/test/CodeGen/AMDGPU/load-lo16.ll
    M llvm/test/CodeGen/AMDGPU/load-local-f32-no-ds128.ll
    M llvm/test/CodeGen/AMDGPU/load-local-f32.ll
    M llvm/test/CodeGen/AMDGPU/load-local-f64.ll
    M llvm/test/CodeGen/AMDGPU/load-local-i1.ll
    M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-local-i32.ll
    M llvm/test/CodeGen/AMDGPU/load-local-i64.ll
    M llvm/test/CodeGen/AMDGPU/load-local-i8.ll
    M llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
    M llvm/test/CodeGen/AMDGPU/load-local.128.ll
    M llvm/test/CodeGen/AMDGPU/load-local.96.ll
    M llvm/test/CodeGen/AMDGPU/load-range-metadata-assert.ll
    M llvm/test/CodeGen/AMDGPU/load-range-metadata-sign-bits.ll
    M llvm/test/CodeGen/AMDGPU/load-saddr-offset-imm.ll
    M llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
    M llvm/test/CodeGen/AMDGPU/load-store-cnt.ll
    M llvm/test/CodeGen/AMDGPU/load-store-opt-addc0.mir
    M llvm/test/CodeGen/AMDGPU/load-store-opt-dlc.mir
    M llvm/test/CodeGen/AMDGPU/load-store-opt-ds-regclass-constrain.mir
    M llvm/test/CodeGen/AMDGPU/load-store-opt-scale-offset.mir
    M llvm/test/CodeGen/AMDGPU/load-store-opt-scc.mir
    M llvm/test/CodeGen/AMDGPU/load-weird-sizes.ll
    M llvm/test/CodeGen/AMDGPU/local-64.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
    M llvm/test/CodeGen/AMDGPU/local-atomics.ll
    M llvm/test/CodeGen/AMDGPU/local-atomics64.ll
    M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
    M llvm/test/CodeGen/AMDGPU/local-memory.ll
    M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
    M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
    M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
    M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
    M llvm/test/CodeGen/AMDGPU/local-stack-alloc-sort-framerefs.mir
    M llvm/test/CodeGen/AMDGPU/local-stack-slot-offset.ll
    M llvm/test/CodeGen/AMDGPU/loop-header-align-gfx950.mir
    M llvm/test/CodeGen/AMDGPU/loop-idiom.ll
    M llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll
    M llvm/test/CodeGen/AMDGPU/loop-on-function-argument.ll
    M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
    M llvm/test/CodeGen/AMDGPU/loop-prefetch.ll
    M llvm/test/CodeGen/AMDGPU/loop_break.ll
    M llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
    M llvm/test/CodeGen/AMDGPU/loop_header_nopred.mir
    M llvm/test/CodeGen/AMDGPU/lower-brcond-with-xor.ll
    M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-dead-intrinsics.ll
    M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-lastuse-metadata.ll
    M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
    M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
    M llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
    M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-declaration.ll
    M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-existing.ll
    M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll
    M llvm/test/CodeGen/AMDGPU/lower-empty-ctor-dtor.ll
    M llvm/test/CodeGen/AMDGPU/lower-i1-copies-clear-kills.mir
    M llvm/test/CodeGen/AMDGPU/lower-i1-copies-implicit-def-unstructured-loop.mir
    M llvm/test/CodeGen/AMDGPU/lower-indirect-lds-references.ll
    M llvm/test/CodeGen/AMDGPU/lower-intrinsics-noalias-metadata.ll
    M llvm/test/CodeGen/AMDGPU/lower-kernel-and-module-lds.ll
    M llvm/test/CodeGen/AMDGPU/lower-kernel-arguments-noalias-call-no-ptr-args.ll
    M llvm/test/CodeGen/AMDGPU/lower-kernel-lds-constexpr.ll
    M llvm/test/CodeGen/AMDGPU/lower-kernel-lds-super-align.ll
    M llvm/test/CodeGen/AMDGPU/lower-kernel-lds.ll
    M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
    M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-merge.ll
    M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
    M llvm/test/CodeGen/AMDGPU/lower-lds-with-alias-scope.ll
    M llvm/test/CodeGen/AMDGPU/lower-lds-with-noalias.ll
    M llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics-threshold.ll
    M llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (23)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



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