[all-commits] [llvm/llvm-project] 52a905: [AMDGPU] Add pre-commit test demonstrating current...

[Pankaj Dwivedi via All-commits]

  Branch: refs/heads/users/Pankajdwivedi-25/Fix-div-phi-one-input
  Home:   https://github.com/llvm/llvm-project
  Commit: 52a905b1fd0e53e3917ff5f323eb6faf06cd5020
      https://github.com/llvm/llvm-project/commit/52a905b1fd0e53e3917ff5f323eb6faf06cd5020
  Author: padivedi <pankajkumar.divedi at amd.com>
  Date:   2026-07-13 (Mon, 13 Jul 2026)

  Changed paths:
    A llvm/test/CodeGen/AMDGPU/divergent-loop-i1-lane-mask.ll
    A llvm/test/CodeGen/AMDGPU/si-annotate-loop-i1-lane-mask.ll

  Log Message:
  -----------
  [AMDGPU] Add pre-commit test demonstrating current control-flow lowering (NFC)


  Commit: 0b65a075761c2468db37fe14657a25ff5d558b25
      https://github.com/llvm/llvm-project/commit/0b65a075761c2468db37fe14657a25ff5d558b25
  Author: padivedi <pankajkumar.divedi at amd.com>
  Date:   2026-07-13 (Mon, 13 Jul 2026)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
    M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
    M llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/control-flow-intrinsics.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
    M llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll
    M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
    M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
    M llvm/test/CodeGen/AMDGPU/div_i128.ll
    M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
    M llvm/test/CodeGen/AMDGPU/diverge-switch-default.ll
    M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
    M llvm/test/CodeGen/AMDGPU/divergent-loop-i1-lane-mask.ll
    M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
    M llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll
    M llvm/test/CodeGen/AMDGPU/literal64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/loop-on-function-argument.ll
    M llvm/test/CodeGen/AMDGPU/loop_break.ll
    M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
    M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
    M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
    M llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
    M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
    M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
    M llvm/test/CodeGen/AMDGPU/rem_i128.ll
    M llvm/test/CodeGen/AMDGPU/sdiv64.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-dbg-info.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-loop-i1-lane-mask.ll
    M llvm/test/CodeGen/AMDGPU/si-annotatecfg-multiple-backedges.ll
    M llvm/test/CodeGen/AMDGPU/si-unify-exit-return-unreachable.ll
    M llvm/test/CodeGen/AMDGPU/srem64.ll
    M llvm/test/CodeGen/AMDGPU/udiv64.ll
    M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
    M llvm/test/CodeGen/AMDGPU/urem64.ll
    M llvm/test/CodeGen/AMDGPU/valu-i1.ll
    M llvm/test/CodeGen/AMDGPU/wave32.ll

  Log Message:
  -----------
  [AMDGPU] Model structured control-flow lane masks as i1


Compare: https://github.com/llvm/llvm-project/compare/52a905b1fd0e%5E...0b65a075761c

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