[all-commits] [llvm/llvm-project] 8cb0e6: [AArch64][llvm][tablegen] Restrict luti6 assembly ...

[Jonathan Thackray via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8cb0e63054ce96860b12d68218eb67c97bc6c378
      https://github.com/llvm/llvm-project/commit/8cb0e63054ce96860b12d68218eb67c97bc6c378
  Author: Jonathan Thackray <jonathan.thackray at arm.com>
  Date:   2026-07-13 (Mon, 13 Jul 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    M llvm/test/MC/AArch64/SME2p3/luti6-diagnostics.s
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp

  Log Message:
  -----------
  [AArch64][llvm][tablegen] Restrict luti6 assembly (4 regs, 8-bit) to 0 <= Zn <= 7 (#200751)

The `luti6` instruction (four registers, 8-bit) should only allow
assembly of `0 <= Zn <= 7`, since there's only 3 bits for `Zn`. It
actually allows > 7:
```
   luti6 { z0.b - z3.b }, zt0, { z8 - z10 }
```
which produces a duplicate encoding to the following:
```
   luti6 { z0.b - z3.b }, zt0, { z0 - z2 }
```

Update tablegen to handle the inferred register-class naming
collision caused by adding the explicit z0-z7 ZPR3 class.



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