[all-commits] [llvm/llvm-project] 5742a3: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

Matt Arsenault via All-commits all-commits at lists.llvm.org
Sat Jul 11 13:24:05 PDT 2026 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5742a30a749a5cc9271bd5bd8945c3033285c775
      https://github.com/llvm/llvm-project/commit/5742a30a749a5cc9271bd5bd8945c3033285c775
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-11 (Sat, 11 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_single_lane.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_store_local.ll
    M llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll
    M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
    M llvm/test/CodeGen/AMDGPU/atomicrmw-nand.ll
    M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
    M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
    M llvm/test/CodeGen/AMDGPU/atomics-cas-remarks-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
    M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
    M llvm/test/CodeGen/AMDGPU/attr-amdgpu-align.ll
    M llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
    M llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll
    M llvm/test/CodeGen/AMDGPU/attr-amdgpu-max-num-workgroups-propagate.ll
    M llvm/test/CodeGen/AMDGPU/attr-amdgpu-max-num-workgroups.ll
    M llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
    M llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-vgpr.ll
    M llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-workgroups_error_check.ll
    M llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
    M llvm/test/CodeGen/AMDGPU/attr-unparseable.ll
    M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
    M llvm/test/CodeGen/AMDGPU/attributor-loop-issue-58639.ll
    M llvm/test/CodeGen/AMDGPU/attributor-noalias-addrspace.ll
    M llvm/test/CodeGen/AMDGPU/av-invalid-scope.ll
    M llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir
    M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
    M llvm/test/CodeGen/AMDGPU/av_movimm_pseudo_expansion.mir
    M llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
    M llvm/test/CodeGen/AMDGPU/back-off-barrier-subtarget-feature.ll
    M llvm/test/CodeGen/AMDGPU/bad-agpr-vgpr-regalloc-priority.mir
    M llvm/test/CodeGen/AMDGPU/barrier-elimination-gfx12.ll
    M llvm/test/CodeGen/AMDGPU/barrier-signal-wait-latency.ll
    M llvm/test/CodeGen/AMDGPU/basic-branch.ll
    M llvm/test/CodeGen/AMDGPU/basic-call-return.ll
    M llvm/test/CodeGen/AMDGPU/basic-loop.ll
    M llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
    M llvm/test/CodeGen/AMDGPU/bf16-math.ll
    M llvm/test/CodeGen/AMDGPU/bf16-ops.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
    M llvm/test/CodeGen/AMDGPU/bfe-i8-i16.ll
    M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
    M llvm/test/CodeGen/AMDGPU/bfi_int.ll
    M llvm/test/CodeGen/AMDGPU/bfm.ll
    M llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
    M llvm/test/CodeGen/AMDGPU/bitcast-constant-to-vector.ll
    M llvm/test/CodeGen/AMDGPU/bitcast-v4f16-v4i16.ll
    M llvm/test/CodeGen/AMDGPU/bitcast-vector-extract.ll
    M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
    M llvm/test/CodeGen/AMDGPU/bitop3-shared-operand.ll
    M llvm/test/CodeGen/AMDGPU/bitop3.ll
    M llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll
    M llvm/test/CodeGen/AMDGPU/bitreverse.ll
    M llvm/test/CodeGen/AMDGPU/blender-coalescer-verifier-error-empty-subrange.mir
    M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
    M llvm/test/CodeGen/AMDGPU/block-should-not-be-in-alive-blocks.mir
    M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
    M llvm/test/CodeGen/AMDGPU/branch-condition-and.ll
    M llvm/test/CodeGen/AMDGPU/branch-folder-requires-no-phis.mir
    M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
    M llvm/test/CodeGen/AMDGPU/branch-relax-bundle.ll
    M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
    M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
    M llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir
    M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx10-branch-offset-bug.ll
    M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
    M llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx10.ll
    M llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx11.ll
    M llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx1250.mir
    M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
    M llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir
    M llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
    M llvm/test/CodeGen/AMDGPU/bswap.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-rtn.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_cond.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_sat.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-unsupported-errors.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
    M llvm/test/CodeGen/AMDGPU/buffer-intrinsic-mmo-type.ll
    M llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
    M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
    M llvm/test/CodeGen/AMDGPU/buffer-schedule.ll
    M llvm/test/CodeGen/AMDGPU/buffer-store-dwordx4-vpk-mul-war-hazard-gfx942.mir
    M llvm/test/CodeGen/AMDGPU/bug-cselect-b64.ll

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (8) (#208837)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)



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