[all-commits] [llvm/llvm-project] d5ff29: AMDGPU: Migrate CodeGen tests to amdgpu subarch tr...

Sat Jul 11 02:22:47 PDT 2026

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d5ff29d5b4b9cd7ba446d1cff138a8e626ec27d0
      https://github.com/llvm/llvm-project/commit/d5ff29d5b4b9cd7ba446d1cff138a8e626ec27d0
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-11 (Sat, 11 Jul 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll
    M llvm/test/CodeGen/AMDGPU/a-v-ds-atomic-cmpxchg.ll
    M llvm/test/CodeGen/AMDGPU/a-v-ds-atomicrmw.ll
    M llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
    M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
    M llvm/test/CodeGen/AMDGPU/a-v-global-atomic-cmpxchg.ll
    M llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
    M llvm/test/CodeGen/AMDGPU/aa-as-infer.ll
    M llvm/test/CodeGen/AMDGPU/aa-points-to-constant-memory.ll
    M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
    M llvm/test/CodeGen/AMDGPU/abs_i16.ll
    M llvm/test/CodeGen/AMDGPU/abs_i32.ll
    M llvm/test/CodeGen/AMDGPU/absdiff.ll
    M llvm/test/CodeGen/AMDGPU/acc-ldst.ll
    M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/add-debug.ll
    M llvm/test/CodeGen/AMDGPU/add-max.ll
    M llvm/test/CodeGen/AMDGPU/add.i16.ll
    M llvm/test/CodeGen/AMDGPU/add.ll
    M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/add3.ll
    M llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll
    M llvm/test/CodeGen/AMDGPU/add_i1.ll
    M llvm/test/CodeGen/AMDGPU/add_shl.ll
    M llvm/test/CodeGen/AMDGPU/add_sub_u64_pseudos.mir
    M llvm/test/CodeGen/AMDGPU/add_u64.ll
    M llvm/test/CodeGen/AMDGPU/addrspacecast-captured.ll
    M llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
    M llvm/test/CodeGen/AMDGPU/addrspacecast-gas.ll
    M llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll
    M llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll
    M llvm/test/CodeGen/AMDGPU/addsub64_carry.ll
    M llvm/test/CodeGen/AMDGPU/adjust-writemask-cse.ll
    M llvm/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll
    M llvm/test/CodeGen/AMDGPU/adjust-writemask-vectorized.ll
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers-assertion-after-ra-failure.ll
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/agpr-copy-propagation.mir
    M llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
    M llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/agpr-csr.ll
    M llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
    M llvm/test/CodeGen/AMDGPU/agpr-remat.ll
    M llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir
    M llvm/test/CodeGen/AMDGPU/agpr-to-agpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx1250.mir
    M llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir
    M llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/alloc-all-regs-reserved-in-class.mir
    M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn-av-scopes.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn-cs-chain-intrinsic-dyn-vgpr-w32.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn-ieee.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ptr.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-accesslist-offsetbins-out-of-sync.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-branch-weight-metadata.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-break-large-phis-heuristics.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-break-large-phis.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-mul24.ll

  Log Message:
  -----------
  AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (5) (#208834)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)

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