[all-commits] [llvm/llvm-project] 2ad788: [X86][ACE] Add x86_bsr type and Block Scale Regist...

[Ganesh via All-commits]

  Branch: refs/heads/users/ganeshgit/X86ACEBSR
  Home:   https://github.com/llvm/llvm-project
  Commit: 2ad788bb7549824b8640c6808d05087362f668ec
      https://github.com/llvm/llvm-project/commit/2ad788bb7549824b8640c6808d05087362f668ec
  Author: Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian at amd.com>
  Date:   2026-07-10 (Fri, 10 Jul 2026)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsX86_64.td
    M clang/lib/CodeGen/CGBuiltin.cpp
    M clang/lib/Headers/acev1intrin.h
    M clang/test/CodeGen/X86/ace-api.c
    M llvm/include/llvm-c/Core.h
    M llvm/include/llvm/Analysis/IR2Vec.h
    M llvm/include/llvm/Bitcode/LLVMBitCodes.h
    M llvm/include/llvm/CodeGen/ValueTypes.td
    M llvm/include/llvm/IR/DataLayout.h
    M llvm/include/llvm/IR/Intrinsics.h
    M llvm/include/llvm/IR/Intrinsics.td
    M llvm/include/llvm/IR/IntrinsicsX86.td
    M llvm/include/llvm/IR/Type.h
    M llvm/include/llvm/SandboxIR/Type.h
    M llvm/lib/Analysis/ConstantFolding.cpp
    M llvm/lib/AsmParser/LLLexer.cpp
    M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
    M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
    M llvm/lib/CodeGen/ValueTypes.cpp
    M llvm/lib/IR/AsmWriter.cpp
    M llvm/lib/IR/ConstantFold.cpp
    M llvm/lib/IR/Core.cpp
    M llvm/lib/IR/DataLayout.cpp
    M llvm/lib/IR/Intrinsics.cpp
    M llvm/lib/IR/LLVMContextImpl.cpp
    M llvm/lib/IR/LLVMContextImpl.h
    M llvm/lib/IR/Type.cpp
    M llvm/lib/IR/TypedPointerType.cpp
    M llvm/lib/IR/Verifier.cpp
    M llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
    M llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
    M llvm/lib/Target/X86/CMakeLists.txt
    M llvm/lib/Target/X86/X86.h
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86LowerAMXType.cpp
    A llvm/lib/Target/X86/X86LowerBSRType.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.td
    M llvm/lib/Target/X86/X86TargetMachine.cpp
    M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
    M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
    A llvm/test/Assembler/x86_bsr.ll
    A llvm/test/CodeGen/X86/ACE/ace-bsr-ordering.ll
    A llvm/test/CodeGen/X86/ACE/ace-internal-intrinsics.ll
    M llvm/test/CodeGen/X86/O0-pipeline.ll
    M llvm/test/CodeGen/X86/opt-pipeline.ll
    M llvm/test/Instrumentation/Instrumentor/alloca_and_function.ll
    M llvm/test/Instrumentation/Instrumentor/cast.ll
    M llvm/test/Instrumentation/Instrumentor/cast_crash.ll
    M llvm/test/Instrumentation/Instrumentor/compare.ll
    M llvm/test/Instrumentation/Instrumentor/load_store.ll
    M llvm/test/Instrumentation/Instrumentor/load_store_args.ll
    M llvm/test/Instrumentation/Instrumentor/load_store_noreplace.ll
    M llvm/test/Instrumentation/Instrumentor/module_and_globals.ll
    M llvm/test/Instrumentation/Instrumentor/numeric.ll
    M llvm/test/Instrumentation/Instrumentor/numeric_subtypeid.ll
    M llvm/test/TableGen/CPtrWildcard.td
    M llvm/test/TableGen/x86-fold-tables.inc
    A llvm/test/Verifier/x86_bsr.ll
    M llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
    M llvm/utils/TableGen/X86ManualFoldTables.def

  Log Message:
  -----------
  [X86][ACE] Add x86_bsr type and Block Scale Register support

This patch adds comprehensive support for the Block Scale Register (BSR),
a 1024-bit architectural register used by ACE (AI Compute Extensions) for
storing scale factors in mixed-precision matrix operations.

- Add x86_bsr as an IR type and update similar to x86_amx

Intrinsics Infrastructure:
- Add x86_bsr intrinsics in IntrinsicsX86.td:
  - bsrmovf: Store both halves to hardware BSR
  - bsrmovh_set/bsrmovl_set: Store individual halves
  - bsrmovh_get/bsrmovl_get: Read individual halves
  - bsr_create: Create x86_bsr from two 512-bit vectors
  - Conversion intrinsics between x86_bsr and vector types

X86 Backend:
- Add X86LowerBSRType pass to lower x86_bsr SSA values to implicit
  hardware register operations (similar to X86LowerAMXType)
- Handle BSR in register allocation and frame lowering
- Reserve BSR during register allocation to prevent conflicts

Header and API:
- Add __bsr struct type in acev1intrin.h bundling lo/hi 512-bit halves
- Add struct-based API: __bsr_make, __bsr_load, __bsr_store,
  __bsr_get_lo, __bsr_get_hi, __bsr_set_lo, __bsr_set_hi



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