[all-commits] [llvm/llvm-project] 509a0b: [RISCV] Support Zdinx registers in -fzero-call-use...

[Lucas Chollet via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 509a0b82038d04656eb4c0f172bb8199352b90e9
      https://github.com/llvm/llvm-project/commit/509a0b82038d04656eb4c0f172bb8199352b90e9
  Author: Lucas Chollet <lucas.chollet at free.fr>
  Date:   2026-07-09 (Thu, 09 Jul 2026)

  Changed paths:
    M llvm/lib/CodeGen/PrologEpilogInserter.cpp
    M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/test/CodeGen/RISCV/zero-call-used-regs.ll

  Log Message:
  -----------
  [RISCV] Support Zdinx registers in -fzero-call-used-regs (#206323)

First, this patch makes the backend consider GPRF16 and GPRF32 registers
as GPR. These registers are aliases of normal GPR but for use with the
Zdinx extension (floating points instructions on GPR).

Second, it teaches the general -fzero-call-used-regs logic to handle
used registers that span over multiple physical registers. One example
of this is `GPRPair` in the RISC-V backend.



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