[all-commits] [llvm/llvm-project] d64006: [AMDGPU][test] Split slow lit tests for better par...

[Manuel Carrasco via All-commits]

  Branch: refs/heads/users/mgcarrasco/lit-speed-up
  Home:   https://github.com/llvm/llvm-project
  Commit: d6400601fc65795ea8e343ffb7e5b3de1f9690bb
      https://github.com/llvm/llvm-project/commit/d6400601fc65795ea8e343ffb7e5b3de1f9690bb
  Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
  Date:   2026-07-09 (Thu, 09 Jul 2026)

  Changed paths:
    A llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.gfx11.ll
    A llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.gfx9.ll
    R llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    A llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.si.ll
    A llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.vi.ll
    A llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.gfx11.ll
    A llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.gfx9.ll
    R llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
    A llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.si.ll
    A llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.vi.ll
    A llvm/test/CodeGen/AMDGPU/bf16-gfx1010.ll
    A llvm/test/CodeGen/AMDGPU/bf16-gfx11.ll
    A llvm/test/CodeGen/AMDGPU/bf16-gfx1250.ll
    A llvm/test/CodeGen/AMDGPU/bf16-gfx600.ll
    A llvm/test/CodeGen/AMDGPU/bf16-gfx7.ll
    A llvm/test/CodeGen/AMDGPU/bf16-gfx8.ll
    A llvm/test/CodeGen/AMDGPU/bf16-gfx9.ll
    R llvm/test/CodeGen/AMDGPU/bf16.ll
    A llvm/test/CodeGen/AMDGPU/memintrinsic-unroll-aligned.memcpy_p0_p0_sz2048.ll
    A llvm/test/CodeGen/AMDGPU/memintrinsic-unroll-aligned.memcpy_p0_p4_sz2048.ll
    A llvm/test/CodeGen/AMDGPU/memintrinsic-unroll-aligned.memcpy_p0_p5_sz2048.ll
    A llvm/test/CodeGen/AMDGPU/memintrinsic-unroll-aligned.memcpy_p1_p1_sz2048.ll
    A llvm/test/CodeGen/AMDGPU/memintrinsic-unroll-aligned.memcpy_p5_p5_sz2048.ll
    A llvm/test/CodeGen/AMDGPU/memintrinsic-unroll-aligned.memmove_p0_p0_sz2048.ll
    A llvm/test/CodeGen/AMDGPU/memintrinsic-unroll-aligned.memmove_p0_p4_sz2048.ll
    A llvm/test/CodeGen/AMDGPU/memintrinsic-unroll-aligned.memmove_p0_p5_sz2048.ll
    A llvm/test/CodeGen/AMDGPU/memintrinsic-unroll-aligned.memmove_p1_p1_sz2048.ll
    A llvm/test/CodeGen/AMDGPU/memintrinsic-unroll-aligned.memmove_p5_p5_sz2048.ll
    A llvm/test/CodeGen/AMDGPU/memintrinsic-unroll-aligned.memset_p0_sz2048.ll
    A llvm/test/CodeGen/AMDGPU/memintrinsic-unroll-aligned.memset_p1_sz2048.ll
    A llvm/test/CodeGen/AMDGPU/memintrinsic-unroll-aligned.memset_p3_sz2048.ll
    A llvm/test/CodeGen/AMDGPU/memintrinsic-unroll-aligned.memset_p5_sz2048.ll
    A llvm/test/CodeGen/AMDGPU/memintrinsic-unroll-unroll3.ll
    M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
    A llvm/test/CodeGen/AMDGPU/sched-group-barrier-pipeline-solver-exact.mir
    A llvm/test/CodeGen/AMDGPU/sched-group-barrier-pipeline-solver-greedy.mir
    R llvm/test/CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir

  Log Message:
  -----------
  [AMDGPU][test] Split slow lit tests for better parallel lit throughput (NFC)

Split the slowest AMDGPU CodeGen tests into independent lit units so
llvm-lit can distribute work across available host cores.



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