[all-commits] [llvm/llvm-project] d1cd1d: X86: Fix mishandling subregisters in ndd memory fo...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Thu Jul 9 06:38:38 PDT 2026
Branch: refs/heads/users/alexey-bataev/spr/slp-support-faddfsub-as-interchangeable-instructions
Home: https://github.com/llvm/llvm-project
Commit: d1cd1de72a8f88c3b44c2eacb18146ffd3adee2e
https://github.com/llvm/llvm-project/commit/d1cd1de72a8f88c3b44c2eacb18146ffd3adee2e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
A llvm/test/CodeGen/X86/apx/peephole-fold-subreg-tied-copy.mir
Log Message:
-----------
X86: Fix mishandling subregisters in ndd memory fold (#207997)
Defends against regressions in a future change.
Commit: 3c7727f1269e5986915aacf4ee1ae117843bd573
https://github.com/llvm/llvm-project/commit/3c7727f1269e5986915aacf4ee1ae117843bd573
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libc/src/spawn/linux/CMakeLists.txt
M libc/src/spawn/linux/posix_spawn.cpp
Log Message:
-----------
[libc] Use the dup2 syscall wrapper in posix_spawn (#207879)
posix_spawn's local dup2 helper fell back to a bare dup3 on targets
without SYS_dup2. dup3 fails with EINVAL when oldfd == newfd, where dup2
must instead return oldfd if it is valid, so
posix_spawn_file_actions_adddup2 with equal fds misbehaved on those
targets. linux_syscalls::dup2 already implements the correct fallback,
so call it directly and drop the local helper.
Commit: e16c737a52fa9c5144299282f4da519e898af2a5
https://github.com/llvm/llvm-project/commit/e16c737a52fa9c5144299282f4da519e898af2a5
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
A llvm/test/CodeGen/SPIRV/instructions/phi-aggregate-call.ll
A llvm/test/CodeGen/SPIRV/instructions/phi-aggregate-with-overflow-zeroinitializer.ll
A llvm/test/CodeGen/SPIRV/instructions/phi-aggregate-with-overflow.ll
A llvm/test/CodeGen/SPIRV/instructions/select-freeze-aggregate-with-overflow.ll
Log Message:
-----------
[SPIRV] Expand aggregate instructions with mutated-type uses (#206835)
This is a workaround for the problem in GH issue
https://github.com/llvm/llvm-project/issues/203586.
The problem is that we need to mutate aggregate-typed PHI nodes to
`i32`, however that means all incoming values need to have a matching
type, but we can't always easily mutate the incoming types to i32, as in
the case in the GH issue with a math intrinsic that returns a struct
by-value.
We do the same mutation for some other cases like `freeze`, the
workaround is the same.
The workaround is to expand the incoming values to a form that will also
be mutated to i32 so the types match. An example transformation is
below:
Before
```
...
bb1: ; preds = %entry
%0 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
br label %epilog
...
%2 = phi { i64, i1 } [ %1, %bb0 ], [ %0, %bb1 ]
```
After
```
...
bb1: ; preds = %entry
%0 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
%1 = extractvalue { i64, i1 } %0, 0
%2 = insertvalue { i64, i1 } poison, i64 %1, 0
%3 = extractvalue { i64, i1 } %0, 1
%4 = insertvalue { i64, i1 } %2, i1 %3, 1
br label %epilog
...
%10 = phi { i64, i1 } [ %9, %bb0 ], [ %4, %bb1 ]
```
`insertvalue` get replaced with a SPIR-V intrinsic later in the pass
which is also type-mutated, so the IR is correct:
```
...
bb1: ; preds = %entry
%0 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
call void @llvm.spv.value.md(metadata !0)
call void (...) @llvm.fake.use({ i64, i1 } %0)
%1 = extractvalue { i64, i1 } %0, 0
call void @llvm.spv.assign.type.i64(i64 %1, metadata i64 poison)
call void @llvm.spv.assign.type.i32(i32 undef, metadata { i64, i1 } poison)
%2 = call i32 (i32, i64, ...) @llvm.spv.insertv.i64(i32 undef, i64 %1, i32 0)
call void @llvm.spv.assign.type.i32(i32 %2, metadata { i64, i1 } poison)
%3 = extractvalue { i64, i1 } %0, 1
call void @llvm.spv.assign.type.i1(i1 %3, metadata i1 poison)
%4 = call i32 (i32, i1, ...) @llvm.spv.insertv.i1(i32 %2, i1 %3, i32 1)
call void @llvm.spv.assign.type.i32(i32 %4, metadata { i64, i1 } poison)
br label %epilog
...
%10 = phi i32 [ %9, %bb0 ], [ %4, %bb1 ]
```
This is the simplest change I could come up with, my other ideas were
much more complicated and/or risky.
This fix is important for us because this pattern comes up in libc's
implementation on FMA, so this is blocking SPIR-V libc support.
Fixes: https://github.com/llvm/llvm-project/issues/203586
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: cb668bb3632d06bbcd736ec8999811c8b6b06dd5
https://github.com/llvm/llvm-project/commit/cb668bb3632d06bbcd736ec8999811c8b6b06dd5
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
A llvm/test/CodeGen/SPIRV/capability-Int64Atomics-weak-cmpxchg.ll
Log Message:
-----------
[SPIR-V] Add missing Int64Atomics requirement for OpAtomicCompareExchangeWeak (#207965)
Commit: 250a554f05e54f2bf4f2c2ba736ed2e06429aba2
https://github.com/llvm/llvm-project/commit/250a554f05e54f2bf4f2c2ba736ed2e06429aba2
Author: Matthew Devereau <matthew.devereau at arm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-cmpeq.ll
Log Message:
-----------
[AArch64][InstCombine] Fold xor(cmpeq, pg) to cmpne (#207759)
Extend the existing xor(cmpne(pg, lhs, rhs), pg) fold to also handle
cmpeq to cmpne
Commit: 999b3cfbe21747aa952f79814e7dfd1a7b3fd891
https://github.com/llvm/llvm-project/commit/999b3cfbe21747aa952f79814e7dfd1a7b3fd891
Author: Ankit Kumar Tiwari <141545455+ankit-cybertron at users.noreply.github.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
A llvm/test/CodeGen/RISCV/rvv/vecreduce-add-constant-fold.ll
Log Message:
-----------
[SelectionDAG] Fold VECREDUCE_ADD of a constant BUILD_VECTOR (#207560)
This PR implements constant folding for ISD::VECREDUCE_ADD when the
input is a BUILD_VECTOR of integer constants. The fold computes the sum
at compile time using APInt arithmetic and returns a folded constant
scalar, instead of emitting real vector materialization and reduction
instructions for a value that's already known.
Folding is skipped if any element is undef or opaque, since the result
can't be assumed at compile time in that case.
Fixes #206743
Commit: 047b145c0cfe2ebcf73694f0ab39a0fc11dc9d09
https://github.com/llvm/llvm-project/commit/047b145c0cfe2ebcf73694f0ab39a0fc11dc9d09
Author: hulxv <hulxxv at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libc/shared/builtins.h
A libc/shared/builtins/mulsf3.h
M libc/src/__support/builtins/CMakeLists.txt
A libc/src/__support/builtins/mulsf3.h
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_builtins_test.cpp
Log Message:
-----------
[libc] add shared mulsf3 builtin (#205678)
Re-exposes LLVM-libc's `__mulsf3` as `shared::mulsf3` for reuse by
compiler-rt's builtins.
Stacked change - merge these first:
- #200094
- #205669
- #205670
- #205671
- #205672
- #205673
- #205674
- #205675
- #205676
- #205677
Part of #197824
Commit: 2f7a3a032cb0ff5347135c59914733fc04b20d35
https://github.com/llvm/llvm-project/commit/2f7a3a032cb0ff5347135c59914733fc04b20d35
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/signed_arithmetic_overflow.ll
Log Message:
-----------
[SPIR-V] Fix crash on direct aggregate return of an intrinsic call result (#206491)
Commit: 012523d96b30a9a6d7148825fe307919a9c4753c
https://github.com/llvm/llvm-project/commit/012523d96b30a9a6d7148825fe307919a9c4753c
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
Log Message:
-----------
[VPlan] Support VPInstruction for intrinsic calls in live-in folding. (#207836)
Use getIntrinsicID in getOpcodeOrIntrinsicID. This enables constant
folding for VPInstructions calling intrinsics.
PR: https://github.com/llvm/llvm-project/pull/207836
Commit: 3a6d3f77960b4dded18d15e28eaa3f953be18faa
https://github.com/llvm/llvm-project/commit/3a6d3f77960b4dded18d15e28eaa3f953be18faa
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
Log Message:
-----------
[mlir][LLVM] Add arithmetic fence intrinsic op (#207975)
Add a generated LLVM dialect op for llvm.arithmetic.fence, including
LLVM IR import and export coverage for scalar and vector floating-point
forms.
Assisted-by: Codex
Commit: 43ccdbc84774da0ae4cb5131f2245a9633d977b9
https://github.com/llvm/llvm-project/commit/43ccdbc84774da0ae4cb5131f2245a9633d977b9
Author: Scott Manley <rscottmanley at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/FIRToSCF.cpp
M flang/test/Fir/FirToSCF/do-loop.fir
Log Message:
-----------
[FIRToSCF] propagate acc.par_dims during fir.do_loop conversion (#207973)
Copy any OpenACC parallel dimensions from the fir.do_loop to the scf op
Commit: 35db7fd565138b4756193b36750f052e27359baf
https://github.com/llvm/llvm-project/commit/35db7fd565138b4756193b36750f052e27359baf
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.atomic.cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir
M llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
M llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
M llvm/test/CodeGen/AMDGPU/agpr-csr.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ptr.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/and.ll
M llvm/test/CodeGen/AMDGPU/andorn2.ll
M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_cond.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir
M llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir
M llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir
M llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2_a_v.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fceil64.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.simple.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-memops.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/siloadstoreopt-misaligned-regsequence.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/ssubo.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/structurize-hoist.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
M llvm/test/CodeGen/AMDGPU/swdev380865.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
M llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/valu-i1.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/wqm.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
Log Message:
-----------
[AMDGPU] Stop adding implicit def of superreg in copyPhysReg (#125255)
Previously when copyPhysReg expanded a COPY into multiple MOV
instructions it added an implicit def of the destination superreg to the
first MOV. Removing these does not cause any liveness verification
problems and still passes Vulkan CTS for correctness testing.
Commit: 863be135eb5261fc85007492a5f26de926802a81
https://github.com/llvm/llvm-project/commit/863be135eb5261fc85007492a5f26de926802a81
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libc/src/stdio/printf_core/float_hex_converter.h
Log Message:
-----------
[libc] Fix build failure with ASSUME_ROUND_NEAREST_ONLY (#207991)
Commit 03c62ca40d19ba0 moved some local variables of
`convert_float_hex_exp` into a struct called `properties`, but didn't
edit the #ifdef branch for `LIBC_MATH_HAS_ASSUME_ROUND_NEAREST_ONLY`, so
builds with that definition failed.
Commit: 5ee85101a70dd2628d5b65a6a8a1e5d697d6c757
https://github.com/llvm/llvm-project/commit/5ee85101a70dd2628d5b65a6a8a1e5d697d6c757
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/mul-shl-nsw-intmin.ll
Log Message:
-----------
[SLP][NFC]Add tests with mul to shl transformations, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/208020
Commit: 31fc40b0904861d33b926dfd6ea04432e7690c49
https://github.com/llvm/llvm-project/commit/31fc40b0904861d33b926dfd6ea04432e7690c49
Author: Benjamin Luke <benjamin.luke at sony.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/CodeGen/Targets/X86.cpp
M clang/test/CodeGen/X86/mmx-inline-asm-error.c
A clang/test/CodeGen/target-avx-abi-diag-knr.c
M clang/test/CodeGen/target-builtin-error-3.c
M clang/test/CodeGen/target-features-error-2.c
A clang/test/CodeGenCXX/target-avx-abi-diag.cpp
M libcxx/include/__algorithm/simd_utils.h
Log Message:
-----------
[clang][X86] Emit AVX level mismatch psABI warnings on function definitions (#199091)
Emit -WpsABI for x86_64 function definitions whose return type or
parameter type uses a vector wider than 128 bits without the required
ABI feature enabled. 256-bit vectors require avx, and 512-bit vectors
require avx512f.
Previously this diagnostic was only emitted at call sites, so
definitions with wide vector signatures could be introduced without a
warning until they were called. Use the function feature map so
attribute(target("avx/avx512f")) definitions are accepted, and emit no
warnings for prototype-only declarations.
Commit: e702ecb84930e1d7d8ed1869c713566de2262a63
https://github.com/llvm/llvm-project/commit/e702ecb84930e1d7d8ed1869c713566de2262a63
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
R llvm/test/Transforms/SLPVectorizer/X86/mul-shl-nsw-intmin.ll
Log Message:
-----------
Revert "[SLP][NFC]Add tests with mul to shl transformations, NFC"
This reverts commit 5ee85101a70dd2628d5b65a6a8a1e5d697d6c757, incorrect
checks in the test
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/208022
Commit: e390e6b7a64353c72dbe1ff3f4bd3382412daca5
https://github.com/llvm/llvm-project/commit/e390e6b7a64353c72dbe1ff3f4bd3382412daca5
Author: sohail <sohailraj.satapathy at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libc/docs/headers/stdfix.rst
R libc/src/stdfix/bitusk.cpp
M libc/test/src/stdfix/CMakeLists.txt
A libc/test/src/stdfix/IdivFxTest.h
R libc/test/src/stdfix/IdivTest.h
M libc/test/src/stdfix/idivk_test.cpp
M libc/test/src/stdfix/idivlk_test.cpp
M libc/test/src/stdfix/idivlr_test.cpp
M libc/test/src/stdfix/idivr_test.cpp
M libc/test/src/stdfix/idivuk_test.cpp
M libc/test/src/stdfix/idivulk_test.cpp
M libc/test/src/stdfix/idivulr_test.cpp
M libc/test/src/stdfix/idivur_test.cpp
Log Message:
-----------
[libc][stdfix] Fix idiv* doc table, rename idivfx test helpers and remove duplicate bitsuk source (#206729)
Two small cleanups in libc/src/stdfix.
1. `idiv*` in `stdfix.rst` was marked as implemented for all 12 type
variants but only the 8 non-short width variants (ur, r, ulr, lr, uk, k,
ulk, lk) exist in the directory and are built. Updated the table to
match.
2. Removed `bitusk.cpp` which is an orphaned duplicate of `bitsuk.cpp`
with a typo in the file name. It isn't referenced in the CMakeLists.txt
and has no corresponding .h file.
3. Rename the idivfx test header and helpers.
Commit: c1822d6104d7b2cb2093a5273d6ceccd9ebb2fb1
https://github.com/llvm/llvm-project/commit/c1822d6104d7b2cb2093a5273d6ceccd9ebb2fb1
Author: Yanzuo Liu <zwuis at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/lib/Sema/SemaCXXScopeSpec.cpp
Log Message:
-----------
[clang][Sema][NFC] Improve readability in `computeDeclContext` (#208010)
Split off from #190495.
Co-authored-by: Matheus Izvekov <mizvekov at gmail.com>
Commit: 93ff6992c68766a1def33a8a074f9bce544fc102
https://github.com/llvm/llvm-project/commit/93ff6992c68766a1def33a8a074f9bce544fc102
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/mul-shl-nsw-intmin.ll
Log Message:
-----------
[SLP][NFC]Add tests with mul to shl transformations, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/208027
Commit: cde011852d0b7d08c820f7d623655e5f354a50c8
https://github.com/llvm/llvm-project/commit/cde011852d0b7d08c820f7d623655e5f354a50c8
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/mul-shl-nsw-intmin.ll
Log Message:
-----------
[SLP] Drop nsw when mul by INT_MIN is converted to shl
mul nsw X, INT_MIN is valid, but shl X, BW-1 is not nsw-safe. Drop nsw on
the vector shl when a mul lane with INT_MIN is unified into shl during
opcode interchange.
Fixes #207990
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/208028
Commit: 94a8d4cbf13810e9f4fee03488312dee8869c074
https://github.com/llvm/llvm-project/commit/94a8d4cbf13810e9f4fee03488312dee8869c074
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll
Log Message:
-----------
[AMDGPU] Clear DS aggregate in inverted sched_barrier mask when LDSDMA allowed (#207779)
The DS clause was missing the LDSDMA check that the VMEM clause has
Commit: 6053d19eb3bc2391fcab76eb20a8ea0462568224
https://github.com/llvm/llvm-project/commit/6053d19eb3bc2391fcab76eb20a8ea0462568224
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/PhaseOrdering/X86/avg.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/long-non-power-of-2.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/partial-vec-invalid-cost.ll
M llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-postpone-for-dependency.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-reused-with-bv-subvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/commutable-node-with-non-sched-parent.ll
M llvm/test/Transforms/SLPVectorizer/X86/debug-info-salvage.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-subvectors-insert.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-parent-multi-copyables.ll
M llvm/test/Transforms/SLPVectorizer/X86/recalc-copyable-operand-deps-shared-inst.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-ordered-values-update.ll
Log Message:
-----------
[SLP] Retune look-ahead scores for constants
Rescale LookAheadHeuristics scores and add ScoreSameConstants /
ScoreConstantScaleFactor so identical constants no longer score the
same as same-opcode instruction matches, fixing suboptimal operand
reordering around repeated constants (shift amounts, splat values).
Also retry a SplitVectorize alt-shuffle build for copyable-element
bundles when scheduling fails, instead of always falling back to a
gather, to fix regressions.
Reviewers: hiraditya, bababuck, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/207548
Commit: a00f7be392d9468779af59d86bed12d17aa578c0
https://github.com/llvm/llvm-project/commit/a00f7be392d9468779af59d86bed12d17aa578c0
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
M llvm/test/Transforms/SLPVectorizer/X86/c-ray.ll
M llvm/test/Transforms/SLPVectorizer/X86/delayed-gather-emission.ll
M llvm/test/Transforms/SLPVectorizer/X86/poor-throughput-seeds.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-reorder-reshuffle.ll
Log Message:
-----------
[SLP]Use poor-throughput instructions as vectorization seeds
Seed vectorization from expensive poor-throughput ops (fdiv/frem/fsqrt
and target-expensive calls) even when they do not feed a store or reduction.
Compile time effect https://llvm-compile-time-tracker.com/compare.php?from=8cdf6346f46c505928a9fb9d3ef9e8ce125a2108&to=27a3f0a5c0489c91bf386e480289fdcc9dc9c8b7&stat=instructions:u
These compile time regressions are the side effects of the vectorization
vectorization gains and cannot be reduced further (note Bullet).
Fixes #38780
Reviewers: hiraditya, bababuck, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/206518
Commit: 29f1a71a8d3f12232ccd53bca2442e35396a11a3
https://github.com/llvm/llvm-project/commit/29f1a71a8d3f12232ccd53bca2442e35396a11a3
Author: Aditya Medhane <sherlockedaditya at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M openmp/runtime/src/kmp_dispatch.h
Log Message:
-----------
[OpenMP] Remove internal linkage from __kmp_wait template (NFC) (#207983)
__kmp_wait in kmp_dispatch.h is a static function template in a header,
so any TU that includes it without instantiating it trips
-Wunused-template (kmp_runtime.cpp, kmp_affinity.cpp, kmp_global.cpp,
kmp_settings.cpp). It is used by kmp_dispatch.cpp and
kmp_dispatch_hier.h. Drop static, which the comment above it already
suggests.
Part of #202945
Commit: 72e1037c32e22759b682a0e973af6b95b0630a01
https://github.com/llvm/llvm-project/commit/72e1037c32e22759b682a0e973af6b95b0630a01
Author: AnthonyCalandraGeotab <anthonycalandra at geotab.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libcxx/docs/ReleaseNotes/23.rst
M libcxx/include/__configuration/attributes.h
M libcxx/include/__mutex/lock_guard.h
M libcxx/include/__mutex/mutex.h
M libcxx/include/mutex
M libcxx/include/shared_mutex
A libcxx/test/extensions/clang/thread/thread.mutex/thread_safety_scoped_lock.pass.cpp
A libcxx/test/extensions/clang/thread/thread.mutex/thread_safety_scoped_lock.verify.cpp
Log Message:
-----------
[libc++][ThreadSafety] Add thread safety annotations for variadic std::scoped_lock (#204462)
The thread safety annotations on std::scoped_lock were previously only
applied to the empty and single-mutex specializations. The general
variadic specialization carried no annotations, so -Wthread-safety
considered none of the mutexes held inside a multi-mutex scoped_lock
block and reported the guarded data accessed there as unprotected.
Now that Clang supports pack expansion inside thread safety attributes
(landed for Clang 21), annotate the variadic scoped_lock with
acquire_capability/requires_capability on its constructors,
release_capability on its destructor, and scoped_lockable on the class.
Fixes #42000.
Co-authored-by: Anthony Calandra <anthony at anthony-calandra.com>
Commit: e4e2a9346b60e3805b63cec888f6de022db5b271
https://github.com/llvm/llvm-project/commit/e4e2a9346b60e3805b63cec888f6de022db5b271
Author: Jacob Crawley <jacob.crawley at arm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
A llvm/test/CodeGen/AArch64/sve-interleave-low-vf.ll
M llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence.ll
A llvm/test/Transforms/LoopVectorize/AArch64/sve-interleave-low-vf-cost.ll
A llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-access-low-vf.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
Log Message:
-----------
[AArch64][LV] Cost low-VF interleaved access (#205844)
Adds a case to getInterleavedMemoryOpCost to cost scalable interleaved
memory accesses where the interleave factor is larger than the VF.
Previously for these cases, memory operations would be costed as
individual gathers and scatters, which may result in the LoopVectorizer
choosing a wider VF than necessary.
This changes proposes an alternative approach of using a contiguous
load/store of the interleaved vector followed by shuffles to get
the elements into place.
Commit: 1045d1ebca559d7e6dee49b002142e52bb61b49e
https://github.com/llvm/llvm-project/commit/1045d1ebca559d7e6dee49b002142e52bb61b49e
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libcxx/include/__ranges/zip_view.h
M libcxx/test/libcxx/ranges/range.adaptors/range.zip.transform/nodiscard.verify.cpp
A libcxx/test/libcxx/ranges/range.adaptors/range.zip/nodiscard.verify.cpp
A libcxx/test/libcxx/ranges/range.adaptors/range_adaptor_types.h
Log Message:
-----------
[libc++][ranges] Applied `[[nodiscard]]` to `zip_view` (#207667)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html
- https://wg21.link/range.zip
Towards #172124
Commit: 3046fb3de4b067179bcb8f933942aafea2c0d46f
https://github.com/llvm/llvm-project/commit/3046fb3de4b067179bcb8f933942aafea2c0d46f
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
A offload/test/Inputs/declare-target-common-block-sub.f90
A offload/test/offloading/fortran/declare-target-common-block-2.f90
A offload/test/offloading/fortran/declare-target-common-block-main.f90
Log Message:
-----------
[Flang][OpenMP][Offload] Add Flang offload tests for common block and declare target (#202949)
This PR adds a couple of tests revolving around the usage of common
block with declare target in Fortran OpenMP.
Commit: 3b3f6b56dba47ce53afa6340b27355a94a483e8c
https://github.com/llvm/llvm-project/commit/3b3f6b56dba47ce53afa6340b27355a94a483e8c
Author: Frederik Harwath <frederik.harwath at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
Log Message:
-----------
[AMDGPU] SIFoldOperands: Print instructions/operands in debug output (NFC) (#207945)
Print instructions/operands instead of their addresses in debug output.
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: da9377fad1764dd7f654676aba1fef49205ccc6d
https://github.com/llvm/llvm-project/commit/da9377fad1764dd7f654676aba1fef49205ccc6d
Author: UebelAndre <github at uebelandre.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M utils/bazel/MODULE.bazel
M utils/bazel/MODULE.bazel.lock
Log Message:
-----------
[bazel] Sort bazel_deps into 'compat floor' and 'latest' sections (#207605)
Some dependencies have big knock-on effects and to the benefit of
consumers should best be tracked as min-supported-version. This change
divides the `MODULE.bazel` file into two sections where one contains
known sensitive dependencies that should only be bumped as needed and
the second are flex dependencies that can freely be updated with minimal
impact to external consumers.
Commit: 2bb0c2d1e86c6bd008c3dc23040fb9081289deff
https://github.com/llvm/llvm-project/commit/2bb0c2d1e86c6bd008c3dc23040fb9081289deff
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
Log Message:
-----------
PPC: Use SmallVector for tracking operands instead of DenseMap (#208034)
This is just tracking registers by operand index, which doesn't
need a heavy map.
Commit: 301060211315e9eadb39e17872c2b9d696d72fd6
https://github.com/llvm/llvm-project/commit/301060211315e9eadb39e17872c2b9d696d72fd6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
Log Message:
-----------
PPC: Fix querying TargetInstrInfo from PPCInstrInfo (#208030)
Commit: 3a9778bbf2d78d95bd1d330390187922c6956c78
https://github.com/llvm/llvm-project/commit/3a9778bbf2d78d95bd1d330390187922c6956c78
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M lldb/bindings/python/get-python-config.py
Log Message:
-----------
Revert "[lldb] Change Python site-packages path" (#207910)
Reverts llvm/llvm-project#207771.
`/usr/lib/pythonN.M/site-packages` is a standard path that everyone uses
to install python modules on posix systems. There is no such thing as
`/usr/lib/site-packages`. This change breaks lldb packaging for Linux
distros.
Commit: 17e8068444b58be6935b05200961c984e52989cb
https://github.com/llvm/llvm-project/commit/17e8068444b58be6935b05200961c984e52989cb
Author: Ivo Popov <popov.ivo at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/AST/ASTContext.cpp
A clang/test/Modules/modules-using-enum-class-scope.cppm
Log Message:
-----------
[clang][Modules] Support ODR merging of `UsingEnumDecl` (#207071)
Fixes https://github.com/llvm/llvm-project/issues/207066.
`UsingEnumDecl` (representing C++20 `using enum` declarations)
was not handled in `ASTContext::isSameEntity`.
Consequently, identical class definitions containing
a `using enum` statement failed to merge, resulting in spurious ODR
mismatch errors such as: `error: 'MyStruct::MyEnum' from module
'ModuleB' is not present in definition of 'MyStruct' in module
'ModuleA'`.
This patch implements merging support for `UsingEnumDecl` in
`ASTContext::isSameEntity` by comparing the nested-name-specifier
qualifiers and the underlying `EnumDecl` target.
---------
Co-authored-by: ipopov <ipopov at google.com>
Commit: 87a5682c92f69c87704487670d49db4ca65db21c
https://github.com/llvm/llvm-project/commit/87a5682c92f69c87704487670d49db4ca65db21c
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
Log Message:
-----------
[SLP][NFC]Update test checks, add some more tests, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/208048
Commit: 221cd6295224c93bed2bdfcc113eba5b64325c06
https://github.com/llvm/llvm-project/commit/221cd6295224c93bed2bdfcc113eba5b64325c06
Author: Folkert de Vries <folkert at folkertdev.nl>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp
A llvm/test/CodeGen/WebAssembly/f128-minmax.ll
Log Message:
-----------
[WebAssembly] support `f{min, max}imum.f128` and `f{min, max}imumnum.f128` (#207160)
fixes https://github.com/llvm/llvm-project/issues/207100
As far as I can see `wasi-libc` does not currently export the dedicated
libcalls, so I went with a custom expansion. It emits more code, but
will work without any linker errors etc.
The `long double` type is actually `f128` for webassembly, so at least
the libcalls should work.
Commit: 24688c6a67dc5293c2e75ca9ec991dd0c2a23e59
https://github.com/llvm/llvm-project/commit/24688c6a67dc5293c2e75ca9ec991dd0c2a23e59
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
Log Message:
-----------
PPC: Fix querying TargetRegisterInfo in PPCInstrInfo (#208031)
Use the direct PPCRegisterInfo member
Commit: 9e22a5950e51ace7f50729d7f556ca99d06fa8bb
https://github.com/llvm/llvm-project/commit/9e22a5950e51ace7f50729d7f556ca99d06fa8bb
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
M llvm/lib/Analysis/MemorySSA.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/test/Analysis/MemorySSA/invariant-load-intrinsic.ll
M llvm/test/Transforms/GVN/invariant-load-intrinsic.ll
M llvm/test/Transforms/InstCombine/invariant-load-like-sink.ll
M llvm/test/Transforms/Sink/invariant-load.ll
A llvm/test/Verifier/invariant-load-metadata-invalid.ll
Log Message:
-----------
[llvm] Support invariant.load on readonly intrinsics (#205916)
Update passes and analyses that look at invariant.load (ex. MemorySSA)
to also consider the possibility that `!invariant.load` may be present
on intrinsic calls.
Updates the verifier to indicate that `!invariant.load` is only legal
for loads and readonly intrinsics (and moves the definition of the
metadata out of the definition of `load`).
This has not been extended to arbitrary function calls since it's less
clear what the semantics of !invariant.load on them would be.
Furthermore, extension to read/write intrinsics like memcpy() is planned
as a followup.
This PR also deletes tests that were pre-committed in
https://github.com/llvm/llvm-project/pull/205894 but that become invalid
with the verifier changes in this PR
AI disclosure: I've reviewed the code but all the actual generation was
done by AI.
---------
Co-authored-by: Codex <codex at openai.com>
Commit: dda9dc50945006189f5fabe08a165640c289f0e7
https://github.com/llvm/llvm-project/commit/dda9dc50945006189f5fabe08a165640c289f0e7
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M .github/workflows/libcxx-run-benchmarks.yml
Log Message:
-----------
[libc++] Use a median-of-3 for the A/B comparison benchmarking job (#208023)
After a bit of testing, I think this provides a good tradeoff between
resource utilization and noise reduction. Furthermore, the comparison
script (which produces the output) will be augmented to surface the
variability of the results in a separate PR.
Commit: 0fba09ca6c856f7ec043689c62198166a0b0321e
https://github.com/llvm/llvm-project/commit/0fba09ca6c856f7ec043689c62198166a0b0321e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/ashr-main-opcode-copyables.ll
Log Message:
-----------
[SLP][NFC]Add an extra test with ashr vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/208057
Commit: 100a1fb9d628dc9969ca8f7aef774f61e168f9e9
https://github.com/llvm/llvm-project/commit/100a1fb9d628dc9969ca8f7aef774f61e168f9e9
Author: Chi-Chun, Chen <chichun.chen at hpe.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M flang/include/flang/Semantics/openmp-dsa.h
M flang/lib/Semantics/openmp-dsa.cpp
M flang/lib/Semantics/resolve-directives.cpp
Log Message:
-----------
[flang][OpenMP][NFC] Share SetSymbolDSA between semantics and lowering (#207826)
Move the DSA helper from the private OmpAttributeVisitor::SetSymbolDSA
into the public openmp-dsa header next to GetSymbolDSA, and share the
DSA flag set through a single GetDataSharingAttributeFlags().
This lets an upcoming metadirective lowering change reuse the helper to
set the predetermined DSA of the loop induction variables of a selected
variant. A loop-associated variant is resolved during lowering, so the
usual semantic DSA resolution never runs on its loop nest and lowering
must set those flags itself.
Assisted with Copilot.
Commit: 5da6b3c590792a069c40d8982c8b0fb3557f241a
https://github.com/llvm/llvm-project/commit/5da6b3c590792a069c40d8982c8b0fb3557f241a
Author: Alex Langford <alangford at apple.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M lldb/include/lldb/Target/DynamicRegisterInfo.h
M lldb/source/Target/DynamicRegisterInfo.cpp
Log Message:
-----------
[lldb] DynamicRegisterInfo::Dump should take a Stream argument (#207863)
Otherwise, it creates its own Stream dumping to stdout.
Commit: 29495e193f67cb88704f97bae906c21464148c7d
https://github.com/llvm/llvm-project/commit/29495e193f67cb88704f97bae906c21464148c7d
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
A .github/workflows/libcxx-pr-benchmark.yml
R .github/workflows/libcxx-run-benchmarks.yml
Log Message:
-----------
[libc++][NFC] Rename workflow file for libc++ A/B performance comparisons (#208070)
I want to introduce another workflow that allows running benchmarks on
historical commits of libc++ for LNT submission, so having an
unambiguous name is desirable.
Commit: 6d1566cecf40143012674376f5c9250316c29634
https://github.com/llvm/llvm-project/commit/6d1566cecf40143012674376f5c9250316c29634
Author: Petr Hosek <phosek at google.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang-tools-extra/clang-tidy/misc/DefinitionsInHeadersCheck.cpp
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/refactor/tweaks/DefineInline.cpp
M clang/docs/LibASTMatchersReference.html
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/JSONNodeDumper.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/ASTMatchers/ASTMatchersInternal.h
M clang/include/clang/Basic/Specifiers.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTDumper.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/Comment.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/ASTMatchers/Dynamic/Registry.cpp
M clang/lib/Analysis/ExprMutationAnalyzer.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
M clang/lib/CodeGen/CGVTables.cpp
M clang/lib/Index/IndexingContext.cpp
M clang/lib/InstallAPI/Visitor.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/StaticAnalyzer/Core/BugSuppression.cpp
M clang/lib/Tooling/Syntax/BuildTree.cpp
M clang/test/AST/ast-dump-templates-pattern.cpp
M clang/test/CXX/basic/basic.link/p11.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg7xx.cpp
M clang/test/CXX/temp/temp.arg/temp.arg.template/p3-2a.cpp
M clang/test/CXX/temp/temp.constr/temp.constr.decl/p4.cpp
M clang/test/CXX/temp/temp.decls/temp.spec.partial/temp.spec.partial.member/p2.cpp
M clang/test/CXX/temp/temp.spec/temp.expl.spec/p7.cpp
M clang/test/CodeGenCXX/default-arguments.cpp
M clang/test/CodeGenCXX/explicit-instantiation.cpp
M clang/test/SemaCXX/GH195416.cpp
M clang/test/SemaCXX/constant-expression-cxx14.cpp
M clang/test/SemaCXX/deduced-return-type-cxx14.cpp
M clang/test/SemaCXX/member-class-11.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/test/SemaTemplate/friend-template.cpp
M clang/test/SemaTemplate/instantiate-scope.cpp
M clang/test/Templight/templight-default-func-arg.cpp
M clang/test/Templight/templight-empty-entries-fix.cpp
M clang/tools/libclang/CIndex.cpp
M clang/unittests/AST/ASTImporterTest.cpp
M clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
Log Message:
-----------
Revert "[clang] Reland: fix getTemplateInstantiationArgs" (#208064)
Reverts llvm/llvm-project#207825 since it's causing a crash in Clang.
Commit: 585f04f2bf11c84367641f62a5e280a0241a71de
https://github.com/llvm/llvm-project/commit/585f04f2bf11c84367641f62a5e280a0241a71de
Author: Derek Schuff <dschuff at chromium.org>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Support/CrashRecoveryContext.cpp
Log Message:
-----------
[Support] Add missing include for MacOS defines (#208065)
https://github.com/llvm/llvm-project/pull/142733 removed several
includes, including
llvm/Support/ProgramStack.h. This was indirectly including headers that
defined
PRIO_DARWIN_THREAD and PRIO_DARWIN_BG.
Add back sys/resource.h to define them locally.
Commit: d8f56af5fecb3d431efa801b80a87a6547638fd8
https://github.com/llvm/llvm-project/commit/d8f56af5fecb3d431efa801b80a87a6547638fd8
Author: Nerixyz <nerixdev at outlook.de>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusNameParser.cpp
M lldb/unittests/Language/CPlusPlus/CPlusPlusLanguageTest.cpp
Log Message:
-----------
[lldb] Support MS style `struct`/`class` in C++ name parser (#196525)
If a type is declared as a `class` or a `struct` is part of the mangled
name in the Microsoft ABI. This is also reflected in the demangled name.
There, it shows up before the qualified name. For example, you could
have `class ns1::ns2::MyClass`. It will show up like this in return
types and function/template arguments.
This adds a check in `CPlusPlusNameParser::ParseFullNameImpl` for these
cases.
Commit: c098e41b8de197330454afd5ce8cf05ee8e57b39
https://github.com/llvm/llvm-project/commit/c098e41b8de197330454afd5ce8cf05ee8e57b39
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/unittests/Transforms/Vectorize/VPDomTreeTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[VPlan] Use StepVector without operands, VPBuilder in C++ tests (NFC) (#208075)
Update unit tests construction VScale for VPInstructions without
operands to use StepVector where possible. When VScale is needed,
construct with VPBuilder. Also update constructing other recipes in same
function to use VPBuilder, for consistency.
Split off from approved https://github.com/llvm/llvm-project/pull/207541
Commit: eba2fde4d5409ae861587552ddc8c6837de2ad82
https://github.com/llvm/llvm-project/commit/eba2fde4d5409ae861587552ddc8c6837de2ad82
Author: Zachary Yedidia <zyedidia at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/lib/Basic/Targets/X86.cpp
M llvm/docs/LFI.rst
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/MC/MCLFI.cpp
M llvm/lib/Target/X86/MCTargetDesc/CMakeLists.txt
A llvm/lib/Target/X86/MCTargetDesc/X86MCLFIRewriter.cpp
A llvm/lib/Target/X86/MCTargetDesc/X86MCLFIRewriter.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86Subtarget.h
M llvm/lib/TargetParser/Triple.cpp
A llvm/test/CodeGen/X86/lfi-sibcall.ll
A llvm/test/MC/X86/LFI/abi-note.s
A llvm/test/MC/X86/LFI/syscall.s
A llvm/test/MC/X86/LFI/thread-pointer-errors.s
A llvm/test/MC/X86/LFI/thread-pointer.s
Log Message:
-----------
Reland: [LFI][X86] Add X86 LFI target and system instruction rewrites (#207892)
Reintroduction of #189569 using the MCRegisterClass accessor API, which
was recently modified and caused a build error when the previous PR
was merged since it was not rebased onto the latest commit.
Commit: 9a1f5b76b4af5c99f4c60456abcc95f5640b35df
https://github.com/llvm/llvm-project/commit/9a1f5b76b4af5c99f4c60456abcc95f5640b35df
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/OpenACC/Analysis/FIROpenACCSupportAnalysis.h
M flang/lib/Optimizer/OpenACC/Analysis/CMakeLists.txt
M flang/lib/Optimizer/OpenACC/Analysis/FIROpenACCSupportAnalysis.cpp
M flang/unittests/Optimizer/CMakeLists.txt
A flang/unittests/Optimizer/OpenACC/FIROpenACCSupportAnalysisTest.cpp
M mlir/include/mlir/Dialect/OpenACC/Analysis/OpenACCSupport.h
A mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsType.h
M mlir/lib/Dialect/OpenACC/Analysis/OpenACCSupport.cpp
M mlir/lib/Dialect/OpenACC/Utils/CMakeLists.txt
A mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsType.cpp
M mlir/unittests/Dialect/OpenACC/CMakeLists.txt
A mlir/unittests/Dialect/OpenACC/OpenACCUtilsTypeTest.cpp
Log Message:
-----------
[mlir][acc][flang] Add type sizing utilities (#208074)
Add a general acc utility for computing the size and alignment of a
type. It works for simple scalar types as well as nested and aggregate
types like arrays, tuples, and structures.
Because some types come from other dialects, the utility can hand those
off to a specialized helper that understands them. This lets sizing work
seamlessly even for mixed types, such as an aggregate whose members come
from a different dialect.
Add a Fortran-specific helper so Fortran types are sized correctly,
falling back to the general utility for everything else.
Include unit tests covering a range of scenarios, including scalars,
arrays, aggregates, and mixed-dialect types.
Commit: 9ff1d7a21e6d23088eb5dac38f95edd4329c50b7
https://github.com/llvm/llvm-project/commit/9ff1d7a21e6d23088eb5dac38f95edd4329c50b7
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
R llvm/test/Transforms/SampleProfile/icp_target_feature.ll
Log Message:
-----------
Revert "[PGO][ICP] Prevent indirect call promotion to functions with incompatible target features" (#208079)
Reverts llvm/llvm-project#192142
Now that https://github.com/llvm/llvm-project/pull/205113 has landed, we
will not inline functions with incompatible target features, even if the
callee is marked `alwaysinline`, so we can promote calls to such
functions while also removing the extra complexity from ICP.
Commit: 6d34e50b88ecce3d5e9ef7e0ed0b54e8f9818019
https://github.com/llvm/llvm-project/commit/6d34e50b88ecce3d5e9ef7e0ed0b54e8f9818019
Author: Alex Langford <alangford at apple.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M lldb/source/Utility/FileSpec.cpp
M lldb/source/Utility/FileSpecList.cpp
Log Message:
-----------
[lldb] Remove uses of ConstString in FileSpec methods (#206851)
After this, FileSpec only uses ConstString for storage. In a subsequent
commit, I will change FileSpec's storage.
Commit: ee745070b05e2474ea27f2268b5e7d52be933c4e
https://github.com/llvm/llvm-project/commit/ee745070b05e2474ea27f2268b5e7d52be933c4e
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M lldb/source/Plugins/Process/wasm/UnwindWasm.cpp
M lldb/test/API/functionalities/gdb_remote_client/TestWasm.py
Log Message:
-----------
[lldb] Give Wasm stack frames a synthetic call frame address (#208061)
UnwindWasm reported a call frame address of zero for every Wasm frame.
StackID orders frames by their CFA, assuming the stack grows downward so
that a younger frame compares below its caller. With every CFA equal to
zero that ordering collapsed, and CompareCurrentFrameToStartFrame
treated a step into a function as a step out, which silently disabled
step-in avoid-regexp and confused other thread plans.
WebAssembly keeps its call stack inside the engine and exposes no
linear-memory frame address, so synthesize a CFA from each frame's
distance to the outermost frame. That distance is invariant as frames
are pushed and popped above it, so a given frame keeps a stable, ordered
CFA across steps.
Commit: c7d45caea0faba51223feb08e2224bf845724b17
https://github.com/llvm/llvm-project/commit/c7d45caea0faba51223feb08e2224bf845724b17
Author: Adam Nemet <anemet at apple.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
A llvm/test/CodeGen/ARM/unaligned_load_store_no_aeabi.ll
M llvm/utils/UpdateTestChecks/asm.py
Log Message:
-----------
[ARM] Don't try to emit AEABI libcalls for non-AEABI targets (#207813)
PR #172672 added ARMTargetLowering::LowerAEABIUnalignedLoad/Store which
lowers some of the unaligned i32/i64 stores to
__aeabi_u{read,write}{4,8}. The libcall is emitted unconditionally, with
no check whether the target environment actually has these AEABI
helpers.
We don't have it for Apple/MachO which leads to a compiler crash.
rdar://175136625
Commit: 8fbf94a21b69770091c73381be24fff43e89d93e
https://github.com/llvm/llvm-project/commit/8fbf94a21b69770091c73381be24fff43e89d93e
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/lib/Lex/LiteralSupport.cpp
Log Message:
-----------
Silence a signed/unsigned mismatch diagnostic; NFC (#208088)
Commit: d2888890b513e757916e8e20c06146d2b9b6b4a0
https://github.com/llvm/llvm-project/commit/d2888890b513e757916e8e20c06146d2b9b6b4a0
Author: Anshul Nigham <nigham at google.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/docs/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack.md
Log Message:
-----------
Update AMD DWARF ext doc headers to only have a single title-level header (#208103)
This ensures no leakage of individual headings on the page to the global
TOC, see https://github.com/llvm/llvm-project/pull/184440
Commit: 4c93275445c698b4290ef48f98f256adf2a90f39
https://github.com/llvm/llvm-project/commit/4c93275445c698b4290ef48f98f256adf2a90f39
Author: Jackson Stogel <jtstogel at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libc/src/__support/CPP/string.h
M libc/test/src/__support/CPP/string_test.cpp
Log Message:
-----------
[libc][cpp::string] Fix off-by-one bug in resize and a memory leak (#208077)
AFAICT, `cpp::string` is only used in tests, so these bugs were mostly
inconsequential.
Commit: 448b57d52e77950e0cfc9d81fb0e65f7143c27d1
https://github.com/llvm/llvm-project/commit/448b57d52e77950e0cfc9d81fb0e65f7143c27d1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/test/CodeGen/X86/vector-trunc.ll
Log Message:
-----------
[X86] vector-trunc.ll - regenerate checks to add missing ADD constant pool comments (#207827)
Commit: 73867dce09789f8de6d38edcfa8101f2ae2138e4
https://github.com/llvm/llvm-project/commit/73867dce09789f8de6d38edcfa8101f2ae2138e4
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/include/clang/Driver/Action.h
M clang/include/clang/Options/Options.td
M clang/lib/Driver/Action.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Driver/ToolChains/MSVC.h
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/lib/Driver/ToolChains/MinGW.h
A clang/test/Driver/arm64x.c
M clang/test/Driver/msvc-link.c
Log Message:
-----------
[clang][ARM64X] Support compiling both native and EC objects with -marm64x (#207612)
When -marm64x is used during the assembly phase, construct jobs for both
native and EC targets and merge their outputs using llvm-objcopy.
Allow passing ArchName to computeTargetTriple on non-Darwin targets to
enable BindArchAction on other platforms. Additionally, allow passing
multiple inputs to ObjcopyJobAction and use this capability to construct
ARM64X merge jobs.
Commit: 8b93782d2da3d651a1774f96acf747c5b2181cd4
https://github.com/llvm/llvm-project/commit/8b93782d2da3d651a1774f96acf747c5b2181cd4
Author: Anshul Nigham <nigham at google.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/docs/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack.md
Log Message:
-----------
Add explicit anchors to deep headers for AMD DWARF ext doc (#208110)
Anchors get auto-generated only upto level 6, and
https://github.com/llvm/llvm-project/pull/208103 added another level,
causing sphinx to complain about no targets for these anchors.
Commit: 39dcb0ff91b312bb269334168d5e32be78b60417
https://github.com/llvm/llvm-project/commit/39dcb0ff91b312bb269334168d5e32be78b60417
Author: Mircea Trofin <mtrofin at google.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
M clang/test/CodeGen/lto-newpm-pipeline.c
M clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
M lld/test/ELF/lto/devirt_vcall_vis_export_dynamic.ll
M lld/test/ELF/lto/devirt_vcall_vis_public.ll
M lld/test/ELF/lto/devirt_vcall_vis_shared_def.ll
M llvm/include/llvm/Analysis/CtxProfAnalysis.h
M llvm/include/llvm/Bitcode/BitcodeReader.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/IR/GlobalObject.h
M llvm/include/llvm/IR/GlobalValue.h
M llvm/include/llvm/IR/Module.h
M llvm/include/llvm/IR/ModuleSummaryIndex.h
M llvm/include/llvm/LTO/LTO.h
M llvm/include/llvm/Passes/PassBuilder.h
A llvm/include/llvm/Transforms/Utils/AssignGUID.h
M llvm/lib/Analysis/CtxProfAnalysis.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeAnalyzer.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/GlobalMerge.cpp
M llvm/lib/IR/Globals.cpp
M llvm/lib/LTO/LTO.cpp
M llvm/lib/LTO/LTOBackend.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Transforms/IPO/ConstantMerge.cpp
M llvm/lib/Transforms/IPO/FunctionImport.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/lib/Transforms/Instrumentation/PGOCtxProfFlattening.cpp
M llvm/lib/Transforms/Instrumentation/PGOCtxProfLowering.cpp
M llvm/lib/Transforms/Scalar/JumpTableToSwitch.cpp
A llvm/lib/Transforms/Utils/AssignGUID.cpp
M llvm/lib/Transforms/Utils/CMakeLists.txt
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
M llvm/lib/Transforms/Utils/CloneModule.cpp
M llvm/lib/Transforms/Utils/FunctionImportUtils.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
R llvm/test/Analysis/CtxProfAnalysis/flatten-prethinlink-requires-guid-metadata.ll
M llvm/test/Assembler/index-value-order.ll
M llvm/test/Bitcode/thinlto-alias.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph-partial-sample-profile-summary.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph-pgo.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph-profile-summary.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph-sample-profile-summary.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph.ll
M llvm/test/Bitcode/thinlto-function-summary-refgraph.ll
M llvm/test/Bitcode/thinlto-function-summary.ll
M llvm/test/CodeGen/X86/fat-lto-section.ll
M llvm/test/LTO/Resolution/X86/not-prevailing-alias.ll
M llvm/test/LTO/Resolution/X86/not-prevailing-weak-aliasee.ll
M llvm/test/Linker/funcimport2.ll
M llvm/test/Other/new-pm-O0-defaults.ll
M llvm/test/Other/new-pm-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
M llvm/test/ThinLTO/AArch64/aarch64_inline.ll
M llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions1.ll
M llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions2.ll
M llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions3.ll
M llvm/test/ThinLTO/X86/ctor-dtor-alias.ll
M llvm/test/ThinLTO/X86/ctor-dtor-alias2.ll
M llvm/test/ThinLTO/X86/deadstrip.ll
M llvm/test/ThinLTO/X86/devirt_function_alias.ll
M llvm/test/ThinLTO/X86/devirt_function_alias2.ll
M llvm/test/ThinLTO/X86/devirt_pure_virtual_base.ll
M llvm/test/ThinLTO/X86/devirt_vcall_vis_public.ll
M llvm/test/ThinLTO/X86/distributed_import.ll
M llvm/test/ThinLTO/X86/funcattrs-prop-exported-internal.ll
M llvm/test/ThinLTO/X86/funcattrs-prop-unknown.ll
M llvm/test/ThinLTO/X86/funcattrs-prop-weak.ll
M llvm/test/ThinLTO/X86/globals-import.ll
M llvm/test/ThinLTO/X86/hidden-escaped-symbols-alt.ll
M llvm/test/ThinLTO/X86/hidden-escaped-symbols.ll
M llvm/test/ThinLTO/X86/import-ro-constant.ll
M llvm/test/ThinLTO/X86/index-const-prop-alias.ll
M llvm/test/ThinLTO/X86/index-const-prop.ll
M llvm/test/ThinLTO/X86/linkonce_resolution_comdat.ll
M llvm/test/ThinLTO/X86/memprof-dups.ll
M llvm/test/ThinLTO/X86/memprof_callee_type_mismatch.ll
M llvm/test/ThinLTO/X86/memprof_imported_internal.ll
M llvm/test/ThinLTO/X86/memprof_imported_internal2.ll
M llvm/test/ThinLTO/X86/prevailing_weak_globals_import.ll
M llvm/test/ThinLTO/X86/visibility-elf.ll
M llvm/test/ThinLTO/X86/visibility-macho.ll
M llvm/test/ThinLTO/X86/weak_resolution.ll
M llvm/test/ThinLTO/X86/windows-vftable.ll
M llvm/test/ThinLTO/X86/writeonly.ll
A llvm/test/Transforms/AssignGUID/assign_guid.ll
M llvm/test/Transforms/ConstantMerge/merge-dbg.ll
M llvm/test/Transforms/EmbedBitcode/embed-wpd.ll
M llvm/test/Transforms/EmbedBitcode/embed.ll
M llvm/test/Transforms/FunctionImport/funcimport-debug-retained-nodes.ll
M llvm/test/Transforms/FunctionImport/funcimport.ll
A llvm/test/Transforms/GlobalMerge/guid.ll
M llvm/test/Transforms/LowerTypeTests/cfi-icall-alias.ll
M llvm/test/Transforms/LowerTypeTests/export-icall.ll
M llvm/test/Transforms/PGOProfile/thinlto_indirect_call_promotion.ll
M llvm/test/Transforms/PhaseOrdering/speculative-devirt-then-inliner.ll
M llvm/test/Transforms/SampleProfile/ctxsplit.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal-typeid.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal1.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal2.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc-internal.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/unsplittable.ll
M llvm/test/Transforms/WholeProgramDevirt/branch-funnel-profile.ll
M llvm/test/Transforms/WholeProgramDevirt/export-single-impl.ll
M llvm/test/Transforms/WholeProgramDevirt/export-vcp.ll
M llvm/test/Transforms/WholeProgramDevirt/virtual-const-prop-interposable.ll
M llvm/test/tools/gold/X86/devirt_vcall_vis_export_dynamic.ll
M llvm/test/tools/gold/X86/devirt_vcall_vis_public.ll
M llvm/test/tools/gold/X86/devirt_vcall_vis_shared_def.ll
M llvm/test/tools/gold/X86/thinlto_weak_library.ll
M llvm/test/tools/gold/X86/thinlto_weak_resolution.ll
M llvm/test/tools/gold/X86/v1.16/devirt_vcall_vis_export_dynamic.ll
M llvm/tools/llvm-link/llvm-link.cpp
M llvm/tools/opt/NewPMDriver.cpp
M llvm/tools/opt/optdriver.cpp
Log Message:
-----------
Reland "Compute GUIDs once and store in metadata" (#184065) (#201849)
This reverts #201194, thus relanding @orodley's PR #184065 (and
#200323):
> This allows us to keep GUIDs consistent across compilation phases
which may change the name or linkage type.
> See
https://discourse.llvm.org/t/rfc-keep-globalvalue-guids-stable/84801
The CFI issues that triggered the original revert are fixed by #201370,
together with the addressing of the TODOs in `LowerTypeTests.cpp` left
in the latter. The [graphite
diff](https://app.graphite.com/github/pr/llvm/llvm-project/201849/Reland-%23184065)
between this change's V1 and V2 shows what's been added:
- the `TODO`s from #201370 are done
- in LowerTypeTests.cpp, passing `!guid` when creating a new declaration
and when converting a definition to a declaration.
- `llvm/test/Transforms/LowerTypeTests/export-icall.ll` tests also the
above def->decl conversion
- removed
`test/Analysis/CtxProfAnalysis/flatten-prethinlink-requires-guid-metadata.ll`
introduced in #194383 (this was between the revert and this PR), as now
the general expectation is that GUID assignment happens appropriately
and all passes use `getGUID`, so there's no reason for `CtxProfAnalysis`
to do something different.
Currently, we reassign GUIDs when CFI promotes internal linkage symbols,
which is counter to the goal of the RFC. This is addressed in PR
#203171. The reason for this split fix can be explained on
`compiler-rt/test/cfi/icall/wrong-signature-mixed-lto.c`. Here, a module
with the exact same source path is compiled twice, under different
conditional compilation, to produce 2 objects. Each object defines an
internal linkage symbol with the same name (this is
`install_trap_loop_detection` from
`compiler-rt/test/cfi/trap_loop_signal_handler.inc` which is
`-include`\-d by both - see how `%clang_cfi` is defined). The ThinLTO
GUID of this symbol will be the same. Its name won't be - because CFI
promotes it and renames it using a hash that is based on the IR Module
content (rather than the source path). During thinlink,
`LTO::addThinLTO`will mark each of the 2 exported symbols as prevailing
in their corresponding modules. But that is done by associating their
GUID to the module. So whichever comes last wins. The other symbol will
be marked available externally and its body DCEd later in backend. But
each module will refer to its copy of `install_trap_loop_detection`, and
so we end up with a linker error.
As mentioned, the fix is in PR #203171, and this relanding PR just
maintains the existing ThinLTO behavior by rewriting the GUIDs. Since we
haven't yet leveraged the GUID mechanics for e.g. simplifying PGO, this
aspect of this change is essentially NFC.
Co-authored-by: Owen Rodley <orodley at google.com>
Commit: 2a8e0e1abbdc558f3a4b43d5a9432c07b5d01387
https://github.com/llvm/llvm-project/commit/2a8e0e1abbdc558f3a4b43d5a9432c07b5d01387
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/X86/reassociate-ops.ll
Log Message:
-----------
[SLP][NFC]Add tests with some preferred reassociation, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/208118
Commit: cc27a240be812f854801c24aefbea1243c5efde8
https://github.com/llvm/llvm-project/commit/cc27a240be812f854801c24aefbea1243c5efde8
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M lldb/include/lldb/Target/Process.h
M lldb/include/lldb/Utility/Policy.h
M lldb/source/Expression/FunctionCaller.cpp
M lldb/source/Expression/IRInterpreter.cpp
M lldb/source/Expression/LLVMUserExpression.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/StackFrameList.cpp
M lldb/source/Target/StopInfo.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/Thread.cpp
M lldb/source/Utility/Policy.cpp
M lldb/unittests/Utility/PolicyTest.cpp
Log Message:
-----------
[lldb] Push ExpressionEvaluation policy and remove identity check fallbacks (#195775)
Push `PolicyStack::Get().PushPublicStateRunningExpression()` at all
three expression evaluation entry points
(`LLVMUserExpression::DoExecute`, `FunctionCaller::ExecuteFunction`,
`IRInterpreter`). This policy sets `can_run_breakpoint_actions=false`,
preventing recursive breakpoint callback execution during expression
eval.
Push `PolicyStack::Get().PushPrivateState()` unconditionally for all
PSTs in `RunPrivateStateThread` (not just overrides), giving every PST
the private view while keeping frame providers and recognizers enabled
for normal stop processing. Override PSTs use
`PushPrivateStateRunningExpression()` which additionally disables
providers and recognizers.
With all PSTs and expression eval sites now covered by the policy,
remove all host thread identity check fallbacks:
- `CurrentThreadPosesAsPrivateStateThread()` in `Process::GetState()`
- `CurrentThreadIsPrivateStateThread()` in `Target::GetAPIMutex()`
- `IsOnThread()` in `PrivateStateThread::GetRunLock()`
- `CurrentThreadPosesAsPrivateStateThread()` in
`SelectMostRelevantFrame()`
- `IsRunningExpression()` in `StopInfoBreakpoint::PerformAction()`
`SelectMostRelevantFrame` now checks `!can_run_frame_recognizers`
instead of `View::Private`, so recognizers run during normal PST stop
processing but are skipped during expression evaluation.
----
The following PRs are related to the Policy feature:
- #195762
- #195771
- #198897
- #195774
- #195775
rdar://176223894
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: d1ad52f0ca135b972f352b38fbc813404efb91ac
https://github.com/llvm/llvm-project/commit/d1ad52f0ca135b972f352b38fbc813404efb91ac
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M flang/include/flang/Common/constexpr-bitset.h
M flang/include/flang/Common/idioms.h
M flang/include/flang/Decimal/binary-floating-point.h
M flang/include/flang/Evaluate/expression.h
M flang/include/flang/Evaluate/fold-designator.h
M flang/include/flang/Evaluate/fold.h
M flang/include/flang/Evaluate/intrinsics.h
M flang/include/flang/Evaluate/rewrite.h
M flang/include/flang/Evaluate/shape.h
M flang/include/flang/Evaluate/traverse.h
M flang/include/flang/Evaluate/type.h
M flang/include/flang/Frontend/CodeGenOptions.h
M flang/include/flang/Frontend/TextDiagnostic.h
M flang/include/flang/Lower/Allocatable.h
M flang/include/flang/Lower/CUDA.h
M flang/include/flang/Lower/CallInterface.h
M flang/include/flang/Lower/ConvertExprToHLFIR.h
M flang/include/flang/Lower/ConvertType.h
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Lower/HostAssociations.h
M flang/include/flang/Lower/Mangler.h
M flang/include/flang/Lower/OpenMP.h
M flang/include/flang/Lower/Runtime.h
M flang/include/flang/Lower/Support/Utils.h
M flang/include/flang/Lower/SymbolMap.h
M flang/include/flang/Optimizer/Builder/DirectivesCommon.h
M flang/include/flang/Optimizer/Builder/Factory.h
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/include/flang/Optimizer/Builder/MIFCommon.h
M flang/include/flang/Optimizer/Builder/Runtime/Character.h
M flang/include/flang/Optimizer/Builder/Runtime/RTBuilder.h
M flang/include/flang/Optimizer/Builder/Todo.h
M flang/include/flang/Optimizer/CodeGen/CodeGenOpenMP.h
M flang/include/flang/Optimizer/CodeGen/TypeConverter.h
M flang/include/flang/Optimizer/Dialect/CUF/CUFDialect.h
M flang/include/flang/Optimizer/Dialect/FIRCG/CGOps.h
M flang/include/flang/Optimizer/Dialect/MIF/MIFDialect.h
M flang/include/flang/Optimizer/Dialect/SafeTempArrayCopyAttrInterface.h
M flang/include/flang/Optimizer/Passes/Pipelines.h
M flang/include/flang/Optimizer/Support/InitFIR.h
M flang/include/flang/Optimizer/Support/InternalNames.h
M flang/include/flang/Optimizer/Support/Utils.h
M flang/include/flang/Optimizer/Transforms/CUDA/CUFAllocationConversion.h
M flang/include/flang/Optimizer/Transforms/CUFGPUToLLVMConversion.h
M flang/include/flang/Optimizer/Transforms/CUFOpConversion.h
M flang/include/flang/Optimizer/Transforms/MIFOpConversion.h
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Parser/char-block.h
M flang/include/flang/Parser/char-buffer.h
M flang/include/flang/Parser/openmp-utils.h
M flang/include/flang/Parser/parse-state.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Parser/token-sequence.h
M flang/include/flang/Parser/unparse.h
M flang/include/flang/Parser/user-state.h
M flang/include/flang/Runtime/CUDA/common.h
M flang/include/flang/Runtime/CUDA/kernel.h
M flang/include/flang/Runtime/array-constructor-consts.h
M flang/include/flang/Runtime/random.h
M flang/include/flang/Runtime/reduce.h
M flang/include/flang/Runtime/reduction.h
M flang/include/flang/Runtime/support.h
M flang/include/flang/Semantics/attr.h
M flang/include/flang/Semantics/expression.h
M flang/include/flang/Semantics/openmp-utils.h
M flang/include/flang/Semantics/runtime-type-info.h
M flang/include/flang/Semantics/semantics.h
M flang/include/flang/Semantics/type.h
M flang/include/flang/Semantics/unparse-with-symbols.h
M flang/include/flang/Tools/CrossToolHelpers.h
M flang/include/flang/Tools/TargetSetup.h
M flang/lib/Decimal/big-radix-floating-point.h
M flang/lib/Decimal/decimal-to-binary.cpp
M flang/lib/Evaluate/expression.cpp
M flang/lib/Evaluate/fold-implementation.h
M flang/lib/Evaluate/host.h
M flang/lib/Evaluate/intrinsics-library.cpp
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Evaluate/real.cpp
M flang/lib/Evaluate/variable.cpp
M flang/lib/Frontend/CodeGenOptions.cpp
M flang/lib/Frontend/CompilerInstance.cpp
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Frontend/FrontendAction.cpp
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
M flang/lib/Lower/Allocatable.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Lower/ConvertArrayConstructor.cpp
M flang/lib/Lower/ConvertExpr.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/CustomIntrinsicCall.cpp
M flang/lib/Lower/HostAssociations.cpp
M flang/lib/Lower/IO.cpp
M flang/lib/Lower/Mangler.cpp
M flang/lib/Lower/MultiImageFortran.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/Atomic.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/Decomposer.cpp
M flang/lib/Lower/OpenMP/Decomposer.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/PFTBuilder.cpp
M flang/lib/Lower/Runtime.cpp
M flang/lib/Lower/SymbolMap.cpp
M flang/lib/Lower/VectorSubscripts.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/lib/Optimizer/Builder/CUFCommon.cpp
M flang/lib/Optimizer/Builder/MIFCommon.cpp
M flang/lib/Optimizer/Builder/Runtime/Character.cpp
M flang/lib/Optimizer/Builder/Runtime/Derived.cpp
M flang/lib/Optimizer/Builder/Runtime/Intrinsics.cpp
M flang/lib/Optimizer/Builder/Runtime/Main.cpp
M flang/lib/Optimizer/CodeGen/BoxedProcedure.cpp
M flang/lib/Optimizer/CodeGen/CodeGenOpenMP.cpp
M flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp
M flang/lib/Optimizer/CodeGen/PassDetail.h
M flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp
M flang/lib/Optimizer/CodeGen/TBAABuilder.cpp
M flang/lib/Optimizer/CodeGen/Target.cpp
M flang/lib/Optimizer/Dialect/CUF/Attributes/CUFAttr.cpp
M flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Dialect/MIF/MIFOps.cpp
M flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
M flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp
M flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/HLFIR/Transforms/PropagateFortranVariableAttributes.cpp
M flang/lib/Optimizer/HLFIR/Transforms/ScheduleOrderedAssignments.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCAttributes.cpp
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
M flang/lib/Optimizer/OpenMP/DeleteUnreachableTargets.cpp
M flang/lib/Optimizer/OpenMP/FunctionFiltering.cpp
M flang/lib/Optimizer/OpenMP/LowerWorkdistribute.cpp
M flang/lib/Optimizer/OpenMP/LowerWorkshare.cpp
M flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
M flang/lib/Optimizer/OpenMP/MapsForPrivatizedSymbols.cpp
M flang/lib/Optimizer/OpenMP/Support/FIROpenMPAttributes.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Support/DataLayout.cpp
M flang/lib/Optimizer/Support/InternalNames.cpp
M flang/lib/Optimizer/Transforms/AddAliasTags.cpp
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/lib/Optimizer/Transforms/AffineDemotion.cpp
M flang/lib/Optimizer/Transforms/AffinePromotion.cpp
M flang/lib/Optimizer/Transforms/AssumedRankOpConversion.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFAllocationConversion.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFComputeSharedMemoryOffsetsAndSize.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFDeviceFuncTransform.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFDeviceGlobal.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFFunctionRewrite.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFGPUToLLVMConversion.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFLaunchAttachAttr.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversionLate.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFPredefinedVarToGPU.cpp
M flang/lib/Optimizer/Transforms/CompilerGeneratedNames.cpp
M flang/lib/Optimizer/Transforms/ControlFlowConverter.cpp
M flang/lib/Optimizer/Transforms/ConvertComplexPow.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.h
M flang/lib/Optimizer/Transforms/ExternalNameConversion.cpp
M flang/lib/Optimizer/Transforms/FIRToMemRef.cpp
M flang/lib/Optimizer/Transforms/FIRToSCF.cpp
M flang/lib/Optimizer/Transforms/GenRuntimeCallsForTest.cpp
M flang/lib/Optimizer/Transforms/LoopInvariantCodeMotion.cpp
M flang/lib/Optimizer/Transforms/LoopVersioning.cpp
M flang/lib/Optimizer/Transforms/MIFOpConversion.cpp
M flang/lib/Optimizer/Transforms/MemRefDataFlowOpt.cpp
M flang/lib/Optimizer/Transforms/MemoryAllocation.cpp
M flang/lib/Optimizer/Transforms/MemoryUtils.cpp
M flang/lib/Optimizer/Transforms/OptimizeArrayRepacking.cpp
M flang/lib/Optimizer/Transforms/PolymorphicOpConversion.cpp
M flang/lib/Optimizer/Transforms/SetRuntimeCallAttributes.cpp
M flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp
M flang/lib/Optimizer/Transforms/SimplifyRegionLite.cpp
M flang/lib/Optimizer/Transforms/StackReclaim.cpp
M flang/lib/Optimizer/Transforms/VScaleAttr.cpp
M flang/lib/Parser/basic-parsers.h
M flang/lib/Parser/executable-parsers.cpp
M flang/lib/Parser/expr-parsers.cpp
M flang/lib/Parser/message.cpp
M flang/lib/Parser/openmp-utils.cpp
M flang/lib/Parser/parse-tree.cpp
M flang/lib/Parser/preprocessor.cpp
M flang/lib/Parser/prescan.cpp
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Parser/source.cpp
M flang/lib/Parser/token-parsers.h
M flang/lib/Semantics/assignment.cpp
M flang/lib/Semantics/canonicalize-omp.cpp
M flang/lib/Semantics/check-acc-structure.cpp
M flang/lib/Semantics/check-case.cpp
M flang/lib/Semantics/check-data.cpp
M flang/lib/Semantics/check-data.h
M flang/lib/Semantics/check-deallocate.cpp
M flang/lib/Semantics/check-do-forall.cpp
M flang/lib/Semantics/check-if-stmt.cpp
M flang/lib/Semantics/check-nullify.cpp
M flang/lib/Semantics/check-select-rank.cpp
M flang/lib/Semantics/check-select-type.cpp
M flang/lib/Semantics/check-stop.cpp
M flang/lib/Semantics/compute-offsets.cpp
M flang/lib/Semantics/mod-file.cpp
M flang/lib/Semantics/pointer-assignment.cpp
M flang/lib/Semantics/resolve-labels.cpp
M flang/lib/Semantics/resolve-names-utils.cpp
M flang/lib/Semantics/resolve-names-utils.h
M flang/lib/Semantics/runtime-type-info.cpp
M flang/lib/Semantics/scope.cpp
M flang/lib/Support/LangOptions.cpp
M flang/lib/Support/Version.cpp
M flang/lib/Testing/fp-testing.cpp
Log Message:
-----------
[flang][NFC] Remove unnecessary #include directives across flang (#207640)
Audit of every #include directive in flang/lib/ and
flang/include/flang/:
- Remove 423 #include directives (293 from lib/ translation units, 23
from lib-private headers, 107 from public headers) that are not needed:
no entity declared by the removed header is used - directly or in any
conditional-compilation branch (Windows, macOS, ARM/PowerPC,
REAL(16)/REAL(2) configuration macros) - in the including file, and for
headers no consumer in flang/lib, flang/tools, flang/unittests, or
flang-rt relies on the include as a re-export. Load-bearing includes
were examined and retained: textual .inc/.def expansions, tablegen
pass-header declaration/definition pairings, dialect headers carrying
generated-op interface dependencies, config-macro providers (e.g.
float128.h ahead of matmul-instances.inc guards), and ADL formatting
machinery (Evaluate/formatting.h).
- Add 5 missing direct #includes in lib translation units that used
entities only via now-removed transitive includes, and drop one
vestigial 'using namespace Fortran::runtime;' whose declaring header no
longer arrives transitively (nothing namespace-qualified from it was
used), per the include rules in flang/docs/C++style.md.
Assisted-by: AI
Commit: aaeac36566967650fcd63797a10da065eaedd90f
https://github.com/llvm/llvm-project/commit/aaeac36566967650fcd63797a10da065eaedd90f
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
M flang/test/Fir/target-rewrite-arg-position.fir
Log Message:
-----------
[flang][TargetRewrite] Keep argument attributes consistent after ABI arg shift (#208124)
When target-rewrite expands an argument into several arguments
(for example splitting a complex value into two scalars),
the arguments after it shift to the right.
Argument attributes were only moved for a shift introduced
by result lowering, so an attribute on a later argument
(e.g. fir.host_assoc) could stay on its old index and end up
on an unrelated argument. Remap every saved argument
attribute to the new index of its argument.
This is a consistency fix and may not cause a miscompile today.
Commit: d6c0a0a6a5c762fd327001c177490ee4c49ca718
https://github.com/llvm/llvm-project/commit/d6c0a0a6a5c762fd327001c177490ee4c49ca718
Author: jinge90 <ge.jin at intel.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M libc/config/gpu/amdgpu/entrypoints.txt
M libc/config/gpu/nvptx/entrypoints.txt
Log Message:
-----------
[libc][complex] Add basic complex ops including carg/cabs for GPU (#207887)
This PR adds carg and cabs for AMD GPU and also add all other basic
complex ops for NV GPU.
Signed-off-by: jinge90 <ge.jin at intel.com>
Commit: 478bbbeb0bdd7d186f308dccfa634280afaf0c00
https://github.com/llvm/llvm-project/commit/478bbbeb0bdd7d186f308dccfa634280afaf0c00
Author: hev <wangrui at loongson.cn>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
A llvm/test/CodeGen/LoongArch/lasx/xvexth.ll
A llvm/test/CodeGen/LoongArch/lsx/vexth.ll
Log Message:
-----------
[LoongArch][NFC] Add vector widening extends tests (#207315)
Commit: e60dc90e3134975afb1a951f792b71d4b648877f
https://github.com/llvm/llvm-project/commit/e60dc90e3134975afb1a951f792b71d4b648877f
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
M llvm/test/CodeGen/Hexagon/shadow-call-stack.ll
Log Message:
-----------
[Hexagon] Disable restore stubs when ShadowCallStack is active (#206302)
The returning restore stubs (e.g.
__restore_r16_through_r17_and_deallocframe) perform deallocframe+jumpr
r31 internally, returning via the on-stack return address. This is
incompatible with ShadowCallStack, which must restore r31 from the
shadow stack before returning.
Fix by having useRestoreFunction() return false when the ShadowCallStack
attribute is present, forcing inline callee-saved restores so the SCS
epilogue is properly emitted.
Commit: 4708581453ead90685a55e343cc5ace1e1ddabb1
https://github.com/llvm/llvm-project/commit/4708581453ead90685a55e343cc5ace1e1ddabb1
Author: hev <wangrui at loongson.cn>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/test/CodeGen/LoongArch/lasx/xvexth.ll
M llvm/test/CodeGen/LoongArch/lsx/vexth.ll
Log Message:
-----------
[LoongArch] Add DAG combines for vector widening extends (#207316)
Lower:
```
SEXT/ZEXT(High-Half-128-Bit-Lanes(vec))
```
to:
```
LSX: VEXTH.H.B, VEXTH.W.H, VEXTH.D.W
VEXTH.HU.BU, VEXTH.WU.HU, VEXTH.DU.WU
LASX: XVEXTH.H.B, XVEXTH.W.H, XVEXTH.D.W
XVEXTH.HU.BU, XVEXTH.WU.HU, XVEXTH.DU.WU
```
Commit: 63122f54df24161899609449e92589f3db556bf4
https://github.com/llvm/llvm-project/commit/63122f54df24161899609449e92589f3db556bf4
Author: Jessica Clarke <jrtc27 at jrtc27.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
Log Message:
-----------
[NFC][ELF] Don't reimplement addReloc in MipsGotSection::addConstant (#208130)
This is a repeat of d48eb719d240 ("[NFC][ELF] Don't reimplement addReloc
in GotSection::addConstant") but for MipsGotSection. Unfortunately,
9fb61d972213 ("[NFCI][ELF][Mips] Refactor MipsGotSection to avoid
explicit writes (#178561)") was put up for review before, and was landed
after, that commit, and I did not think to update it, so it ended up
copying the old GotSection code. Although there's no motivation to
support CHERI in this code (even though CHERI-MIPS existed it never used
the highly-specialised MipsGotSection to hold capabilities), it's still
better to use our own abstractions, and to be consistent.
Fixes: 9fb61d972213 ("[NFCI][ELF][Mips] Refactor MipsGotSection to avoid
explicit writes (#178561)")
Commit: 5a924bf3962c7f0c84e2de46172cd1d01ae3a67d
https://github.com/llvm/llvm-project/commit/5a924bf3962c7f0c84e2de46172cd1d01ae3a67d
Author: Orphic Dreamer <160723353+Siya-05 at users.noreply.github.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/CodeGen/TargetInfo.cpp
M clang/lib/CIR/CodeGen/TargetInfo.h
A clang/lib/CIR/CodeGen/Targets/NVPTX.cpp
A clang/test/CIR/CodeGenCUDA/surface.cu
Log Message:
-----------
[CIR][CUDA] Support built-in CUDA surface type (#196079)
Related: #179278
This patch adds initial support for CUDA built-in surface types in CIR
for device-side compilation.
CUDA surface references are lowered to the NVPTX device-handle
representation (`i64`), matching existing Clang CodeGen behavior.
Changes
* Add `getCUDADeviceBuiltinSurfaceDeviceType()` target hook to
`TargetCIRGenInfo`
* Implement NVPTX surface lowering in `NVPTXTargetCIRGenInfo`
* Handle CUDA built-in surface types in `CIRGenTypes::convertType`
* Add CIR CUDA test coverage for device-side surface lowering
Notes
* This patch only implements device-side surface type lowering support
* Texture types remain unsupported
* TBAA handling for surface/texture types is left for follow-up work
---------
Co-authored-by: mencotton <mencotton0410 at gmail.com>
Co-authored-by: David Rivera <davidriverg at gmail.com>
Co-authored-by: Andy Kaylor <akaylor at nvidia.com>
Commit: 1cefbacdaa0156880d8363b24ae04638a8fd31c8
https://github.com/llvm/llvm-project/commit/1cefbacdaa0156880d8363b24ae04638a8fd31c8
Author: Petr Hosek <phosek at google.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libcxx/src/include/overridable_function.h
Log Message:
-----------
[libc++] Replace the of use custom sections for detecting overriden functions (#175896)
This is a follow up to #133876 and an alternative to #120805 which
doesn't rely on aliases and works across both ELF and Mach-O. This
mechanism is preferable in baremetal environments since it doesn't
require special handling of the custom sections.
Commit: 333edde4e80e02d6fe5e866abf317969b66c0b8e
https://github.com/llvm/llvm-project/commit/333edde4e80e02d6fe5e866abf317969b66c0b8e
Author: yonghong-song <yhs at fb.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/lib/CodeGen/Targets/BPF.cpp
A clang/test/CodeGen/bpf-struct-return-regs.c
A clang/test/CodeGen/bpf-struct-return.c
A llvm/test/CodeGen/BPF/aggr_ret_regs.ll
Log Message:
-----------
[BPF] Return small aggregates directly in registers (#206876)
Previously the BPF ABI always returned aggregate (struct/union) types
indirectly through an sret pointer, regardless of size. This is
inconsistent with how classifyArgumentType() already passes small
aggregates: arguments up to 128 bits are coerced into one or two 64-bit
registers, while only larger aggregates use an indirect reference.
Make classifyReturnType() mirror that convention by factoring the shared
aggregate handling into a classifyAggregateType() helper used by both:
- empty aggregates (0 bits) are ignored;
- aggregates up to 64 bits are returned directly, coerced to an integer
of the padded size;
- aggregates of 65..128 bits are returned directly as [2 x i64];
- aggregates larger than 128 bits are returned indirectly via sret.
This keeps each returned value within the backend's two-register return
convention and avoids an unnecessary memory round-trip for small
structs.
This also aligns BPF with the general-purpose C ABIs of other targets:
both x86-64 (System V, RAX:RDX) and AArch64 (AAPCS64, X0:X1) return
aggregates up to 16 bytes in a pair of registers and only fall back to
an indirect sret pointer for larger ones.
Co-authored-by: Yonghong Song <yonghong.song at linux.dev>
Commit: 2b080317511d3285c7376e25ee9668edcc41c06e
https://github.com/llvm/llvm-project/commit/2b080317511d3285c7376e25ee9668edcc41c06e
Author: Jackson Stogel <jtstogel at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/OpenACC/Analysis/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Port 9a1f5b76b4 (#208126)
Commit: 6eb35326147077a18f6fc56540059d779d7e3d4b
https://github.com/llvm/llvm-project/commit/6eb35326147077a18f6fc56540059d779d7e3d4b
Author: Shreeyash Pandey <shrpand at qti.qualcomm.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M libunwind/test/aarch64_za_unwind.pass.cpp
Log Message:
-----------
[libunwind] include alloca.h in test/aarch64_za_unwind.pass.cpp (#207376)
Glibc provides the alloca function as a part of stdlib.h when
_GNU_SOURCE is declared (which is the case with standard linux builds).
[1]
On non-glibc systems, this may not be the case (for example, picolibc).
These libraries may not implicitly include alloca.h as a part of the
standard lib.
[1]
https://github.com/bminor/glibc/blob/04e750e75b73957cf1c791535a3f4319534a52fc/stdlib/stdlib.h#L728
Signed-off-by: Shreeyash Pandey <shrpand at qti.qualcomm.com>
Commit: 7ca17050c766ff1a1bd4bc74525f018ba1d9a104
https://github.com/llvm/llvm-project/commit/7ca17050c766ff1a1bd4bc74525f018ba1d9a104
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CGCoroutine.cpp
M clang/test/CodeGenCoroutines/coro-elide.cpp
M clang/test/CodeGenCoroutines/coro-halo.cpp
M clang/test/CodeGenCoroutines/pr65018.cpp
Log Message:
-----------
[CodeGen] Set attributes on coroutine wrapper functions (#207961)
Call SetInternalFunctionAttributes() so that target feature attributes
get set. This ensures that inlining works without having to reason about
target-specific inline compatibility logic.
Commit: e6525149c347a4787dd82ce5d2663bc577afd4a3
https://github.com/llvm/llvm-project/commit/e6525149c347a4787dd82ce5d2663bc577afd4a3
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang-tools-extra/clang-tidy/cppcoreguidelines/SpecialMemberFunctionsCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/special-member-functions-implicit-delete.cpp
Log Message:
-----------
[clang-tidy] Fix AllowImplicitlyDeletedCopyOrMove missing-move false positive (#207586)
The documentation for `cppcoreguidelines-special-member-functions` says
that `AllowImplicitlyDeletedCopyOrMove` suppresses diagnostics for
classes which implicitly delete copy or move operations.
In practice, the move operations are missing because the user-declared
destructor prevents their implicit declaration. This commit suppresses
that missing-move diagnostic when both copy operations are implicitly
deleted and no move operation is user-declared.
Godbolt: https://clang-tidy.godbolt.org/z/h1nT84Tee
Closes https://github.com/llvm/llvm-project/issues/196615
Commit: 70df3ccef10d336d3644df293fddb2adcb36e097
https://github.com/llvm/llvm-project/commit/70df3ccef10d336d3644df293fddb2adcb36e097
Author: Petr Hosek <phosek at google.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M libcxx/src/include/overridable_function.h
Log Message:
-----------
Revert "[libc++] Replace the of use custom sections for detecting overriden functions" (#208157)
Reverts llvm/llvm-project#175896 since it broke the build of internal
symbolizer used by sanitizers.
Commit: e7195d5d23adf9336555e7244e2fcf397111c57e
https://github.com/llvm/llvm-project/commit/e7195d5d23adf9336555e7244e2fcf397111c57e
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
A llvm/test/Transforms/LoopInterchange/debug-record-after-phi.ll
Log Message:
-----------
[LoopInterchange] Fix crash when dbg_value exists right after PHI (#208147)
When enabling reduction2mem with `-loop-interchange-reduction-to-mem`
and the input IR contains `dbg_value`s immediately after a certain PHI
node, assertion failure could be triggered due to the insertion position
of newly created PHI node. This patch fixes the issue by changing
IRBuilder ctor to be called. TBH, I'm not entirely sure what the
difference is between `IRBuilder::IRBuilder(Instruction *)` and
`IRBuilder::IRBuilder(BasicBlock *, BasicBlock::iterator)`, but judging
from the generated code, the behavior with this patch seems reasonable.
Taken over from #183273
Commit: c279890c85da307abe34f10333442bbf72a60644
https://github.com/llvm/llvm-project/commit/c279890c85da307abe34f10333442bbf72a60644
Author: Haibo Jiang <jianghaibo9 at huawei.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Passes/IndirectCallPromotion.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
A bolt/test/AArch64/icp-inline.c
A bolt/test/AArch64/icp.c
M bolt/test/AArch64/unsupported-passes.test
Log Message:
-----------
[BOLT][AArch64] Support call ICP (#208158)
* extends MCPlusBuilder with comparision between registers.
* updates the ICP pass to request a scavenged register for AArch64
callsites.
* wires ICP code generation on AArch64.
Commit: 475f7026055c77007d19c708ed13465a4206dfee
https://github.com/llvm/llvm-project/commit/475f7026055c77007d19c708ed13465a4206dfee
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaExpr.cpp
M clang/test/SemaTemplate/fun-template-def.cpp
Log Message:
-----------
[Clang] No longer reject call expression whose type is a not-yet-deduced auto type. (#208007)
This fixes a regression introduced in #139246
Fixes #207565
Commit: 62907d4a3bb330f79f41f548bfa836223c12735e
https://github.com/llvm/llvm-project/commit/62907d4a3bb330f79f41f548bfa836223c12735e
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/test-issue-98598.ll
Log Message:
-----------
[PowerPC] Fix combineSignExtendSetCC() for large/small types (#207721)
The code should reject larger types (like i128) and zero-extend smaller
types (like i8 and i16). Consolidate the handling based on being
smaller/larger than OpVT to reduce the number of PPC64 conditions.
Commit: 35678db1b4dbf7e14ad5238eee5590bf32aebb87
https://github.com/llvm/llvm-project/commit/35678db1b4dbf7e14ad5238eee5590bf32aebb87
Author: SiHuaN <liyongtai at iscas.ac.cn>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsRISCV.td
M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
M clang/lib/Headers/riscv_packed_simd.h
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
Log Message:
-----------
[Clang][RISCV] packed absolute difference sum intrinsics (#207936)
Add the __riscv_pabdsumu/pabdsumau_* header wrappers over new
__builtin_riscv_* builtins, lowering to the
llvm.riscv.pabdsumu/pabdsumau intrinsics.
Commit: ea6d5c6a2e37705688c74167990115e535058065
https://github.com/llvm/llvm-project/commit/ea6d5c6a2e37705688c74167990115e535058065
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
Log Message:
-----------
[MLIR][XeGPU] Fix blocking pass for scf.if distribution (#207060)
Commit: b5ed0ae6bc70792cb9749444b2803c3fa72276e4
https://github.com/llvm/llvm-project/commit/b5ed0ae6bc70792cb9749444b2803c3fa72276e4
Author: Javed Absar <javed.absar at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationEnums.td
M mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.td
A mlir/include/mlir/Dialect/Bufferization/Transforms/StaticMemoryPlanning.h
M mlir/lib/Dialect/Bufferization/Transforms/CMakeLists.txt
M mlir/lib/Dialect/Bufferization/Transforms/StaticMemoryPlannerAnalysis.cpp
A mlir/lib/Dialect/Bufferization/Transforms/StaticMemoryPlanning.cpp
A mlir/test/Dialect/Bufferization/Transforms/static-memory-planner-best-fit.mlir
Log Message:
-----------
[mlir][bufferization] Add best-fit algorithm to static memory planner (#207403)
Introduces an algorithm selection option to the static memory planner
pass and adds a best-fit algorithm that reuses memory from expired allocations by
finding the smallest suitable gap.
I have tested the correctness of the best-fit algorithm with an
independent randomized verifier.
Signed-off-by: mabsar <mabsar at qti.qualcomm.com>
Commit: f02b48182be73c531fb83312da15c85031fadde3
https://github.com/llvm/llvm-project/commit/f02b48182be73c531fb83312da15c85031fadde3
Author: Krisitan Erik Olsen <kristian.erik at outlook.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Analysis/AssumptionCache.cpp
A llvm/test/Transforms/DropUnnecessaryAssumes/duplicate-affected-value.ll
Log Message:
-----------
[AssumptionCache] Deduplicate affected values in removeAffectedValues (#205441)
removeAffectedValues can encounter duplicate entries in the Affected
list when a separate_storage bundle uses the same pointer for both
arguments (e.g. "separate_storage"(ptr %p, ptr %p)). The duplicate
entries share both the same value and the same bundle index. The first
iteration handles the value completely and may erase the AffectedValues
entry, causing the second iteration to fail the assertion.
This patch deduplicates entries in removeAffectedValues by (Value *,
Index) pair, matching the deduplication already done in
updateAffectedValues. This also fixes the ExpectedMatches counting in
the debug logic added by #205275, which otherwise miscounts when
duplicates are present.
Fixes #205378.
Commit: 063ac503e44ff17dda84698375091fa5b8b53557
https://github.com/llvm/llvm-project/commit/063ac503e44ff17dda84698375091fa5b8b53557
Author: lrzlin <linrunze at loongson.cn>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
A llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-any-ext.ll
M llvm/test/CodeGen/LoongArch/lasx/vxi1-masks.ll
Log Message:
-----------
[LoongArch] Lower ANY_EXTEND to ZERO_EXTEND under LASX to avoid scalarization (#201099)
Some integer/floating-point conversion will generate ANY_EXTEND under
LASX, lowering it to ZERO_EXTEND to avoid scalarization.
Commit: 459cadfaf12cde6b1fda2fde932b277f1630c124
https://github.com/llvm/llvm-project/commit/459cadfaf12cde6b1fda2fde932b277f1630c124
Author: Emmett <emmettzhang2020 at outlook.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M libcxx/docs/Status/Cxx26Issues.csv
M libcxx/include/__chrono/duration.h
M libcxx/include/chrono
A libcxx/test/std/time/time.duration/duration.verify.cpp
Log Message:
-----------
[libc++][chrono] Implement LWG 4481: Disallow `chrono::duration<const T, P>` (#207558)
Commit: 006423944b8efdb115d8fd001cffca888605cd7f
https://github.com/llvm/llvm-project/commit/006423944b8efdb115d8fd001cffca888605cd7f
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
M mlir/test/Conversion/ArithToSPIRV/arith-to-spirv.mlir
M mlir/test/Conversion/ArithToSPIRV/fast-math.mlir
Log Message:
-----------
[mlir][SPIR-V] Lower arith.maxnumf/minnumf to spirv.GL.NMax/NMin (#205975)
The previous lowering targeted spirv.GL.FMax/FMin + NaN guards
spirv.GL.NMax/NMin natively treat NaN as missing, matching
arith.maxnumf/minnumf exactly (no guards required)
Commit: 1d387731334d04f677804a09f29e0863ca977e0c
https://github.com/llvm/llvm-project/commit/1d387731334d04f677804a09f29e0863ca977e0c
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-epilogue-vec.ll
A llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-vscale-x-UF-step.ll
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[LV] Allow setting scalable VFs for `-epilogue-vectorization-force-VF` (#205081)
Follow up to #204953. This allows replacing a unit test with an IR test.
Commit: 736771b6a017b5a18c03819a3348ff793c473261
https://github.com/llvm/llvm-project/commit/736771b6a017b5a18c03819a3348ff793c473261
Author: Chirag Patel <chirag198838 at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGenTypes/MachineValueType.h
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
Log Message:
-----------
[DAG] Adding MVT::widenIntegerElementType to widen both Scalar and Vectors of integer type. (#207148)
Adding MVT::widenIntegerElementType to widen both Scalar and Vectors of
integer type. e.g. i16 -> i32, v8i32->v8i64.
fixes #206730
Commit: e1187834d342ae7890884dbc1ef69de7b5d9fdc1
https://github.com/llvm/llvm-project/commit/e1187834d342ae7890884dbc1ef69de7b5d9fdc1
Author: zip-stack-debug <doremyalt at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/div-i256.ll
M llvm/test/CodeGen/AArch64/sbc-add-constant.ll
Log Message:
-----------
[AArch64][DAG] Port adde and sube combine to AArch64 (#202227)
Same principles apply in AArch64 as they do in ARM.
Commit: 529c7d563bac018b8ea43ea8017c113ee384c004
https://github.com/llvm/llvm-project/commit/529c7d563bac018b8ea43ea8017c113ee384c004
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/PassManagerInternal.h
Log Message:
-----------
[IR][NFC] Make PassConcept immovable (#208167)
PassConcept is only ever created as a unique_ptr when added to the pass
list of a pass manager. The instances are never copied or moved. Due to
inheritance, this also wouldn't work anyway. Explicitly forbid
copying/moving and remove the dead functions.
Preliminary work for removing the vtable from PassConcept/PassModel.
Commit: 32d06af3ea6d05c0f8b5820da3f651d4e03bb80d
https://github.com/llvm/llvm-project/commit/32d06af3ea6d05c0f8b5820da3f651d4e03bb80d
Author: David Green <david.green at arm.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/test/CodeGen/Thumb2/vqabs.ll
M llvm/test/CodeGen/Thumb2/vqneg.ll
Log Message:
-----------
[ARM][MVE] Tests for new sqabs and sqneg tests. NFC (#208180)
Commit: 3451dd23d9b098e8cf7201ab303874dab2d88c19
https://github.com/llvm/llvm-project/commit/3451dd23d9b098e8cf7201ab303874dab2d88c19
Author: Ricardo Jesus <rjj at nvidia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/arm64-fp128.ll
M llvm/test/CodeGen/AArch64/arm64-neon-v1i1-setcc.ll
M llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
M llvm/test/CodeGen/AArch64/fcmp.ll
M llvm/test/CodeGen/AArch64/sme-aarch64-svcount.ll
M llvm/test/CodeGen/AArch64/sve-select.ll
Log Message:
-----------
[AArch64] Fold any/sign-extend of CSET. (#207414)
This is useful to enable selecting i64 CSETM when legalisation places an
extend between a CSET and sext_inreg.
Commit: 302f7aa18e0d68d9db74c2586bd66ef8e4d98e53
https://github.com/llvm/llvm-project/commit/302f7aa18e0d68d9db74c2586bd66ef8e4d98e53
Author: Aayush Shrivastava <iamaayushrivastava at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
A llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops-i1.ll
Log Message:
-----------
[VectorCombine] Fold concat(binop(a,c), binop(b,d)) -> binop(concat(a,b), concat(c,d)) for i1 vectors (#206087)
Fixes #205707
`VectorCombine::foldShuffleOfBinops` rewrites `shuffle(binop(a,c),
binop(b,d))` into `binop(shuffle(a,b), shuffle(c,d))` but only when the
new form is strictly cheaper. For concat shuffles of i1 vectors, both
forms have equal cost, so the transform was silently rejected.
This fix allows the equal-cost transform when both binops are single-use
`BinaryOperators` (not icmps, to avoid widening narrow AVX-512
comparisons), canonicalising the IR to a wider binop.
The motivating case is AVX-512 mask operations: `NOT(concat(XOR(a,c),
XOR(b,d)))` becomes `NOT(XOR(concat(a,b), concat(c,d)))`, which the
backend naturally selects as `kxnorq`, reducing `kxord + kxord +
kunpckdq + knotq` (4 instructions) to `kunpckdq + kunpckdq + kxnorq` (3
instructions).
Commit: 764645b5ef49b18b2ca7c3efc3ca6954e1337f1b
https://github.com/llvm/llvm-project/commit/764645b5ef49b18b2ca7c3efc3ca6954e1337f1b
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
M llvm/test/CodeGen/X86/avx512fp16-combine-shuffle-fma.ll
M llvm/test/CodeGen/X86/vector-narrow-binop.ll
M llvm/test/CodeGen/X86/vector-reduce-fmul-fast.ll
Log Message:
-----------
[SDAG][X86] Support shrinking target-independent nodes (#206721)
X86 generally tries to shrink operations to work on smaller vector sizes
if possible. This happens in
SimplifyDemandedVectorEltsForTargetNode() for target-specific opcodes,
but it's currently not possible to do this for generic opcodes.
This introduces a getPreferredShrunkVectorSize() TLI hook to allow
shrinking generic ops based on demanded elements.
The primary motivation for this is to avoid regressions due to
https://github.com/llvm/llvm-project/pull/188489, which uplifts a
previously x86-specific node to become target-independent.
This PR enables the shrinking for fsub and fmul as examples.
Unfortunately, for many other ops we get various regressions, mostly
because horizontal operations are no longer formed.
Commit: 3fc15b50c6e5b79332023fe7ccacb35b2ed5614e
https://github.com/llvm/llvm-project/commit/3fc15b50c6e5b79332023fe7ccacb35b2ed5614e
Author: Sean Clarke <sclarke at tenstorrent.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Analysis/HashRecognize.cpp
M llvm/test/Analysis/HashRecognize/cyclic-redundancy-check.ll
M llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check.ll
Log Message:
-----------
[HashRecognize] Make `LHSAux` null if it is dead (#207231)
HashRecognize detects big-endian CRC loops with auxiliary data where the
bitwidth of `LHS` exceeds that of `LHSAux`. However, in this case,
`LHSAux` is zero-extended for the most significant bit check in each
iteration, and as such is effectively dead. Later optimization may even
miscompile in this case: for example, in the included
`crc16.be.tc8.zext.data` and `crc16.be.tc8.misalign` test cases,
`optimizeCRCLoop` emits `lshr i8 %crc.data.indexer, 8`, thereby creating
poison.
Since `LHSAux` is dead in this case, the user should receive a null
`LHSAux` instead.
Commit: 475cef62595255a34b795472bba330a60058abb0
https://github.com/llvm/llvm-project/commit/475cef62595255a34b795472bba330a60058abb0
Author: Keshav Vinayak Jha <31160700+keshavvinayak01 at users.noreply.github.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
Log Message:
-----------
[SelectionDAG][AMDGPU] Preserve known bits for demoted sret pointers (#203468)
AMDGPU marks sret pointers with high-zero known bits so stores can be
folded into MUBUF base+offset addressing. Explicit sret arguments keep
this information through an AssertZext, but implicit sret lowering
passes the hidden return pointer through `DemoteRegister` as a
`CopyToReg/CopyFromReg` pair, where the fact is not visible to
SelectionDAG known-bits queries.
Add a `TargetLowering` hook for sret pointer known bits and use a shared
helper to materialize those bits as an `AssertZext` for both explicit
and demoted sret pointers.
Validated with llvm-test-depends, the AMDGPU function-returns test, and
the full llvm/test/CodeGen suite.
Assisted-by: Codex
---------
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Commit: 29553517d044e1864b6dd00b0236006ae999d043
https://github.com/llvm/llvm-project/commit/29553517d044e1864b6dd00b0236006ae999d043
Author: Hongyu Chen <xxs_chy at outlook.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-reverse.ll
Log Message:
-----------
[RISCV][P-ext] Improve codegen for packed reverse intrinsics (#207575)
This patch improves the codegen for vector reverse for RVP.
Commit: 74e44e433a8e1da3da263833e32adde77889f734
https://github.com/llvm/llvm-project/commit/74e44e433a8e1da3da263833e32adde77889f734
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/test/tools/llvm-ar/arm64x-hybridobj.yaml
M llvm/test/tools/llvm-lib/arm64x-hybridobj.yaml
M llvm/test/tools/llvm-readobj/COFF/arm64x-hybridobj.yaml
Log Message:
-----------
[llvm-readobj][llvm-ar][COFF] Use exclude for .obj.arm64ec section in tests (NFC) (#208116)
For consistency with #207612.
Commit: cab8bab9642c33ea42355806730ed431d5cbf205
https://github.com/llvm/llvm-project/commit/cab8bab9642c33ea42355806730ed431d5cbf205
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Forbid CSE'ing writes (NFC) (#207443)
CSE'ing two identical writes does not consider the fact that there could
be another write that writes an aliasing memory location. Fix the
potential miscompile. Note that there is currently no miscompile, as we
never remove a write, but the patch has the benefit of not processing
writes unnecessarily.
Commit: 17b27e7c2cb6267695733969bfca2d5ebb4a0c23
https://github.com/llvm/llvm-project/commit/17b27e7c2cb6267695733969bfca2d5ebb4a0c23
Author: David Green <david.green at arm.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64Processors.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/mul.ll
Log Message:
-----------
[AArch64] Increase the relative cost of vector i64 multiply on Neoverse V3ae. (#207723)
The throughput of vector nxv2i64 multiplies on neoverse v3ae is 1/2, compared
to the throughput of 2 for integer multiplies. This large difference can mean
it is more profitable than normal to use scalar loops as opposed to vectorization.
This adds a subtarget feature that increases the cost multiple by 4 for 64bit
vector multiplies for specific CPUs. The cost model of llvm does not mean that
we can model throughputs correctly, but this should help. The same feature is
added to N2 as it has a similar difference between vector and scalar multiply
cost throughputs.
Commit: 9ab13dc4f7ff3c536e493947781ae344bb4be69a
https://github.com/llvm/llvm-project/commit/9ab13dc4f7ff3c536e493947781ae344bb4be69a
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M mlir/lib/Conversion/ComplexToSPIRV/ComplexToSPIRV.cpp
M mlir/test/Conversion/ComplexToSPIRV/complex-to-spirv.mlir
Log Message:
-----------
[mlir][ComplexToSPIRV] Add lowering for complex.eq and complex.neq (#206279)
Commit: e1f7b53881066bfd6b6d1628e873002bd8ff99a7
https://github.com/llvm/llvm-project/commit/e1f7b53881066bfd6b6d1628e873002bd8ff99a7
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M lld/COFF/Driver.cpp
A lld/test/COFF/arm64x-hybridobj.s
Log Message:
-----------
[LLD][COFF] Add support for multi-arch ARM64X object files (#207868)
Commit: eb4690c251141b7d4ef31f321acc6fb3dc09a1bf
https://github.com/llvm/llvm-project/commit/eb4690c251141b7d4ef31f321acc6fb3dc09a1bf
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M flang/include/flang/Evaluate/tools.h
M flang/lib/Evaluate/tools.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertExprToHLFIR.cpp
A flang/test/Lower/split-sum-expression-tree-lowering.f90
Log Message:
-----------
[flang][Lower] Add alternative real expression lowering (#207371)
This is opt-in by an engineering option and disabled by default.
In section 10.1.5.2.4 of the 2023 Fortran standard "Evaluation of
numerical intrinsic operations", the standard explicitly allows
alternate mathematically equivalent lowerings. For example the source
expression X + Y + Z could be evaluated (X + Y) + Z, X + (Y + Z) or even
(X + Z) + Y, etc.
The open source benchmark SNBone shows significantly better results with
classic flang because classic flang emits real arithmetic expressions in
a different order. In the case of this benchmark it reduces dependency
depth for instructions issued to the vector unit, allowing for more of
the arithmetic to be parallelised over multiple vector execution units
in the ALU.
The lowering added by this patch tries to mimic the way classic flang
orders instructions for these expressions. I did not read any classic
flang source when writing this patch. There is still a notable
difference in that classic flang uses FMA intrinsics whereas LLVM Flang
relies on the rest of the pipeline to introduce FMA when it is safe to
do so.
This is a much less aggressive optimisation than simply enabling reassoc
in the fast-math flags because it does not allow reassociation between
Fortran language statements. This is why I implemented it in lowering.
The new option enables an experimental lowering path for scalar real
top-level addition chains. When enabled with
-enable-split-sum-expression-tree-lowering, eligible sums are split
after the first two terms and rebuilt as a right-associated tail plus
head. This lets the independent tail terms be evaluated before the
assignment-related head, giving the backend a different expression tree
while leaving the default lowering unchanged.
The transform is deliberately narrow. It only applies to scalar real RHS
expressions in assignments and rejects cases with vector subscripts,
parentheses, subtraction, procedure references, or volatile/asynchronous
symbols on either side of the assignment. Subtraction is left out
because the split would need to carry signed terms; division stays
within an individual additive term and does not change the top-level
chain.
In testing I have found some tests in the Fujitsu test suite miscompare
due to small changes in floating point rounding. There are no failures
or regressions in SPEC2017 or SPEC2026. I think it would be legal
according to the Fortran standard to enable this by default, but I am
not proposing that here, and will not consider it until after the LLVM
release branch point.
Assisted-by: Codex
Commit: dcf1b8f2c00b38777f71297afc7b575cd2d9300a
https://github.com/llvm/llvm-project/commit/dcf1b8f2c00b38777f71297afc7b575cd2d9300a
Author: Oleksandr Tarasiuk <oleksandr.tarasiuk at outlook.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang-tools-extra/clang-doc/Serialize.cpp
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/ASTStructuralEquivalence.h
M clang/include/clang/AST/DeclFriend.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/Basic/DeclNodes.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/Template.h
M clang/include/clang/Sema/TemplateDeduction.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ASTStructuralEquivalence.cpp
M clang/lib/AST/DeclFriend.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/ODRHash.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaAccess.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/test/CXX/class.access/class.friend/p3-cxx0x.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg19xx.cpp
M clang/test/CXX/drs/cwg28xx.cpp
M clang/test/CXX/drs/cwg6xx.cpp
M clang/test/CXX/temp/temp.decls/temp.friend/p5.cpp
A clang/test/CXX/temp/temp.decls/temp.friend/p6.cpp
M clang/test/Parser/cxx2c-variadic-friends.cpp
M clang/test/SemaCXX/many-template-parameter-lists.cpp
M clang/test/SemaTemplate/GH71595.cpp
M clang/test/SemaTemplate/concepts-friends.cpp
M clang/test/SemaTemplate/ctad.cpp
M clang/test/SemaTemplate/friend-template.cpp
Log Message:
-----------
[Clang] support friend declarations with a dependent nested-name-specifier (#191268)
Fixes #104057
---
This patch adds support for friend declarations with a dependent NNS
Commit: 293a55ce46a56accc10965712e77f4ba09f15322
https://github.com/llvm/llvm-project/commit/293a55ce46a56accc10965712e77f4ba09f15322
Author: Ömer Sinan Ağacan <omeragacan at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
Log Message:
-----------
[GlobalISel][AArch64] Remove IRs from inline-{memcpy,memmove} tests (NFC) (#208066)
Commit: cd854821ae5550350431146b8fe88005b29da257
https://github.com/llvm/llvm-project/commit/cd854821ae5550350431146b8fe88005b29da257
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
M llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.ll
M llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.mir
Log Message:
-----------
[AArch64] Add missing arithmetic to arith+cb(n)z clustering (#203721)
This patch adds a few missing opcodes for arithmetic+CB(N)Z clustering.
Most of them complement an already existing rr/rs variant for
pre/post-RA coverage. The only one which is completely new is ORN which
I think can be reasonably expected to behave similarly on AArch64
targets.
Commit: dd37265910a290887a16696de6f0dea1731ab4c8
https://github.com/llvm/llvm-project/commit/dd37265910a290887a16696de6f0dea1731ab4c8
Author: Jolyon <yangjian.c at bytedance.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
M llvm/include/llvm/Transforms/Utils/Local.h
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
M llvm/lib/Transforms/Utils/Local.cpp
Log Message:
-----------
[CodeGenPrepare] Cache known-live PHIs when deleting dead PHI chains (#207191)
This patch fixes a compile-time issue in CodeGenPrepare for huge
functions.
`DeleteDeadPHIs` may repeatedly prove overlapping PHI chains non-dead.
For very large functions, many PHIs can share the same non-dead def-use
suffix, causing the same suffix to be scanned many times.
Add an `KnownNonDeadPHIs` cache to `RecursivelyDeleteDeadPHINode`
and `DeleteDeadPHIs`. When a chain is proven non-dead, visited PHIs are
recorded so later queries can stop once they reach one of them.
This reduces the pathological CodeGenPrepare case from ~30mins to ~30s.
Commit: d582a7d2196077d98b97e74a537ec56120d7704c
https://github.com/llvm/llvm-project/commit/d582a7d2196077d98b97e74a537ec56120d7704c
Author: David Truby <david.truby at arm.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M flang-rt/lib/runtime/io-api-server.cpp
Log Message:
-----------
[flang-rt] Fix io-api-server when building for arm64ec (#207998)
Commit: 5f33a29bebe42a032a163a80e311d8ba305de3f6
https://github.com/llvm/llvm-project/commit/5f33a29bebe42a032a163a80e311d8ba305de3f6
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
Log Message:
-----------
[VPlan] Introduce VPConstant VPIRValue (NFC) (#207387)
There a gap in the VPIRValue class hierarchy, where constant live-ins
are absent, when this is in fact a very common case. The motivation of
introducing this new class is to refine optimizations to account for the
fact that non-constant live-ins need broadcast.
Commit: 2f07e6be216858d15e691b2a59514aa73db0f8dc
https://github.com/llvm/llvm-project/commit/2f07e6be216858d15e691b2a59514aa73db0f8dc
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/include/clang/AST/TypeBase.h
M clang/lib/AST/Type.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/CodeGenCXX/dynamic-cast-exact.cpp
Log Message:
-----------
[Clang] Fix missing vtable for `dynamic_cast<FinalClass &>(*this)` in a function template (#207349)
This is a follow-up to #202594, which fixed a pointer cast, but not
a reference cast. Surprisingly, `CXXDynamicCastExpr::getType()`
for a reference cast is a `RecordType` and not a `ReferenceType`.
How this happens:
In `Sema::BuildCXXNamedCast`, a `CastOperation Op` variable
is constructed. The `CastOperation` constructor initializes
`ResultType(destType.getNonLValueExprType(S.Context))`
where `QualType::getNonLValueExprType` turns a `ReferenceType` into
a `RecordType`. `Sema::BuildCXXNamedCast` then passes `Op.ResultType`
to `CXXDynamicCastExpr::Create`.
Commit: 024a691e7784e7ebe3783ddaf557ee07a127d934
https://github.com/llvm/llvm-project/commit/024a691e7784e7ebe3783ddaf557ee07a127d934
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/test/Transforms/LoopVectorize/AArch64/alias-mask.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll
Log Message:
-----------
[VPlan] Pull out reverses and splice.lefts from elementwise operations (#199234)
InstCombine pulls reverses up and out of operations, e.g.
`binop(reverse(x), reverse(y)) -> reverse(binop(x,y))`. This reduces the
overall number of reverses, and also allows the `reverse(reverse(x))`
combine to kick in much more.
This implements the same canonicalization in VPlan which allows for more
vectorization due to cost model improvements, and generally handles more
cases when there's predication involved.
If we have a reversed load and reversed store whose stores are now
eliminated, we will be left with just two reversed masks on the load and
store. But with EVL tail folding this will leave behind a
`splice.right(ops(splice.left(...)))` pair on the value from memory.
InstCombine can fold away a pair of `vp.reverse(ops(vp.reverse(...)))`,
but it can't fold a pair of splices. So to prevent regressions we also
have to pull splice.lefts like `ops(splice.left(poison, x, evl)) ->
splice.left(poison, ops(x), evl)`. The `splice.right(splice.left(x)) ->
x` VPlan transform will then kick in and remove it. We don't need to
pull splice.rights since they are only emitted at stores.
Commit: 4ddfd96314507b6a829b1df5afc5455f345ba38d
https://github.com/llvm/llvm-project/commit/4ddfd96314507b6a829b1df5afc5455f345ba38d
Author: ayrai-gb <ayrai at amd.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/IR/Instruction.cpp
M llvm/test/Transforms/SimplifyCFG/hoist-with-metadata.ll
Log Message:
-----------
[IR] Preserve !nofpclass in dropUBImplyingAttrsAndMetadata (#208186)
`!nofpclass` is a poison-generating metadata kind, so it should be
preserved by dropUBImplyingAttrsAndMetadata().
Commit: 9a465c3f2493bbdca2becb79450d4ee33306bd5d
https://github.com/llvm/llvm-project/commit/9a465c3f2493bbdca2becb79450d4ee33306bd5d
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M orc-rt/CMakeLists.txt
Log Message:
-----------
[orc-rt] Refactor CMakeLists.txt for readability. NFCI. (#208156)
Groups related options, adds comments and separators.
Commit: 0f174998859cfaa48e848bb44400522acd0c4dc3
https://github.com/llvm/llvm-project/commit/0f174998859cfaa48e848bb44400522acd0c4dc3
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Log Message:
-----------
[CodeGen][NFC] Remove stray SDag BFI computation with NewPM (#208181)
This looks like an accident -- there's no need to compute the
BlockFrequencyInfo unconditionally and then discarding it. After this,
enabling the NewPM CodeGen pipeline is faster than the legacy PM.
Commit: c1fd542e61749f3c6765f4d8293094e7064ebb18
https://github.com/llvm/llvm-project/commit/c1fd542e61749f3c6765f4d8293094e7064ebb18
Author: Ayaan <138162656+def3r at users.noreply.github.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/test/Transforms/InstCombine/rotate.ll
A llvm/test/Transforms/InstCombine/zext-sub-trunc.ll
Log Message:
-----------
[InstCombine] Fold zext(sub(0, trunc(X))) to and(sub(0, X), mask) (#207564)
Problem: vector rotate and funnel shift fails to fold for vectors > 16
bytes on AVX-512. This is because of the `trunc` and `zext`
instructions.
Example:
```llvm
define dso_local <8 x i64> @baz(<8 x i64> %0, <8 x i64> %1) local_unnamed_addr {
Entry:
%2 = trunc <8 x i64> %1 to <8 x i6>
%3 = sub <8 x i6> zeroinitializer, %2
%4 = zext <8 x i6> %3 to <8 x i64>
%5 = shl <8 x i64> %0, %4
%6 = and <8 x i64> %1, splat (i64 63)
%7 = lshr <8 x i64> %0, %6
%8 = or <8 x i64> %5, %7
ret <8 x i64> %8
}
```
Solution; Canonicalize the transformation `zext(sub(0, trunc(X))) ->
and(sub(0, X), mask)` for scalars and vectors.
Closes #165306
Commit: 76f49f834e057c028a9f42fddca7e3f522e1dda1
https://github.com/llvm/llvm-project/commit/76f49f834e057c028a9f42fddca7e3f522e1dda1
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
A llvm/test/Transforms/DFAJumpThreading/br-debuglocs.ll
A llvm/test/Transforms/DFAJumpThreading/br-debuglocs2.ll
Log Message:
-----------
[DFAJumpThreading] Propagate DebugLocs to branches in select unfolding (#205851)
When DFAJumpThreading replaces a select with control flow, it generates
new blocks, new branches in those blocks, and potentially replaces the
branch in an existing block. Prior to this patch, none of these branches
were assigned debug locations; this patch replaces them as follows:
For the case where we generate two new blocks between the select block
and use block, and use a PHI of those blocks to replace the select, we
use the select's debug location for the branch instructions, since they
are doing the work of the select.
For the case where we generate one new block and replace the
unconditional branch from the select block with a conditional branch to
the new block and the use block, we treat the new branches as replacing
both the select and the original branch, so each branch takes the merged
location of the original select+br.
This patch also ensures that when we create a new path which would end
with a switch statement, such that the switch statement can be safely
replaced with an unconditional branch, we propagate the switch's debug
location to the replacing unconditional branch.
Commit: 5166fea278a64988e166ae6d669b955d07544f13
https://github.com/llvm/llvm-project/commit/5166fea278a64988e166ae6d669b955d07544f13
Author: David Green <david.green at arm.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/uaddo-8-16-bits.mir
Log Message:
-----------
[AArch64][GlobalISel] Use integer types in applySimplifyUADDO (#207962)
This avoids creating some scalar types in the IR, using integer types
for constants from a uaddo combine instead.
Commit: b4b9fbb56271236f6415403b562c46fcb64016d5
https://github.com/llvm/llvm-project/commit/b4b9fbb56271236f6415403b562c46fcb64016d5
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/sa_family_t.h
M libc/test/src/sys/socket/linux/CMakeLists.txt
M libc/test/src/sys/socket/linux/bind_test.cpp
M libc/test/src/sys/socket/linux/connect_accept_test.cpp
M libc/test/src/sys/socket/linux/sockaddr_storage_helper.cpp
M libc/test/src/sys/socket/linux/sockaddr_storage_test.cpp
M libc/test/src/sys/socket/linux/sockname_test.cpp
Log Message:
-----------
[libc] Add a proxy header for sa_family_t (#207736)
This patch adds `hdr/types/sa_family_t.h` and updates socket tests and
helpers to use it instead of directly including `<sys/socket.h>` or
`include/llvm-libc-types/sa_family_t.h`.
The patch also adds a couple of includes of `hdr/types/socklen_t.h` for
files that are using the type, but not including it directly.
Assisted by Gemini.
Commit: 2d829f66147850c1fa9cd49c207b40c69aff5f17
https://github.com/llvm/llvm-project/commit/2d829f66147850c1fa9cd49c207b40c69aff5f17
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/docs/HowToUpdateDebugInfo.rst
M llvm/include/llvm/Transforms/Utils/Debugify.h
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/unittests/Transforms/Utils/DebugifyTest.cpp
Log Message:
-----------
[Debugify] Simplify debugify for locations (#207374)
This patch attempts to improve the performance of debugify for
locations, by relying on coverage tracking to replace most of the
functionality provided via the DILocations map, in exchange for losing
the ability to distinguish between "dropped" and "not-generated" bugs,
and requiring coverage tracking to determine when new bugs appear in a
pass instead of reporting the same bug repeatedly across passes.
This patch is not without cost; the justifications for using it are
that:
- Debugify locations is incredibly expensive; on a local build, without
using any coverage-tracking, this patch takes the build time for sqlite3
down from ~15 minutes to ~10 seconds.
- The difference between "dropped" and "not-generated" is a minor detail
of a bug - besides helping to determine the cause of the bug, which
origin-tracking can do with more accuracy, there's no fundamental
difference in the correctness of either. Furthermore, almost no
"dropped" bugs appear in the compiler anymore (since the debug location
coverage tracker bot has been online).
- Requiring coverage tracking to prevent repeated bugs is a loss, but
coverage tracking is not a very expensive feature to enable compared to
using debugify itself, and the only public automated tests that use
debugify already enable coverage tracking.
Commit: 95eef8c4b209036bc2fdce0891b43cb9170a46c5
https://github.com/llvm/llvm-project/commit/95eef8c4b209036bc2fdce0891b43cb9170a46c5
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/Instructions.h
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
Log Message:
-----------
[IR][NFC] Add LoadStoreProperties to copy load/store attrs (#206470)
Introduce a small `LoadStoreProperties` struct plus get/setAttributes on
`LoadInst` and `StoreInst` so volatile/align/ordering/syncscope can be
copied together instead of one field at a time. Switch the obvious load->load
and store->store clone sites over to it.
Commit: 179badc020b48f736341408fdb01537ada3eedfb
https://github.com/llvm/llvm-project/commit/179badc020b48f736341408fdb01537ada3eedfb
Author: Yusuke MINATO <minato.yusuke at fujitsu.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M flang/docs/FAQ.md
Log Message:
-----------
[flang][docs] Add a mention about -fsafe-trampoline to FAQ.md (#207656)
Co-authored-by: Tarun Prabhu <tarunprabhu at gmail.com>
Commit: 047011710642a63471fcdba64f009a0125f715bf
https://github.com/llvm/llvm-project/commit/047011710642a63471fcdba64f009a0125f715bf
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
A llvm/test/CodeGen/AArch64/sve-pred-ldst.ll
Log Message:
-----------
[LLVM][CodeGen][SVE] Make use of predicate load/store "mul vl" addressing mode. (#206997)
Commit: 2abc19543d802780eadd1450f0aa0c28fed080af
https://github.com/llvm/llvm-project/commit/2abc19543d802780eadd1450f0aa0c28fed080af
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M libc/fuzzing/arpa/inet/CMakeLists.txt
A libc/fuzzing/arpa/inet/inet_ntop_differential_fuzz.cpp
Log Message:
-----------
[libc] Add a differential fuzzer for inet_ntop (#207977)
The first byte of the input is used to select the address class and the
size of the output buffer. The rest is used as the input.
We compare the results and also check that our implementation does not
overflow the buffer.
Assisted by Gemini.
Commit: 6008f6735309d3efafa8680df04f486b0819d34d
https://github.com/llvm/llvm-project/commit/6008f6735309d3efafa8680df04f486b0819d34d
Author: David Green <david.green at arm.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abds.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abdu.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-add.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-ashr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-assertzext.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-buildvector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-concat.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-const.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-ctls.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-cttz.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-extract-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-fshl-fshr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-rotl-rotr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-saddo.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sdiv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shl.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shuffle.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-smulh.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-srem.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-stepvector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sub.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sve-splat.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-trunk.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uaddo.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-udiv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-umulh.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-unmerge.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-zext.mir
Log Message:
-----------
[AArch64][GlobalISel] Update scalar types in knownbits tests. NFC (#208199)
Commit: 7205d7c676c8f90a0cf89484c1a9687fa601b867
https://github.com/llvm/llvm-project/commit/7205d7c676c8f90a0cf89484c1a9687fa601b867
Author: Kristina Bessonova <ch.bessonova at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/ABIVersions.def
M clang/lib/AST/ItaniumMangle.cpp
M clang/test/CodeGenCXX/dtor-local-lambda-mangle.cpp
M clang/test/CodeGenCXX/mangle-lambdas-gh88906.cpp
A clang/test/CodeGenCXX/mangle-lambdas-in-dmi-local-class.cpp
Log Message:
-----------
[clang][ItaniumMangle] Fix mangling of lambdas in default member initializers of local classes (#206740)
Lambdas appearing in default member initializers of members of local
classes were previously mangled as if they belonged only to the class
scope, ignoring the enclosing function-local context.
This caused different (but same-named) local classes to produce
identical closure type mangling and corresponding RTTI/IR collisions.
Consider the following example:
```
void foo() {
{
struct T {
std::function<void()> a = [](){ std::cout << "a"; };
} t;
t.a();
}
{
struct T {
std::function<void()> a = [](){ std::cout << "b"; };
} t;
t.a();
}
}
```
The expected output is `ab` (and GCC-compiled code behaves accordingly),
while clang previously printed `bb` because the first `T::a` definition
is overridden by the second one due to the missing `<local-name>`
encoding and discriminator required to distinguish the two local `T`
definitions.
Commit: 852286d8169ce8522cccddaaf5356c62a1b7a8a2
https://github.com/llvm/llvm-project/commit/852286d8169ce8522cccddaaf5356c62a1b7a8a2
Author: Chirag Patel <chirag198838 at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
Log Message:
-----------
Fix unused variable build failure in Release build (#208195)
Fixes build failure introduced by commit [736771b]
(https://github.com/llvm/llvm-project/commit/736771b6a017b5a18c03819a3348ff793c473261)
into llvm:main
Ref : https://github.com/llvm/llvm-project/pull/207148
Failure : https://lab.llvm.org/buildbot/#/builders/228/builds/4056
Commit: ac1af12027ee0e2787400a896f67dc3f154b3d16
https://github.com/llvm/llvm-project/commit/ac1af12027ee0e2787400a896f67dc3f154b3d16
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/test/CodeGen/X86/apx/ccmp.ll
Log Message:
-----------
[X86][CCMP] Lower select(and/or(setcc,...), T, F) as a CCMP chain (#207929)
Fixes: #207886
Assisted-by: Claude Sonnet 4.6
Commit: adfb3be9d098e4c12895957f9ac3fc9d892b45a9
https://github.com/llvm/llvm-project/commit/adfb3be9d098e4c12895957f9ac3fc9d892b45a9
Author: Rito Takeuchi <licht-t at outlook.jp>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/mulhu-v4i64-umul-lohi-guard.ll
M llvm/test/CodeGen/X86/srem-vector-lkk.ll
M llvm/test/CodeGen/X86/urem-vector-lkk.ll
M llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
M llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
Log Message:
-----------
[X86] Add vXi64 MULHU/MULHS lowering, keeping full-width products scalar (#206983)
Based on the discussion in the PR #169819.
This lands the unsigned (`MULHU`) and signed (`MULHS`)
`vXi64` high-multiply lowering, plus a guard so full 128-bit products
stay scalar.
### What this does
1. **Lower `ISD::MULHU` for `v4i64`/`v8i64`** via `forceExpandMultiply`
(a `vpmuludq` schoolbook), as in #169819.
2. **Lower `ISD::MULHS` for `v4i64`/`v8i64`, gated on AVX512DQ.** The
signed low multiply is `vpmullq`, so `MULHS` is only marked `Custom`
when DQ (and VL for `v4i64`) is available.
3. **Guard the full-width-product case.** When the *low* half of the
product is also used (a `wyhash`-style `lo ^ hi`), vectorizing just the
high half is redundant with the low half's wide multiply. So, this guard
let a single scalar multiply per lane yield both halves, likewise the
unpatched target already did.
This is done by marking `UMUL_LOHI`/`SMUL_LOHI` `v4i64`/`v8i64` `Custom`
(unrolled), which lets the existing DAGCombiner check decline to narrow
`trunc(srl(mul(ext,ext)))` to `MULHU`/`MULHS` when the wide multiply's
low half is used.
### Performance
Same-IR A/B (identical IR, stock vs patched `llc`), EC2 metal,
per-target `-march`/`-mtune`, turbo off, one pinned core. ns/elem,
`stock → patched (ratio)`. Full matrix:
https://github.com/llvm/llvm-project/pull/206983#issuecomment-4871421534.
| kernel (AVX-512 256b) | Cascade | Ice Lake | SPR | Zen 4 |
|---|---|---|---|---|
| `udiv` (MULHU) | 1.71x | 1.71x | 1.78x | 1.88x |
| `div` (MULHS) | 1.18x | 1.25x | 1.31x | 2.04x |
| full-128 `lo ^ hi` (guarded) | 1.00x | 1.00x | 1.00x | 1.00x |
### Testing
- New `test/CodeGen/X86/mulhu-v4i64-umul-lohi-guard.ll`:
`umul_lohi_both_halves` (both halves used → scalarizes) and
`mulhu_high_only` (high only → vectorizes), on AVX2 and AVX-512.
- Existing `vector-idiv-{udiv,sdiv}-{256,512}.ll`, `urem-vector-lkk.ll`,
`srem-vector-lkk.ll` show the `MULHU`/`MULHS` vectorization (the signed
ones only on AVX512DQ RUN lines).
- No regressions across `test/CodeGen/X86`.
### AI Usage Disclosure
This PR was prepared with the assistance of Claude Code.
Fixes #37771
Commit: b5fa9eee6798b678fc7cb5f2b42a977932b708f9
https://github.com/llvm/llvm-project/commit/b5fa9eee6798b678fc7cb5f2b42a977932b708f9
Author: inquisitivecrystal <thoughtsoflifeandlight17 at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M libcxx/docs/Status/Cxx26Issues.csv
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/test/std/utilities/memory/specialized.algorithms/uninitialized.move/uninitialized_move.pass.cpp
M libcxx/test/std/utilities/memory/specialized.algorithms/uninitialized.move/uninitialized_move_n.pass.cpp
Log Message:
-----------
[libc++] Implement LWG3918: copy elision in `std::uninitialized_move/_n` (#207692)
This implements [LWG3918](https://wg21.link/LWG3918), which guarantees
copy elision for rvalues in `std::uninitialized_move/_n`. It also
implements [LWG4452](https://wg21.link/LWG4452), a minor correction that
makes the helper added by LWG3918 constexpr.
This additionally fixes a bug in `std::uninitialized_move/_n` where they
could create and then access dangling references. The previous
implementation used the following lambda as an implementation detail:
```c++
[](auto&& __iter) -> decltype(auto) { return std::move(*__iter); }
```
When `__iter` is a prvalue, this creates a temporary object within the
lambda's body and `std::move` then returns a reference to that object.
The reference dangles as soon as control leaves the lambda. This
behavior was not permitted by the standard even before LWG3918.
The new implementation fixes the bug by using a helper,
`std::__deref_move(__iter)`, which returns `*__iter` directly when
`*__iter` is already an rvalue.
Resolves #118339.
Resolves #171416.
Commit: fd86339aa29c096855b9cfba4a44c539a013ba15
https://github.com/llvm/llvm-project/commit/fd86339aa29c096855b9cfba4a44c539a013ba15
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
Log Message:
-----------
[LinkerWrapper] Fix AMDGPU Target-IDs linking in improper order (#207853)
Summary:
These target IDs are supposed to be ordered from most to least specific,
but we had no such ordering. The changes basically sort the input from
least to most specific using the target-id presence, then ensures that
their entries are listed first.
Fixes: https://github.com/llvm/llvm-project/issues/207835
Commit: 3ec5229fb7e0631119059fd1b50bef3c3d9bb24d
https://github.com/llvm/llvm-project/commit/3ec5229fb7e0631119059fd1b50bef3c3d9bb24d
Author: Mark Zhuang <mark.zhuang at spacemit.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M lld/test/ELF/compressed-debug-level.test
Log Message:
-----------
[lld][ELF][test] Accept zlib-ng compressed size (#206880)
zlib-ng 2.3.2 deflates slightly differently from zlib; the level-1
default is 0x20, just outside the LEVEL1 pattern. Widen it to accept
0x20.
Assisted-by: claude-opus
Commit: 646dcad77c7aec076dbc1c6d99d4b4fb1d63df3b
https://github.com/llvm/llvm-project/commit/646dcad77c7aec076dbc1c6d99d4b4fb1d63df3b
Author: Ivan R. Ivanov <iivanov at nvidia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M offload/test/lit.cfg
Log Message:
-----------
[offload] Add cuda to the PATH for nvptx tests (#208101)
To execute the JIT tests, ptxas needs to be in PATH. This also makes
sure we use ptxas from the same cuda path that we use when compiling.
Commit: f6976c8e7be28eae61f4c636370caef124a65f57
https://github.com/llvm/llvm-project/commit/f6976c8e7be28eae61f4c636370caef124a65f57
Author: Jack Styles <jack.styles at arm.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M flang/include/flang/Lower/Support/ReductionProcessor.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/Support/ReductionProcessor.cpp
A flang/test/Lower/OpenMP/reduction-array-element.f90
Log Message:
-----------
[Flang][OpenMP] Correct ArrayElements in Reduction Clause (#196094)
Currently, when an ArrayElement is used within a Reduction clause, it
will be lowered with the reduction referencing the box containing the
array, not just the element.
To address this, adjust Flang lowering to track expressions alongside
symbol to ensure that the Array Element context is not lost and
considered when lowering a reduction with Array Element. This ensures
that, when represented in HLFIR, it will be just the element's type,
rather than the full array.
Currently this excludes DO CONCURRENT as it excludes Array Elements, and
is limited to Array Elements but there are options to expand this into
Array Sections in the future.
Assisted-by: Codex
Commit: 961ab7a3696701f9cc0c82a4cde7fc9937141b01
https://github.com/llvm/llvm-project/commit/961ab7a3696701f9cc0c82a4cde7fc9937141b01
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX10.td
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
M llvm/test/CodeGen/X86/fminimum-fmaximum.ll
M llvm/test/CodeGen/X86/vec-strict-cmp-128.ll
Log Message:
-----------
[SDAG][X86] Uplift pseudo fmin/fmax from X86 (#188489)
X86 has pseudo fmin/fmax operations that implement `x olt y ? x : y` and
`x ogt y ? x : y` respectively. There are other targets that also
support these operations, including wasm and s390x.
On wasm (where I've adopted the "pseudo" terminology from), we currently
create these ops, but incorrectly (wrt signed zero handling). On s390x
we don't, but should to avoid regressions from fixing incorrect
minnum/maxnum formation.
I figured it would make sense to uplift the existing support form X86,
so other targets can benefit from it by just marking the operations
legal.
Commit: 6a151b618696a484adb9c848debb9ccc742a0867
https://github.com/llvm/llvm-project/commit/6a151b618696a484adb9c848debb9ccc742a0867
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M orc-rt/include/orc-rt-c/Compiler.h
Log Message:
-----------
[orc-rt] Add an ORC_RT_C_FORMAT_PRINTF macro for format-string checking (#208209)
Add a macro to annotate a function that takes a printf-style format
string, so that supporting compilers can check the format string against
the function's arguments at compile time.
This will be used by the upcoming logging API to type-check log format
strings, including at call sites that are compiled out.
Commit: 5fd64bb8f4878dcc002a5ba1bde3c23f0f2714ac
https://github.com/llvm/llvm-project/commit/5fd64bb8f4878dcc002a5ba1bde3c23f0f2714ac
Author: Vladimir Suvorov <svfly at yandex.ru>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.h
M mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/verifier.mlir
Log Message:
-----------
[mlir][tosa] Fix regression in mlir StableHLO tests due to PR #203583 (#207995)
StableHLO tests have regression due to use of additional op parameter in
verifyBlockScaledTensorType
This adjusts https://github.com/llvm/llvm-project/pull/203583 and fixes
many of stablehlo/tests
Signed-off-by: Vladimir Suvorov <suvorovv at google.com>
Commit: 188702eeb742a66b8cf32722ca4d8a8d64e77f83
https://github.com/llvm/llvm-project/commit/188702eeb742a66b8cf32722ca4d8a8d64e77f83
Author: Aayush Shrivastava <iamaayushrivastava at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
A llvm/test/CodeGen/AArch64/smax-allones.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/WebAssembly/fpclamptosat.ll
M llvm/test/CodeGen/X86/combine-smax.ll
M llvm/test/CodeGen/X86/combine-smin.ll
M llvm/test/CodeGen/X86/known-never-zero.ll
M llvm/test/CodeGen/X86/probe-stack-eflags.ll
Log Message:
-----------
[DAGCombiner] Fold smax(X, -1)/smin(X, 0) to bitwise shift forms (#206242)
Fixes #206153
`smax(X, -1) = or(X, ashr(X, BW-1))`
`smin(X, 0) = and(X, ashr(X, BW-1))`
`ashr(X, BW-1)` sign-extends the sign bit to all bits 0 for X≥0, -1 for
X<0. OR-ing with X yields X or -1 = smax(X,-1), AND-ing yields 0 or X =
smin(X,0). Both replace a `compare+cmov` with two cheap bitwise
instructions.
The fold is unconditional (not gated on code size), firing whenever the
target has no native `SMAX/SMIN` instruction for the type
(`isOperationExpand`), the type is legal (`isTypeLegal`), and the input
is not a min/max chain (preserving RISCV-P `sati` saturation patterns).
Commit: bb55d6c3c26640f2a0fdb33005e6221ddcdfd18c
https://github.com/llvm/llvm-project/commit/bb55d6c3c26640f2a0fdb33005e6221ddcdfd18c
Author: Jean-Didier PAILLEUX <jean-didier.pailleux at sipearl.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M flang/lib/Lower/MultiImageFortran.cpp
Log Message:
-----------
[flang][MIF] Fix ucobounds given in mif.alloc_coarray #207858 (#207935)
This PR provide a manior fix to issue #207858 when the `ucobound` array
is passed to mif.alloc_coarray. This array was built from the values in
`lcobound`.
Commit: f05387745e53a1fe298b4b45d66f40517ec7ace6
https://github.com/llvm/llvm-project/commit/f05387745e53a1fe298b4b45d66f40517ec7ace6
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M orc-rt/CMakeLists.txt
M orc-rt/include/CMakeLists.txt
A orc-rt/include/orc-rt-c/Logging.h
M orc-rt/include/orc-rt-c/config.h.in
M orc-rt/unittests/CMakeLists.txt
A orc-rt/unittests/LoggingTest.cpp
Log Message:
-----------
[orc-rt] Add a configurable logging API with a no-op backend (#208214)
Adds ORC_RT_LOG(Level, Category, Fmt, ...), a compile-time-configurable
logging facility for the ORC runtime, along with the default "none"
backend.
The backend is chosen at build time via the ORC_RT_LOG_BACKEND CMake
option (none, printf, os_log), and the lowest level to be compiled in
via ORC_RT_LOG_LEVEL.
The "none" backend implemented here compiles every log site out to
nothing (but still type-checks the format string and arguments in an
unevaluated context so disabled sites cannot bit-rot). Levels are Error,
Warning, Info, and Debug; categories are a typo-safe enum.
The printf and os_log backends are stubbed with #error and will follow.
Commit: 44858419d766322d9c51d85f4ac83501a5181597
https://github.com/llvm/llvm-project/commit/44858419d766322d9c51d85f4ac83501a5181597
Author: Jinsong Ji <jinsong.ji at intel.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/include/clang/AST/StmtVisitor.h
M llvm/include/llvm/Support/Compiler.h
Log Message:
-----------
Revert "[clang][AST] Inline StmtVisitor fallback methods" for STMT macro in debug builds (#208106)
This partially reverts commit 8b50847a31f927d258cf22953035db206d42fc5d.
The LLVM_ATTRIBUTE_ALWAYS_INLINE on STMT macro fallback methods caused
stack overflow in debug builds when processing deeply nested
expressions.
The test many-logical-ops.c with 2000+ logical AND operators would crash
in SequenceChecker due to excessive stack consumption.
Introduce LLVM_ATTRIBUTE_ALWAYS_INLINE_UNLESS_DEBUG which expands to
LLVM_ATTRIBUTE_ALWAYS_INLINE in release builds (preserving the binary
size optimization) but to plain `inline` in debug builds (avoiding stack
overflow).
Apply this to the STMT macro while keeping LLVM_ATTRIBUTE_ALWAYS_INLINE
on BINOP_FALLBACK, CAO_FALLBACK, and UNARYOP_FALLBACK.
Fixes regressions in debug builds only:
Clang :: C/C99/n590.c
Clang :: Index/index-many-logical-ops.c
Clang :: Sema/deep_recursion.c
Clang :: Sema/many-logical-ops.c
Co-Authored-By: Claude Sonnet 4.5 <noreply at anthropic.com>
---------
Co-authored-by: Claude Sonnet 4.5 <noreply at anthropic.com>
Commit: 2681879121986aea419cc19421dc04f3f1bc3eb1
https://github.com/llvm/llvm-project/commit/2681879121986aea419cc19421dc04f3f1bc3eb1
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/HIPAMD.h
M clang/test/Driver/hip-phases.hip
M clang/test/Driver/hip-toolchain-device-only.hip
Log Message:
-----------
[HIP] Use complete toolchain in --offload-device-only (#205243)
Summary:
Since https://github.com/llvm/llvm-project/pull/201457 these targets
defaulted to LTO. However, this caused the default for
`--offload-device-only` to now be LLVM-IR. This is a regression from
prior behavior, so we special case it out. Honestly this would probably
be correct if the behavior started like this, but we shouldn't break
existing code.
Commit: c4b3d1d51da2570de41fbfab9784ca31558641a8
https://github.com/llvm/llvm-project/commit/c4b3d1d51da2570de41fbfab9784ca31558641a8
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.h
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.h
M llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.h
M llvm/lib/Target/SystemZ/SystemZInstrInfo.td
M llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
M llvm/test/CodeGen/SystemZ/call-zos-01.ll
M llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
M llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
M llvm/test/CodeGen/SystemZ/zos-ada.ll
M llvm/test/CodeGen/SystemZ/zos-frameaddr.ll
M llvm/test/CodeGen/SystemZ/zos-ppa1.ll
M llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll
M llvm/test/CodeGen/SystemZ/zos-stack-protector.ll
Log Message:
-----------
[SystemZ][z/OS] Emit prolog length (#208069)
The PPA1 contains fields recording the length of the prolog and the
offset to the instruction updating the stack pointer register. The
implementation consists of the following parts:
- the end of the prolog is marked with a FENCE instruction which
prevents scheduling from moving instructions across the barrier.
- when emitting the PPA1, the FENCE instruction along with other stack
update instructions are used to calculate the length and the offset.
Co-authored-by: Tony Tao <tonytao at ca.ibm.com>
Commit: 4c6f664cc78a2c2ad2fd511a5adf9fc988f2d933
https://github.com/llvm/llvm-project/commit/4c6f664cc78a2c2ad2fd511a5adf9fc988f2d933
Author: Wooseok Lee <wolee at amd.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
M llvm/test/CodeGen/AMDGPU/implicit-arg-block-count.ll
Log Message:
-----------
[AMDGPU] Guard block-count upgrade against volatile/atomic grid-size … (#208068)
…loads
AMDGPULowerKernelAttributes upgrades the pre-COV5 pattern
udiv(grid_size_x, group_size_x)
to a direct load of hidden_block_count_x from the implicit args. The
m_Load() pattern matcher does not check whether the matched load is
volatile or atomic, so a volatile or atomic grid_size load would have
been silently deleted and replaced -- dropping its observable side
effects in violation of the LangRef.
Fix: after the pattern match succeeds, cast the matched value to
LoadInst and bail out if !isSimple() (i.e., volatile or atomic).
Add a test case num_blocks_x_volatile_grid_size in
implicit-arg-block-count.ll to verify the volatile load and udiv are
preserved unchanged.
Commit: 1f0dca704ab4b59de9377e21813c18f1bb5899d8
https://github.com/llvm/llvm-project/commit/1f0dca704ab4b59de9377e21813c18f1bb5899d8
Author: Wooseok Lee <wolee at amd.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-fast.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr-fast.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll
Log Message:
-----------
[AMDGPU] Gate fold_pow(x, ±0.5)->sqrt/rsqrt on nsz+ninf fast-math flags (#205592)
AMDGPULibCalls::fold_pow rewrote pow(x, 0.5)->sqrt(x) and pow(x,
-0.5)->rsqrt(x) unconditionally, firing before the
isUnsafeFiniteOnlyMath guard. This is incorrect for two IEEE corner
cases:
pow(-Inf, 0.5) == +Inf but sqrt(-Inf) == NaN
pow(-0.0, 0.5) == +0.0 but sqrt(-0.0) == -0.0
Guard the fold on hasNoSignedZeros() && (IsPowr || hasNoInfs()), where
IsPowr is true for powr/powr_fast. The OpenCL spec requires x >= 0 for
powr, so -Inf is undefined behaviour and the ninf check can be skipped;
-0.0 is a valid input for powr since -0.0 >= 0 by IEEE comparison, so
nsz is still required for all variants. afn alone is not sufficient
since it only permits approximate results and says nothing about the
treatment of infinities or signed zeros.
Update the four autogenerated test files to reflect the new semantics:
- Add nsz (and ninf for pow) to existing afn-only ±0.5 call sites so
those tests continue to exercise the fold as intended. powr tests use
nsz only, documenting that ninf is not required.
- Add afn-only (no nsz/ninf) ±0.5 tests in pow-fast.ll and powr-fast.ll
to document that afn alone does not trigger the fold.
Commit: 56f655fafabc5ff98aee687c4e03f4c6b57c496e
https://github.com/llvm/llvm-project/commit/56f655fafabc5ff98aee687c4e03f4c6b57c496e
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
Log Message:
-----------
[NFC][SPIR-V] Dedupe getConstInt metadata helper into SPIRVUtils (#208194)
Commit: 8b4e74e02ededfdb64258a13f2d2a584b79eec2c
https://github.com/llvm/llvm-project/commit/8b4e74e02ededfdb64258a13f2d2a584b79eec2c
Author: Mark Zhuang <mark.zhuang at spacemit.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/test/MC/RISCV/corev/XCValu-invalid.s
M llvm/test/MC/RISCV/corev/XCVbitmanip-invalid.s
M llvm/test/MC/RISCV/corev/XCVmac-invalid.s
M llvm/test/MC/RISCV/corev/XCVmem-invalid.s
M llvm/test/MC/RISCV/corev/XCVsimd-invalid.s
M llvm/test/MC/RISCV/insn-invalid.s
M llvm/test/MC/RISCV/insn_c-invalid.s
M llvm/test/MC/RISCV/insn_xqci-invalid.s
M llvm/test/MC/RISCV/priv-invalid.s
M llvm/test/MC/RISCV/rv32c-invalid.s
M llvm/test/MC/RISCV/rv32i-invalid.s
M llvm/test/MC/RISCV/rv32zalrsc-invalid.s
M llvm/test/MC/RISCV/rv32zbb-invalid.s
M llvm/test/MC/RISCV/rv32zcmop-invalid.s
M llvm/test/MC/RISCV/rv64zalrsc-invalid.s
M llvm/test/MC/RISCV/rv64zbb-invalid.s
M llvm/test/MC/RISCV/rvc-hints-invalid.s
M llvm/test/MC/RISCV/rvv/zvvfmm-invalid.s
M llvm/test/MC/RISCV/rvv/zvvmm-invalid.s
M llvm/test/MC/RISCV/rvv/zvvmtls-invalid.s
M llvm/test/MC/RISCV/rvv/zvvmttls-invalid.s
M llvm/test/MC/RISCV/rvzicond-invalid.s
M llvm/test/MC/RISCV/rvzihintntl-invalid.s
M llvm/test/MC/RISCV/rvzihintntlc-invalid.s
M llvm/test/MC/RISCV/smrnmi-invalid.s
M llvm/test/MC/RISCV/tlsdesc.s
M llvm/test/MC/RISCV/xmips-invalid.s
M llvm/test/MC/RISCV/xqci-access-pseudos.s
M llvm/test/MC/RISCV/xqciint-invalid.s
M llvm/test/MC/RISCV/xqcisim-invalid.s
M llvm/test/MC/RISCV/xqcisync-invalid.s
M llvm/test/MC/RISCV/xtheadcmo-invalid.s
M llvm/test/MC/RISCV/xtheadcondmov-invalid.s
M llvm/test/MC/RISCV/xtheadsync-invalid.s
Log Message:
-----------
[RISCV] Report "unexpected extra operand" for surplus operands in AsmParser (#207142)
This improves upon the shared near-miss reporting infrastructure added
in #205721 by handling a case that was deferred during that PR's review.
Assisted-by: claude-opus
Commit: 29f8993fa216b7661795923e375f55ba5c814408
https://github.com/llvm/llvm-project/commit/29f8993fa216b7661795923e375f55ba5c814408
Author: Aditya Medhane <sherlockedaditya at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M flang-rt/lib/runtime/time-intrinsic.cpp
M flang-rt/unittests/Runtime/tools.h
Log Message:
-----------
[flang-rt] Fix -Wunused-template in time intrinsics and test helpers (NFC) (#207979)
`time-intrinsic.cpp` implements the timing intrinsics as SFINAE overload
sets (preferred/fallback per platform), so on any given platform some
overloads are intentionally never instantiated and trip
-Wunused-template. Mark all variants [[maybe_unused]].
`StoreElement` and `MakeArray` in `unittests/Runtime/tools.h` are static
function templates in a header, so any test TU that includes it without
using all of them trips the warning.
Part of #202945
Commit: b3e6e6dabdc02153552a64fc74ff5c7532447eed
https://github.com/llvm/llvm-project/commit/b3e6e6dabdc02153552a64fc74ff5c7532447eed
Author: Michael Jones <michaelrj at google.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M libcxx/include/__locale_dir/support/no_locale/characters.h
M libcxx/include/__locale_dir/support/no_locale/conversions.h
Log Message:
-----------
[libcxx][NFC] Move guards outside namespace (#208089)
Libc++ has a warning that triggers on empty namespaces. When
_LIBCPP_BUILDING_LIBRARY is not defined, the __locale namespace was
empty. This PR moves the #ifdef to surround the namespace and fix the
warning.
Commit: 51b007f070b2b0f46da1c4e968600fa90fd0ceee
https://github.com/llvm/llvm-project/commit/51b007f070b2b0f46da1c4e968600fa90fd0ceee
Author: David Zbarsky <dzbarsky at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/lib/Serialization/ASTReader.cpp
Log Message:
-----------
[NFC][clang][Serialization] Outline LangOptions mismatch diagnostics (#202843)
Outline language-option mismatch diagnostic construction into two
`noinline` helpers. Generated comparisons remain direct and ordered as
before, so successful imports add no indirect calls and the serialized
format is unchanged.
Linked `clang` and `clangd` shrink by 35,264 and 29,216 bytes
respectively; `ASTReader.cpp.o` shrinks by 62,712 bytes with 1,347 fewer
relocations, while linked fixups are unchanged.
PCH, PCM, and BMI outputs and mismatch diagnostics are byte-identical,
focused module/PCH tests pass, and batched PCH and module imports show
no significant performance change.
Work towards #202616
AI tool disclosure: Co-authored with OpenAI Codex.
Commit: 059554a0130cc85a0b754b95f73b6ff1b207a4b0
https://github.com/llvm/llvm-project/commit/059554a0130cc85a0b754b95f73b6ff1b207a4b0
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[VPlan] Introduce VPlan-based requiresScalarEpilogue helper. (NFC) (#207784)
Add requiresScalarEpilogue(Plan, VF) that directly checks if a scalar
epilogue is required for a VPlan. In that case, the middle block (i.e.
first predecessor of the scalar ph) unconditionally branches to the
scalar preheader.
For now added to LoopVectorizationPlanner, so we can assert that the
result of the VPlan check matches the legacy result, to catch any
potential divergences.
The helper should be moved to VPlan directly and the assertion dropped
when no divergences have been found for a while, to make it independent
of the cost mode.
PR: https://github.com/llvm/llvm-project/pull/207784
Commit: 7b2e9db8e19e8b9ab1949fa476335c4c87075c58
https://github.com/llvm/llvm-project/commit/7b2e9db8e19e8b9ab1949fa476335c4c87075c58
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
Log Message:
-----------
AMDGPU: Remove unnecessary lookup of function from machineinstr (#208222)
The function is already a shadowed member of the class.
Commit: ae281befbf52aca9522c50f1ab3ddebdf0ac2cb9
https://github.com/llvm/llvm-project/commit/ae281befbf52aca9522c50f1ab3ddebdf0ac2cb9
Author: Sean Perry <perry at ca.ibm.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/Support/AutoConvert.h
M llvm/lib/Support/AutoConvert.cpp
M llvm/lib/Support/Unix/Path.inc
M llvm/lib/Support/raw_ostream.cpp
M llvm/unittests/Support/raw_ostream_test.cpp
Log Message:
-----------
Use existing encoding when writing to an existing file (#198873)
Clang lit test `Sema/warn-lifetime-safety-suggestions.cpp` is failing
because the encoding for the new contents of the source file don't match
the file tag on the file.
This change ensures the contents of a file are written in the same code
page as the existing file.
- The copyFileTagAttributes() function will change the auto conversion
to the code page of the file tag when writing a new version of a file.
- When writing to an existing file (eg. appending), use the file tag as
the code page for auto conversion. Don't assume 1047.
Commit: cd9eeb176ebd9322a02aab2357ee5e9b4840b2c7
https://github.com/llvm/llvm-project/commit/cd9eeb176ebd9322a02aab2357ee5e9b4840b2c7
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/runtimes/CMakeLists.txt
Log Message:
-----------
[libsycl] Add tool dependencies in runtimes mode (#205384)
The libsycl runtime depends on multiple clang tools.
We should ensure that these tools are built.
---------
Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
Commit: 7a57458221c99e649ba002505b0b2e4d9c9b5912
https://github.com/llvm/llvm-project/commit/7a57458221c99e649ba002505b0b2e4d9c9b5912
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M .github/workflows/test-suite.yml
M .github/workflows/test-suite/x86_64.cmake
Log Message:
-----------
[GitHub] Change /test-suite x86_64 configuration to test x86-64-v3 (#208228)
It would be good to see codegen changes for AVX.
Commit: 974fc1319640cce76523bcee48d003421ec7c163
https://github.com/llvm/llvm-project/commit/974fc1319640cce76523bcee48d003421ec7c163
Author: David Zbarsky <dzbarsky at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/lib/Frontend/FrontendActions.cpp
M clang/test/Frontend/compiler-options-dump.cpp
Log Message:
-----------
[clang][Frontend] Table-drive compiler option dumping (#203161)
`Features.def` currently expands 228 feature formatting expressions and
49 extension formatting expressions in
`DumpCompilerOptionsAction::ExecuteAction`. This stores the names in
NUL-separated character blobs, evaluates the predicates into local
`bool` arrays, and formats both arrays with `writeCompilerOptionValues`.
In a Release arm64 build, standalone clang decreases by 49,256 bytes
unstripped and 49,520 bytes stripped, while the LLVM multicall binary
decreases by 49,264 bytes unstripped and 49,528 bytes stripped; linked
`__text` decreases by 52,696 bytes and linked fixups decrease by 7.
Work towards #202616
AI tool disclosure: Co-authored with OpenAI Codex.
Commit: b7091e67a1d027d8db62a2e84b070dd23f85bda4
https://github.com/llvm/llvm-project/commit/b7091e67a1d027d8db62a2e84b070dd23f85bda4
Author: Fateme Hosseini <Fhossein at qti.qualcomm.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonXQFloatGenerator.cpp
M llvm/test/CodeGen/Hexagon/autohvx/xqf-assertion1.ll
M llvm/test/CodeGen/Hexagon/autohvx/xqf-check-qf-instrs.ll
A llvm/test/CodeGen/Hexagon/autohvx/xqf-compliant-ieee-mul-qf16.ll
A llvm/test/CodeGen/Hexagon/autohvx/xqf-compliant-ieee-mul-qf32.ll
A llvm/test/CodeGen/Hexagon/autohvx/xqf-convert-elim.ll
A llvm/test/CodeGen/Hexagon/autohvx/xqf-lossy-mul-qf16.ll
A llvm/test/CodeGen/Hexagon/autohvx/xqf-lossy-mul-qf32.ll
A llvm/test/CodeGen/Hexagon/autohvx/xqf-v81/xqf-v81-compliant-ieee-mul-qf32.ll
A llvm/test/CodeGen/Hexagon/autohvx/xqf-v81/xqf-v81-lossy-mul-qf32.ll
A llvm/test/CodeGen/Hexagon/autohvx/xqf-v81/xqf-v81-vsub.ll
A llvm/test/CodeGen/Hexagon/autohvx/xqf-vsub.ll
Log Message:
-----------
[Hexagon] Add XQFloat extraneous conversion removal pass (#207236)
Introduce VectorConvertRemove to remove extraneous qf->sf/hf conversions
after XQFloat code generation. Off by default, enabled with
-enable-rem-conv.
Co-authored-by: Santanu Das <quic_santdas at qti.qualcomm.com>
Commit: 4f339eedfce6cc7bf8ea9f6737224629dd6e7d0b
https://github.com/llvm/llvm-project/commit/4f339eedfce6cc7bf8ea9f6737224629dd6e7d0b
Author: Qi Ye <qi.ye at intel.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bfloat16_arithmetic/bfloat16-ocl-ext.ll
Log Message:
-----------
[SPIR-V] Add SPV_INTEL_bfloat16_arithmetic for Opencl.std instructions with bfloat16 type (#205128)
For `OpExtInst`, add check for bfloat16 type when it's an OpenCL.std
extended instruction, and add requirements for
SPV_INTEL_bfloat16_arithmetic if so.
Add such check and extension requirement since OpenCL.std extended
instruction set can operate on IEEE-754 FP types only, as per the
revision from [OpenCL.std
spec](https://registry.khronos.org/SPIR-V/specs/unified1/OpenCL.ExtendedInstructionSet.100.html#_changes_from_version_1_0_revision_8)
---------
Co-authored-by: Viktoria Maximova <viktoria.maksimova at intel.com>
Commit: 81b2e47b0d29526a7bb8a7674af61acff019a5a4
https://github.com/llvm/llvm-project/commit/81b2e47b0d29526a7bb8a7674af61acff019a5a4
Author: Pradeep Kumar <pradeepku at nvidia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/test/CodeGen/NVPTX/tcgen05-ld.ll
M llvm/test/CodeGen/NVPTX/tcgen05-st.ll
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/test/Dialect/LLVMIR/nvvm_check_target_sm.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-ld.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-st.mlir
Log Message:
-----------
[SDAG][NVPTX] Enable custom legalization of v1 type for Intrinsic results and operands (#203237)
This commit enables custom legalization for v1 types for intrinsic results and operand by calling CustomLowerNode which gives the target a chance to custom handle the node before scalarizing
To demonstrate, I have used tcgen05.ld/st intrinsics which previously used a scalar i32 type while all wider variants used vector types
Assisted by: Claude Code
Commit: 3a85687f4bd34e10e43b65c6ce6b29b980705efc
https://github.com/llvm/llvm-project/commit/3a85687f4bd34e10e43b65c6ce6b29b980705efc
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/Support/thread.h
M llvm/lib/Support/Unix/Threading.inc
Log Message:
-----------
[Support] Teach llvm::thread about thread-id handling in LLVM-libc. (#207918)
This PR matches the libc++ update from
https://github.com/llvm/llvm-project/pull/198595 and applies similar
changes to `llvm::thread` class. Please see the discussion in that PR
(and linked references to other PRs) for more background / discussions.
`llvm::thread` has methods for extracting integer IDs from running
threads, and as such it needs to know what types are used to represent
those integer IDs - something that e.g. pthreads or C11 threads don't
specify. It assumes that `pthread_t` can be used both as a handle and as
a thread-id on most platforms, with the exception of zOS, where the
custom code is written. In LLVM-libc `pthread_t` is not an integral
type, but today it provides `pthread_id_np_t` type and
`pthread_getunique_np` / `pthread_getthreadid_np` methods as extensions
to extract the integer IDs. Use these methods when building against
LLVM-libc.
This is one of few remaining blockers for building LLVM+Clang on top of
LLVM-libc (https://github.com/llvm/llvm-project/issues/97191).
Commit: 00b2f81418233397e601afaeea6d62c47a6c368a
https://github.com/llvm/llvm-project/commit/00b2f81418233397e601afaeea6d62c47a6c368a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/cmake/modules/ClangConfig.cmake.in
A cmake/Modules/GetTripleCMakeSystemName.cmake
A cmake/Modules/NormalizeTriple.cmake
M llvm/cmake/modules/LLVMConfig.cmake.in
M llvm/cmake/modules/LLVMExternalProjectUtils.cmake
M llvm/runtimes/CMakeLists.txt
M runtimes/CMakeLists.txt
Log Message:
-----------
Reapply "runtimes: Pass CMAKE_SYSTEM_NAME based on target triple" (#205133) (#205522)
This reverts commit 08c728e8528c9584bc1fe0f46bbdd657e368be91.
Reapply after runtimes build fixes on platforms without shared
libraries.
Commit: 8a94ef9467a4be014ab088c01fbe3a15e8a43823
https://github.com/llvm/llvm-project/commit/8a94ef9467a4be014ab088c01fbe3a15e8a43823
Author: Aleksandr Popov <42888396+aleks-tmb at users.noreply.github.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Transforms/LoopVectorize/early-exit-umin-trip-count.ll
M llvm/unittests/Analysis/ScalarEvolutionTest.cpp
Log Message:
-----------
[SCEV] Prove umin(Ops) u< RHS by checking individual operands (#207729)
Teach IsKnownPredicateViaMinOrMax to handle ICMP_ULT/UGT for
SCEVUMinExpr. Since umin(Ops) u<= each Op by definition, proving Op u<
RHS for any single operand is sufficient to establish umin(Ops) u< RHS
by transitivity.
This unblocks loop vectorization for early-exit loops whose trip count
is a umin of a buffer length and an iteration bound.
Fixes https://github.com/llvm/llvm-project/issues/196935
Alive2 proof: https://alive2.llvm.org/ce/z/9DjA2f
Commit: 006429da6ab9527e34c63df3f84517d385c30ef2
https://github.com/llvm/llvm-project/commit/006429da6ab9527e34c63df3f84517d385c30ef2
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonPatterns.td
A llvm/test/CodeGen/Hexagon/fshl-fshr-i32-mask.ll
M llvm/test/CodeGen/Hexagon/funnel-shift.ll
M llvm/test/CodeGen/Hexagon/rotate.ll
Log Message:
-----------
[Hexagon] Fix 32-bit funnel shift miscompilation with register shift amounts (#205489)
The register-variable 32-bit funnel shifts and the i32 rotates that
lower through them, realize the shift as a 64-bit asl/lsr of the {hi,lo}
combine and take one word of the result. That identity only holds for a
shift amount in [0, 31], and llvm.fshl/fshr define the amount to be
taken modulo 32. The register-form variable shift does not reduce the
amount modulo the operand width, it treats the low 7 bits as a signed
amount in [-64, 63]. So the raw, unreduced amount must be masked with
#31 before the 64-bit shift.
Without the mask, counts >= 32 or "negative" counts are miscompiled: a
count of 63 shifts left by 63, 64 becomes -64 and shifts the value out
entirely, and -1 becomes an arithmetic right shift by 1. In-range counts
0..31 come out correct, which is why a test that only sweeps 0..31 does
not catch it. This is exactly the i32.rotl/i32.rotr miscompile that
caused the WAMR Wasm spec-test suites (which invoke rotates with counts
of 32, 33, and -1) to be skipped on Hexagon.
Fix by masking the amount with (A2_andir $Ru, 31), mirroring the masking
the 64-bit patterns already use. This completes the 32-bit case left
unaddressed by 4fffee037520 ("[Hexagon] Fix 64-bit funnel shift
miscompilation with register shift amounts", #183669), which fixed only
the FShl64r/FShr64r width.
Commit: 38aa43fd96dc15092246a94c8a45c1c0a78217cc
https://github.com/llvm/llvm-project/commit/38aa43fd96dc15092246a94c8a45c1c0a78217cc
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/lib/CodeGen/BackendUtil.cpp
Log Message:
-----------
[Clang] Disable verifier passes by default in NewPM CodeGen (#208178)
By default, we shouldn't add expensive verifier passes to the pipeline.
This causes a substantial perf regression compared to the legacy PM.
Commit: 1538aebce77546372d39ebe25bfe75cee6ed39f8
https://github.com/llvm/llvm-project/commit/1538aebce77546372d39ebe25bfe75cee6ed39f8
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToLaneDistribute.cpp
M mlir/test/Dialect/XeGPU/sg-to-lane-distribute-unit.mlir
Log Message:
-----------
[MLIR][XeGPU] Add non-splat constant distribution in SgToLane pass (#205575)
Commit: 7468b5634b038ba915fc326a8fb2f3fe6c3ed098
https://github.com/llvm/llvm-project/commit/7468b5634b038ba915fc326a8fb2f3fe6c3ed098
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
M mlir/lib/Dialect/OpenACC/Transforms/ACCComputeLowering.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
Log Message:
-----------
[mlir][acc] Add utilities for working with acc par dims (#208120)
Add shared helpers for reading, setting, and manipulating parallel
dimensions on operations, covering both discardable and inherent
attributes.
Commit: 89c6fa58bbcca9f64a48104eb0e6bf3a616558e8
https://github.com/llvm/llvm-project/commit/89c6fa58bbcca9f64a48104eb0e6bf3a616558e8
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
A llvm/test/tools/llubi/inttoptr_ptrtoint_constantexpr.ll
M llvm/tools/llubi/lib/Context.cpp
Log Message:
-----------
[llubi] Add support for constant inttoptr/ptrtoint expressions (#207028)
This patch adds support for constant inttoptr/ptrtoint expressions to
unblock the running of csmith-generated programs.
The test doesn't cover all the behaviours, as they have been tested by
previous tests.
This patch treats constant inttoptr/ptrtoint expressions as if they are
executed just before the user. However, since ptrtoint exposes the
pointer provenance and inttoptr relies on the current set of exposed
provenances, it is incorrect. Imagine that we have an inttoptr in a gep
instruction and a ptrtoint in an add instruction. They can be freely
DCEd/reordered. In addition, the behaviour also depends on the
initialization order of globals. That is terrible. Nikita's proposal
also mentioned this issue but left it as an open question:
https://hackmd.io/@nikic/SJBt4mFCll#Constant-expressions
>From my perspective, constant expressions are allowed to execute at any
point in the program (before their users). Moving ptrtoint forward or
inttoptr backward will not make the program more undefined. So we can
evaluate all constant expressions before the program entry (i.e., all
globals involved with ptrtoint will be exposed at the start). The only
remaining concern is the use of `ConstantExpr::getAsInstruction`,
because it will convert CEs back into instruction sequences :(
Commit: 7e2e37536167a96e61f077d993ddc7106e372596
https://github.com/llvm/llvm-project/commit/7e2e37536167a96e61f077d993ddc7106e372596
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/test/CodeGen/SPIRV/instructions/atomic-ptr.ll
A llvm/test/CodeGen/SPIRV/transcoding/atomic-load-store-exchange-unsupported.ll
R llvm/test/CodeGen/SPIRV/transcoding/atomic-load-store-unsupported.ll
Log Message:
-----------
[SPIRV] Support atomic exchange of pointers (#207830)
Similar to what we do for atomic loads and stores, support pointers by
converting the exchange value to an equally-sized int, the pointer to a
pointer to that equally-sized int, and convert the result back to the
original pointer type.
This was found enabling support for SPIR-V in libc.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: d55faf25b49dcf487f5a56d73490743c87cece5a
https://github.com/llvm/llvm-project/commit/d55faf25b49dcf487f5a56d73490743c87cece5a
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M libc/config/linux/riscv/entrypoints.txt
M libc/src/__support/File/linux/CMakeLists.txt
M libc/src/__support/File/linux/file.cpp
R libc/src/__support/OSUtil/fcntl.h
M libc/src/__support/OSUtil/linux/CMakeLists.txt
R libc/src/__support/OSUtil/linux/fcntl.cpp
M libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
M libc/src/__support/OSUtil/linux/syscall_wrappers/dup2.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/fcntl.h
M libc/src/fcntl/linux/CMakeLists.txt
M libc/src/fcntl/linux/fcntl.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc] Move fcntl implementation into the syscall_wrappers layer (#207878)
linux_syscalls::fcntl called SYS_fcntl unconditionally, breaking the
riscv32 full build where only SYS_fcntl64 exists. The syscall selection
and command translation already lived in internal::fcntl, so move that
implementation into syscall_wrappers/fcntl.h, delete the legacy
OSUtil/fcntl.h and OSUtil/linux/fcntl.cpp, and port the callers (fcntl
entrypoint, file.cpp, dup2.h) to linux_syscalls::fcntl.
Commit: ea6cf8c84aacc1d00b463f4558788ff3651fb57a
https://github.com/llvm/llvm-project/commit/ea6cf8c84aacc1d00b463f4558788ff3651fb57a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/X86/bmi2.ll
Log Message:
-----------
[SelectionDAG][X86] Replace OriginalDemandedBits with DemandedBits in SimplifyDemandedBits ISD::PDEP handling. (#208104)
DemandedBits is set to all 1s if the node has multiple uses.
Fixes regression from #204144. The changed test case reverts back to the
output before that change.
Commit: a52eb9869ffbd765f006d36bea64fb44a6fedf76
https://github.com/llvm/llvm-project/commit/a52eb9869ffbd765f006d36bea64fb44a6fedf76
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Fix inconsistent braces in performReverseEVLCombine. NFC (#208097)
Commit: 78f5fd35e0010b2a70411a9ca4bcb140bccce146
https://github.com/llvm/llvm-project/commit/78f5fd35e0010b2a70411a9ca4bcb140bccce146
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
Log Message:
-----------
[RISCV] Avoid let statements in RISCVSystemOperands. NFC (#207890)
Add an optional RV32Only operand to SysReg.
Add AltSysRegName and DeprecatedSysRegName wrappers.
Commit: 3e7a2ec74cd8f8e0e32037d0192a1378789e9af7
https://github.com/llvm/llvm-project/commit/3e7a2ec74cd8f8e0e32037d0192a1378789e9af7
Author: Michael G. Kazakov <mike.kazakov at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M libcxx/include/__algorithm/pstl.h
M libcxx/include/__pstl/backend_fwd.h
M libcxx/include/__pstl/backends/default.h
M libcxx/test/libcxx/algorithms/pstl.iterator-requirements.verify.cpp
M libcxx/test/libcxx/algorithms/pstl.nodiscard.verify.cpp
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find.first.of/find_first_of.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find.first.of/find_first_of_pred.pass.cpp
A libcxx/test/std/algorithms/alg.nonmodifying/alg.find.first.of/pstl.find_first_of.pass.cpp
A libcxx/test/std/algorithms/alg.nonmodifying/alg.find.first.of/pstl.find_first_of_pred.pass.cpp
M libcxx/test/std/algorithms/pstl.exception_handling.pass.cpp
Log Message:
-----------
[libc++][pstl] Default implementation of parallel std::find_first_of (#206328)
This PR adds a default "one-liner" implementation of parallel
`std::find_first_of` expressed as a call to `__find_if`.
The implementation is based on find_if and any_of.
Part of #99938
Commit: 62cf5de4fee60958508cca4db5df7769e0a9e57f
https://github.com/llvm/llvm-project/commit/62cf5de4fee60958508cca4db5df7769e0a9e57f
Author: David Zbarsky <dzbarsky at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/lib/Frontend/ASTConsumers.cpp
Log Message:
-----------
[clang] Use DynamicRecursiveASTVisitor for AST listing (#202661)
Replace `ASTDeclNodeLister`'s CRTP `RecursiveASTVisitor` with
`DynamicRecursiveASTVisitor` while keeping `ASTPrinter` and
`ASTDeclNodeLister` separate. Set `ShouldWalkTypesOfTypeLocs` to false
to
preserve the previous traversal.
In identical arm64 release builds, standalone clang shrinks by 251,840
bytes
(0.215%), stripped clang by 149,488 bytes, and `ASTConsumers.cpp.o` by
153,352
bytes; linked `__TEXT` falls by 147,456 bytes and linked fixups increase
by
1,040.
The `-ast-list` output is byte-identical on the existing clang-check
input and
`ASTConsumers.cpp` (150,918 lines); two reversed-order ten-run timing
passes
have overlapping wall-time distributions and a 0.4% combined mean user
CPU-time increase.
Work towards #202616
AI tool disclosure: Co-authored with OpenAI Codex.
Commit: e9548835fdd84200969b959472d55454d597dfd7
https://github.com/llvm/llvm-project/commit/e9548835fdd84200969b959472d55454d597dfd7
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M lldb/source/Commands/CommandObjectTarget.cpp
A lldb/test/API/functionalities/scripted_frame_provider/register_command_status/Makefile
A lldb/test/API/functionalities/scripted_frame_provider/register_command_status/TestFrameProviderRegisterCommandStatus.py
A lldb/test/API/functionalities/scripted_frame_provider/register_command_status/frame_provider.py
A lldb/test/API/functionalities/scripted_frame_provider/register_command_status/main.c
Log Message:
-----------
[lldb] Fix assert when `target frame-provider register` succeeds (#208232)
`CommandObjectTargetFrameProviderRegister::DoExecute` never called
`CommandReturnObject::SetStatus()` on its success path.
`CommandObject.cpp` has a `DoExecuteStatusCheck` RAII guard that resets
the result's status to `eReturnStatusInvalid` before `DoExecute` runs,
and asserts on exit that `DoExecute` changed it.
`AppendMessage()`/`AppendMessageWithFormatv()` don't touch status
(unlike AppendError()/SetError(), which call
`SetStatus(eReturnStatusFailed)`), so on the success path the status
stayed eReturnStatusInvalid, tripping the assert.
This went unnoticed because every existing `scripted_frame_provider`
test uses `SBTarget::RegisterScriptedFrameProvider` directly, bypassing
the `target frame-provider register` command entirely. Add a regression
test that exercises the command instead.
Assisted-by: Claude
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 7a4c856d55d7b0e7f546cf12fb9b065af46762e7
https://github.com/llvm/llvm-project/commit/7a4c856d55d7b0e7f546cf12fb9b065af46762e7
Author: Sampath Vutkoori <svutkoor at qti.qualcomm.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/cmake/modules/FindLibXml2.cmake
Log Message:
-----------
[cmake] FindLibXml2: fall back to xmlversion.h when pkg-config has no… (#207797)
… version
LLVM's cmake/modules/FindLibXml2.cmake uses PC_LIBXML_VERSION (from
pkg-config) as the VERSION_VAR in find_package_handle_standard_args.
When pkg-config has no libxml-2.0.pc file (e.g. when linking against a
static libxml2-pic.a that ships no .pc file), PC_LIBXML_VERSION is left
empty after pkg_check_modules fails and the >=2.8 version check reports
'Found unsuitable version ""', causing LLDB_ENABLE_LIBXML2 to be set to
FALSE.
Fix: before calling find_package_handle_standard_args, check whether
PC_LIBXML_VERSION is still empty and if so read LIBXML_DOTTED_VERSION
from the xmlversion.h header. This mirrors the version-detection logic
in the system CMake FindLibXml2 module and ensures LLDB is built with
libxml2 support on installations that use a static libxml2 without a .pc
file.
Commit: 466c1c2976f5206bb931617973ca030c51881b0a
https://github.com/llvm/llvm-project/commit/466c1c2976f5206bb931617973ca030c51881b0a
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/test/CodeGenCUDA/builtins-amdgcn.cu
M clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
Log Message:
-----------
[AMDGPU] Reimplement icmp and fcmp builtins using ballot (#208231)
Use `llvm.amdgcn.ballot` instead of the deprecated intrinsics
`llvm.amdgcn.icmp` and `llvm.amdgcn.fcmp`.
Commit: fb26065857a5a8877357ece1611f804ba7c114f4
https://github.com/llvm/llvm-project/commit/fb26065857a5a8877357ece1611f804ba7c114f4
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
Log Message:
-----------
[AggressiveInstCombine] Factor out the common part of tryToRecognizeTableBasedCttz and tryToRecognizeTableBasedLog2. NFC (#208123)
They both start with the same GEP+load matching.
Assisted-by: Claude
Commit: b49d10f67cd43f4a078bbcd3dc04259989a7924a
https://github.com/llvm/llvm-project/commit/b49d10f67cd43f4a078bbcd3dc04259989a7924a
Author: Vicky Nguyen <vicky.trucviennguyen at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/test/CodeGen/AArch64/neon/subtraction.c
Log Message:
-----------
[CIR][test] Use global instcombine RUN line in AArch64 neon subtracti… (#207894)
Related to https://github.com/llvm/llvm-project/issues/185382
Follow-up to https://github.com/llvm/llvm-project/pull/207115
Include `instcombine` into the global LLVM RUN line and remove the
separate `LLVM-IC` prefix that only covered the narrowing-subtraction
tests in `clang/test/CodeGen/AArch64/neon/subtraction.c`.
Update LLVM CHECK to match the `instcombine` output: bitcast checks are
dropped, the inferred `nsw` flags are added on the widening subs, and
unused shuffle operands are canonicalized to `poison`.
Commit: c9e2c308faa924a043175e2afa1e2efcb8b59a8a
https://github.com/llvm/llvm-project/commit/c9e2c308faa924a043175e2afa1e2efcb8b59a8a
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon/fullfp16.c
M clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
Log Message:
-----------
[CIR][AArc64] Add lowering for fp16 intrinsics (step + rounding) (#207511)
This PR adds lowering for the following intrinsic groups:
* https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#markdown-toc-reciprocal-step
It also adds FP16 tests for these intrinsics (implemented in #195021
without tests):
* https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#markdown-toc-rounding-1
It also moves the corresponding tests from:
* clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
to:
* clang/test/CodeGen/AArch64/neon/fullfp16.c
The lowering follows the existing implementation in
CodeGen/TargetBuiltins/ARM.cpp.
Commit: b634fff1e30c0676f57b5b44a544d638561c9ad9
https://github.com/llvm/llvm-project/commit/b634fff1e30c0676f57b5b44a544d638561c9ad9
Author: Chinmay Deshpande <chdeshpa at amd.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCombine.td
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
Log Message:
-----------
[AMDGPU] SDAG and GISel support for folding fabs into fp_round source modifiers (#204861)
Commit: 9df4aed204020bc79be55afa7b177822759856fb
https://github.com/llvm/llvm-project/commit/9df4aed204020bc79be55afa7b177822759856fb
Author: jeanPerier <jperier at nvidia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/StackArrays.cpp
M flang/test/Transforms/stack-arrays.fir
Log Message:
-----------
[flang] add some missing stackrestore with -fstack-arrays (#208161)
In the StackArray pass that moves array temporaries from the heap to the
stack under -fstack-arrays, when visiting FreeMemOp to insert
stackrestore, the code was not unwrapping converts as done in other
parts of the code leading to the allocation conversion and stacksave
insertion to happen without the emission of the stackrestore.
Reuse the same utility as in the rest of the pass to get consistent
behavior and fix the memory leak.
Commit: 33ef532c79b321cf22232ba0054b36d259c62079
https://github.com/llvm/llvm-project/commit/33ef532c79b321cf22232ba0054b36d259c62079
Author: pstarkcdpr <paul.stark at cdprojektred.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/test/Dialect/Linalg/vectorization/extract.mlir
Log Message:
-----------
[mlir][linalg] Fix mask rank for masked contiguous `tensor.extract` (#206207)
### Summary
Note: This fix was made mostly by Claude based on a failure case in
IREE. It addresses issue
https://github.com/llvm/llvm-project/issues/206209
When `vectorizeTensorExtract` lowers a `tensor.extract` recognized as a
*contiguous load*, it builds a `vector.transfer_read` whose permutation
map broadcasts the leading iteration dims and only reads the trailing
`min(dstRank, srcRank)` dims of the source. Until now this read was
returned unmasked and masked later by the generic path, which applies a
**full iteration-space identity mask**. When the source rank is smaller
than the loop nest, that mask is over-ranked relative to the
(rank-reduced) read — e.g. a `vector<1x4xi1>` mask on a read whose
inferred mask type is `vector<4xi1>` — and the op fails verification:
```
'vector.mask' op expects a 'vector<4xi1>' mask for the maskable operation
```
(or, after the masked read is rank-reduced by canonicalization in a full
pipeline, `'vector.transfer_read' op inferred mask type ... don't
match`).
### Root cause
The three `tensor.extract` lowering paths in `vectorizeTensorExtract`
handle masking inconsistently:
- **gather** masks itself — correct, its result is full-rank;
- **scalar broadcast** masks itself with a rank-1 mask, explicitly
noting that the generic identity-map masking "wouldn't be valid here";
- **contiguous load** does neither and relies on the generic path, which
masks over all loop dims. That is only correct when the read is
full-rank (`srcRank >= numLoops`); when `srcRank < numLoops` the read
broadcasts its leading dims and needs a rank-reduced mask.
Existing tests only covered the full-rank case (e.g. a
`tensor<80x16xf32>` source in a 2-D nest), so the rank-reducing case was
never exercised.
### Fix
Mask the contiguous read in place, mirroring the scalar-broadcast path,
using a masking map that projects the iteration space onto exactly the
trailing `min(dstRank, srcRank)` dims that are read:
```cpp
int64_t numReadDims = std::min(dstRank, srcRank);
auto maskingMap = AffineMap::getMinorIdentityMap(
linalgOp.getNumLoops(), numReadDims, rewriter.getContext());
Operation *maskedReadOp =
state.maskOperation(rewriter, transferReadOp, linalgOp, maskingMap);
```
This is **behavior-preserving for the existing full-rank case**: when
`min(dstRank, srcRank) == numLoops`, `getMinorIdentityMap` collapses to
the full identity map, producing the same mask (same `activeMaskCache`
key) and identical
IR. Only the previously-broken rank-reducing case changes.
### Testing
- New regression test `@masked_contiguous_extract_rank_reducing_mask` in
`mlir/test/Dialect/Linalg/vectorization/extract.mlir` (1-D source inside
a 2-D loop nest). It fails verification before this change and checks
the rank-reduced mask after it.
- `mlir/test/Dialect/Linalg` (164 tests) and `mlir/test/Dialect/Vector`
+ `mlir/test/Dialect/Linalg/vectorization` (113 tests) all pass.
### Notes for reviewers
- The change is localized to the contiguous-load branch of
`vectorizeTensorExtract`; the gather and scalar-broadcast branches are
untouched.
- No new mask is created in the full-rank case — the existing cached
iteration-space mask is reused, so there is no codegen/IR churn for
current callers.
---------
Signed-off-by: Paul Stark <paul.stark at cdprojektred.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: 02a7cd5177af78e5c8342bec3f30125113071556
https://github.com/llvm/llvm-project/commit/02a7cd5177af78e5c8342bec3f30125113071556
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/BPF/BPFMIPeephole.cpp
Log Message:
-----------
BPF: Remove unnecessary isReg check on phi operand (#208243)
These must be a register. This pass has quite a lot of
defensive code against invalid MIR that should be deleted.
Commit: e2d6498e36235ecd9955d8d375a0c1a253c2e11a
https://github.com/llvm/llvm-project/commit/e2d6498e36235ecd9955d8d375a0c1a253c2e11a
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Transforms/CUDA/CUFFunctionRewrite.cpp
M flang/test/Fir/CUDA/cuda-function-rewrite.mlir
Log Message:
-----------
[flang][cuda] Defer on_device() folding in host copies of OpenACC routines (#208125)
Add a `defer-acc-routines` option to `cuf-function-rewrite`. When set,
`on_device()` is not folded in the host copy of an OpenACC routine (has
`acc.routine_info`, not in a `gpu.module`), because that body is later
cloned into the device routine and would otherwise bake in the host
value (`.false.`). A later run folds each copy in its own context. Calls
already in a `gpu.module` are still folded.
Commit: 0a015cc516abb7f54bcdd94763f44219b6298bd9
https://github.com/llvm/llvm-project/commit/0a015cc516abb7f54bcdd94763f44219b6298bd9
Author: Guo Chen <guochen2 at amd.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
M llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/ctls.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/srl-bitcast-bv.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
Log Message:
-----------
[AMDGPU] Replace zext pattern from reg_sequence to cvt_u32_u16 (#208045)
Isel pattern putting imm inside reg_sequence create side effects when
register coalescer join these `copy` from imm
```
%1 = v_mov_b16_t16_e64 ...
%2.hi16 = copy %1
%2.lo16 = ....
...
%3.hi16 = copy %1
%3.lo16 = ....
....
%4.hi16 = copy %1
%4.lo16 = ....
```
to
```
%1 = v_mov_b16_t16_e64 ...
%2.hi16 = copy %1
%2.lo16 = ....
...
%2.lo16 = ... (reuse %2 and repeat)
....
```
When the number of copy increase this inserts a large number of WAR
hazzards on the reused virutal reg, and the machine scheduler bail out
getting higher reg pressure after sorting.
Beside this, replacing with cvt_u32_u16 provides better code quality
Commit: a47be1995a65a411527062e7ca7e92fff8d6ad1b
https://github.com/llvm/llvm-project/commit/a47be1995a65a411527062e7ca7e92fff8d6ad1b
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/simplify-reverse-reverse.ll
Log Message:
-----------
[VPlan] Add more tests for reverse simplification. NFC (#208255)
Commit: bdaeb7c290c482111c12da01b86f920e5151286a
https://github.com/llvm/llvm-project/commit/bdaeb7c290c482111c12da01b86f920e5151286a
Author: Wael Yehia <wmyehia2001 at yahoo.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/test/Sema/attr-target.c
Log Message:
-----------
[NFC] Add precommit test for PR 208059 (#208259)
Co-authored-by: Wael Yehia <wyehia at ca.ibm.com>
Commit: 1529d35adbd6f13aa234a5f4cfd9ac0e28bdd338
https://github.com/llvm/llvm-project/commit/1529d35adbd6f13aa234a5f4cfd9ac0e28bdd338
Author: Aditya Medhane <sherlockedaditya at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/test/Misc/warning-wall.c
M clang/test/SemaCXX/warn-func-not-needed.cpp
M clang/test/SemaCXX/warn-variable-not-needed.cpp
Log Message:
-----------
Reland "[Clang] Enable -Wunused-template under -Wall" (#208001)
Reland of #206123, which was reverted in #207848.
What has changed since:
- flang-rt occurrences are fixed in #207979
- openmp had one more occurrence which is fixed in #207983
- The remaining -Wunused-template hits anywhere in CI logs are the tsan
Go runtime warnings, which are warnings only (buildgo.sh does not use
-Werror on Linux)
Marked as draft until #207979 and #207983 land.
Closes #202945
Commit: 16b8129cd76a0954ac2ed1d0343f0fec40c2a691
https://github.com/llvm/llvm-project/commit/16b8129cd76a0954ac2ed1d0343f0fec40c2a691
Author: Giorgi Gvalia <49309634+gvalson at users.noreply.github.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/include/RecordReplay.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/common/src/RecordReplay.cpp
A offload/test/tools/omp-kernel-replay/record-replay-ir-bitcode.cpp
M offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp
Log Message:
-----------
[offload] Add the ability to record and replay IR bitcode modules (#207278)
This PR allows the user to use JIT with kernel record & replay by
expanding the latter to also work with IR bitcode images.
- Add a new field to `DeviceImageTy` for storing the IR image.
- Expand `RecordReplayTy::FileTy` to also include IR bitcode and
associate it with the file extension `.bc`
- Add the `--load-bitcode` command line option to
`llvm-omp-kernel-replay` tool.
---------
Co-authored-by: Giorgi Gvalia <gvalia1 at llnl.gov>
Commit: cf61b62424f6c2b679106b3687f08af5b18a99f7
https://github.com/llvm/llvm-project/commit/cf61b62424f6c2b679106b3687f08af5b18a99f7
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/Analysis/BranchProbabilityInfo.h
M llvm/include/llvm/Support/BranchProbability.h
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
M llvm/lib/Support/BranchProbability.cpp
Log Message:
-----------
[BranchProbabilityInfo][NFC] Remove some global ctors (#208252)
Make BranchProbability constexpr and replace global std::map with
switches.
Commit: b7edea5afa0fef26054a491413a62eb3d35e7d2b
https://github.com/llvm/llvm-project/commit/b7edea5afa0fef26054a491413a62eb3d35e7d2b
Author: Carlos Seo <carlos.seo at linaro.org>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
A flang/test/Lower/OpenMP/declare-reduction-operator-host-assoc.f90
Log Message:
-----------
[flang][OpenMP] Fix host-associated user-defined operator reduction (#207413)
A DECLARE REDUCTION for a user-defined operator (e.g.
reduction(.myadd.:x)) was rejected with "Invalid reduction operator in
REDUCTION clause" when the operator was host-associated.
CheckReductionOperator looked up the mangled reduction name in the scope
that owns the operator symbol (the scope where the operator interface is
declared) instead of the scope where the reduction clause appears. The
user-defined reduction is stored in the latter (a child scope), so the
lookup in the operator's owning scope could not find it and the clause
was reported as invalid.
Look up the reduction in the scope of the clause via
context_.FindScope(source). FindUserReduction already searches enclosing
scopes, so this both finds a locally declared reduction and continues to
find one that is host- or use-associated. The lowering side already
resolves the reduction in the current scope, so no lowering change is
needed.
This is a follow-up of PR #202474.
Commit: 2130acba394cf872bf48fcd96e4a3337f4dc0fd0
https://github.com/llvm/llvm-project/commit/2130acba394cf872bf48fcd96e4a3337f4dc0fd0
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M .github/workflows/test-suite.yml
Log Message:
-----------
[GitHub] Post ./utils/compare.py results in /test-suite (#208154)
llvm-test-suite comes with a ./utils/compare.py script which can compare
metrics across different builds. This PR adds support for displaying
these results in the GitHub comment as markdown table.
For now it just shows the difference in code size (the size..text
metric), but in future it can be extended to show the reuslts of any
arbitrary LLVM statistic.
It also posts the link to the result json files themselves in case the
user wants to do some more analysis locally.
Commit: 290f3bc2d12e5875a0be386fad8f6a5dfce9d6a3
https://github.com/llvm/llvm-project/commit/290f3bc2d12e5875a0be386fad8f6a5dfce9d6a3
Author: Caroline Newcombe <caroline.newcombe at hpe.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M flang/include/flang/Semantics/openmp-utils.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/openmp-utils.cpp
A flang/test/Lower/OpenMP/collapse-imperfect-nest.f90
A flang/test/Lower/OpenMP/collapse-loop-transform.f90
M flang/test/Semantics/OpenMP/do-collapse.f90
M flang/test/Semantics/OpenMP/do-concurrent-collapse-60.f90
M flang/test/Semantics/OpenMP/do-concurrent-collapse.f90
M flang/test/Semantics/OpenMP/do08.f90
M flang/test/Semantics/OpenMP/do10.f90
M flang/test/Semantics/OpenMP/do13.f90
M flang/test/Semantics/OpenMP/do15.f90
M flang/test/Semantics/OpenMP/do16.f90
M flang/test/Semantics/OpenMP/do22.f90
A flang/test/Semantics/OpenMP/doacross-nesting-omp60.f90
A flang/test/Semantics/OpenMP/ordered-nesting-omp50.f90
A flang/test/Semantics/OpenMP/ordered-nesting-omp51.f90
Log Message:
-----------
[flang][OpenMP] Implement collapse for imperfectly nested loops (#202435)
Fixes #199092
Flang previously rejected intervening code between associated loops in a
collapsed nest (e.g. `collapse(2)` with statements between the outer and
inner DO). This patch removes that restriction and implements correct
lowering.
**Semantics:** accept intervening code retroactively for all versions,
except when perfect nesting is still required
OpenMP 5.0 introduced support for collapsing imperfectly nested loops
for worksharing-loop, simd, taskloop, and distribute constructs. OpenMP
5.1 later formalized this under the Canonical Loop Nest (CLN)
definition. This support is applied retroactively for all OpenMP
versions, since the semantics are safe to implement regardless of
version and for compatibility with other compilers.
The only case where perfect nesting is still enforced is when ordered
semantics require it:
- Pre-5.2: any ordered clause with an argument requires perfect nesting.
- 5.2+: perfect nesting is required only when the loop body contains
ordered directives with doacross (or the legacy depend(sink/source))
clauses.
A `DoacrossFinder` visitor is added to detect doacross directives in the
loop body while correctly not descending into nested OpenMP block/loop
constructs (which have their own binding context).
**Lowering**
Intervening statements are guarded by induction variable comparisons
within the flat `omp.loop_nest` body: "before" code executes when inner
induction variables equal their lower bounds; "after" code executes when
inner induction variables equal their last iteration values (`lb + ((ub
- lb) / step) * step)` for non-unit steps).
**Testing**
- Lowering lit test added
- Semantics tests: updated to remove expected errors for now-accepted
code; new tests added for coverage.
- llvm-test-suite update: (will add once opened)
Assisted by: Copilot
Commit: 2e3dcf66357f59dfceca8a9cbb9c3af493a66ad6
https://github.com/llvm/llvm-project/commit/2e3dcf66357f59dfceca8a9cbb9c3af493a66ad6
Author: Hongyu Chen <xxs_chy at outlook.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/lib/Headers/riscv_packed_simd.h
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
A llvm/test/CodeGen/RISCV/rvp-zip.ll
Log Message:
-----------
[Clang][P-ext] Support packed zip/unzip intrinsics (#208245)
This patch implements packed zip/unzip intrinsics with general shuffles.
Commit: d9681a08a79dc6c57b542483e829dc13c38009cb
https://github.com/llvm/llvm-project/commit/d9681a08a79dc6c57b542483e829dc13c38009cb
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM][Maintainers] Volunteer for LoopUnroll (#207802)
I've been reviewing and contributing PRs to the unroller for the past
few months. Since I plan on keeping that up, I figured I'd formally
volunteer as a maintainer.
I'm certainly not an expert on every aspect of the unroller, so no
worries if we feel that we need someone more experienced to fill this
gap.
Commit: c12df55e9a5ee84178c5d30c753a4799b63fec80
https://github.com/llvm/llvm-project/commit/c12df55e9a5ee84178c5d30c753a4799b63fec80
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/PassManagerInternal.h
Log Message:
-----------
[IR][NFC] Drop vtable from PassConcept/PassModel (#208168)
The PassConcept/PassModel vtable has a size of 64 bytes (offset to top,
RTTI pointer, complete object destructor, deleting destructor, run,
printPipeline, name, isRequired), which add up to 53kiB (all
targets)/44 kiB (single-target). As more back-end passes get ported to
the new pass manager, this size will increase.
Remove the vtables by replacing the virtual dispatch with explicit
function pointers, initialized when adding the pass to the pass manager.
While this *very* slightly increases the cost of adding a pass, there's
also a very slight win from avoiding the vtable indirection when
running/destructing the pass.
Commit: af53003dfee4afe3f003996dc09f55d59d63003a
https://github.com/llvm/llvm-project/commit/af53003dfee4afe3f003996dc09f55d59d63003a
Author: Federico Bruzzone <federico.bruzzone.i at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp
M mlir/test/Dialect/ArmSME/vector-legalization.mlir
Log Message:
-----------
[mlir][ArmSME] fix f64 scalable matmul crashes in `VectorLegalizationPass` (#207947)
This PR simply fix what we identified in iree-org/iree#24689.
**Note**: the new test did not pass the checks prior to this PR 🫶
@banach-space @egebeysel @AGindinson
---------
Signed-off-by: Federico Bruzzone <federico.bruzzone.i at gmail.com>
Co-authored-by: Artem Gindinson <gindinson at roofline.ai>
Commit: eb37dfcad129d3e4e14daaa871a52428e424f11f
https://github.com/llvm/llvm-project/commit/eb37dfcad129d3e4e14daaa871a52428e424f11f
Author: Tom Stellard <tstellar at redhat.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M .github/workflows/commit-access-greeter.yml
Log Message:
-----------
workflows/commit-access-greeter: Use github-automation container (#206311)
Commit: 01846f68e5ae612fd348784265e14c0130cd79fd
https://github.com/llvm/llvm-project/commit/01846f68e5ae612fd348784265e14c0130cd79fd
Author: Jan Korous <jkorous at apple.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
A clang/include/clang/ScalableStaticAnalysis/SourceTransformation/YAMLSourceEditFormat.h
M clang/lib/ScalableStaticAnalysis/SourceTransformation/CMakeLists.txt
A clang/lib/ScalableStaticAnalysis/SourceTransformation/YAMLSourceEditFormat.cpp
M clang/unittests/ScalableStaticAnalysis/CMakeLists.txt
A clang/unittests/ScalableStaticAnalysis/SourceTransformation/YAMLFormatTest.cpp
Log Message:
-----------
[clang][ssaf] Add YAML source-edit format (#204491)
Adds the built-in `SourceEditFormat`, registered under the file
extension `yaml`. The writer drives `llvm::yaml::Output` against the
existing `clang::tooling::TranslationUnitReplacements` `MappingTraits`
from `clang/Tooling/ReplacementsYaml.h`, so the resulting document is
byte-for-byte consumable by `clang-apply-replacements`.
Anchored via `SSAFYAMLSourceEditFormatAnchorSource` so static builds
keep the registration.
Assisted-By: Claude Opus 4.7
Commit: da4bbda3dcefbaf88c2f336afd03c4a6ebb41a27
https://github.com/llvm/llvm-project/commit/da4bbda3dcefbaf88c2f336afd03c4a6ebb41a27
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
A llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc-fake16.txt
R llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
Log Message:
-----------
[AMDGPU][NFC] Templatise and roundtrip gfx12_asm_vopc.s (#208265)
This is just an amended version of the corresponding gfx11 test.
Eliminates the current largest contributor into the undesired delta vs
the downstream True16 branch across MC tests.
Commit: d7a09fb4ac7a3f231f1e4be7c00ef8c47e12d76b
https://github.com/llvm/llvm-project/commit/d7a09fb4ac7a3f231f1e4be7c00ef8c47e12d76b
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/FunctionExtras.h
Log Message:
-----------
[ADT][NFC] Simplify llvm::unique_function (#208251)
Refactor the core of UniqueFunctionBase to move away from static
function pointer tables, which consume ~4kiB in .data.rel.ro. Instead,
store two function pointers on construction of the UniqueFunctionBase,
one for call and one that combines move and destruction. Retain the
memcpy path for trivial inline structs. (I haven't verified whether this
is actually beneficial.)
Also, greatly simplify the class and implement the callbacks using
lambdas.
Commit: bd57e09f6a6e3a8eb911e45816d7038f4ff8b017
https://github.com/llvm/llvm-project/commit/bd57e09f6a6e3a8eb911e45816d7038f4ff8b017
Author: Alex Langford <alangford at apple.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M lldb/include/lldb/Target/DynamicRegisterInfo.h
M lldb/include/lldb/lldb-forward.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h
M lldb/source/Plugins/Process/gdb-remote/ThreadGDBRemote.cpp
M lldb/source/Plugins/Process/gdb-remote/ThreadGDBRemote.h
M lldb/source/Plugins/Process/wasm/ProcessWasm.h
M lldb/source/Plugins/Process/wasm/RegisterContextWasm.cpp
M lldb/source/Plugins/Process/wasm/RegisterContextWasm.h
Log Message:
-----------
[lldb] Remove GDBRemoteDynamicRegisterInfo (#208067)
At this point, GDBRemoteDynamicRegisterInfo is an idempotent wrapper
around DynamicRegisterInfo. Its remaining methods are unimplemented as
of 3f5fd4b3c1d670649b59f3631287b6f54c6b85ee, so the only functional
difference is that it provides public copy and copy-assign constructors.
I propose that GDBRemoteDynamicRegisterInfo be removed in favor of
DynamicRegisterInfo.
Commit: 691bda58840dbeccc942cbdde7e01ab53740cd0f
https://github.com/llvm/llvm-project/commit/691bda58840dbeccc942cbdde7e01ab53740cd0f
Author: Alex Langford <alangford at apple.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M lldb/include/lldb/Target/Target.h
M lldb/source/API/SBBreakpointName.cpp
M lldb/source/API/SBTarget.cpp
M lldb/source/Breakpoint/BreakpointIDList.cpp
M lldb/source/Commands/CommandObjectBreakpoint.cpp
M lldb/source/Target/Target.cpp
Log Message:
-----------
[lldb] Remove ConstString from remaining BreakpointName functionality (#206856)
Commit: 777ec1fff4502f6913818de5970a1c060a966877
https://github.com/llvm/llvm-project/commit/777ec1fff4502f6913818de5970a1c060a966877
Author: Alex Langford <alangford at apple.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M lldb/include/lldb/DataFormatters/FormatManager.h
Log Message:
-----------
[lldb] Remove unused overload FormatManager::GetCategory(const char *, bool) (#208109)
Commit: 3424d452ae6e4ec00e6f2e4149f3031471960e47
https://github.com/llvm/llvm-project/commit/3424d452ae6e4ec00e6f2e4149f3031471960e47
Author: Anonmiraj <ezzibrahimx at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/lib/AST/CXXInheritance.cpp
Log Message:
-----------
[clang][NFC] Compute current instantiation less frequently in `lookupInBases` (#208139)
While benchmarking I noticed that #118003 causes a small compile-time
regression. Right now, it computes `isCurrentInstantiation` for every
base during name lookup.
We can easily avoid this overhead by only computing it when a dependent
base could actually be skipped.
Commit: 6560fef7724bbd9baa57d3f09d077c4d2e69c868
https://github.com/llvm/llvm-project/commit/6560fef7724bbd9baa57d3f09d077c4d2e69c868
Author: Ziqing Luo <ziqing_luo at apple.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
A clang/include/clang/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointers.h
M clang/include/clang/ScalableStaticAnalysis/BuiltinAnchorSources.def
M clang/lib/ScalableStaticAnalysis/Analyses/CMakeLists.txt
A clang/lib/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointersExtractor.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/SSAFAnalysesCommon.h
A clang/unittests/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointersExtractorTest.cpp
M clang/unittests/ScalableStaticAnalysis/CMakeLists.txt
Log Message:
-----------
[SSAF][Extractor] Extract operator new/delete overload entities that shall retain their types (#206600)
This commit creates an extractor for operator new/delete overloads.
Overloads of operator new shall retain their void* return type,
regardless of whether they are propagated by unsafe buffers. The same
applies to the parameters of operator delete overloads.
Therefore, clang-reforge eventually need this information.
rdar://179151541
---------
Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
Commit: cefd20c496edd4df4ccd1faf399ee0d971b60116
https://github.com/llvm/llvm-project/commit/cefd20c496edd4df4ccd1faf399ee0d971b60116
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Use DCI.CombineTo instead of DAG.ReplaceAllUsesWith in performReverseEVLCombine. (#208275)
This makes sure the replaced node is deleted without relying on it still
being in the worklist, schedules its users for revisiting, and prints
the debug message for the replacement.
Commit: fd796cffa1b38810fef4ce43c34a6fc72a621b1b
https://github.com/llvm/llvm-project/commit/fd796cffa1b38810fef4ce43c34a6fc72a621b1b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
M llvm/test/CodeGen/X86/vector-reduce-add-zext.ll
M llvm/test/CodeGen/X86/vector-reduce-ctpop.ll
Log Message:
-----------
[X86] combineArithReduction - truncate from v4iXX to v4i16 for PSADBW add reduction patterns (#208286)
Noticed while trying to make ISD::VECREDUCE_ADD legal - if we're using
PSADBW, we don't need to truncate down to v4i8 and then zero-padd the
lowest v8i8/64-bits, we can just use v4i16 and bitcast to v8i8 since we
know the upper 8-bits are zero.
Commit: 40455118dff8af2d662e50a2b6083c9c7174740d
https://github.com/llvm/llvm-project/commit/40455118dff8af2d662e50a2b6083c9c7174740d
Author: Fabrice de Gans <Steelskin at users.noreply.github.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/Plugins/PassPlugin.h
M llvm/utils/git/ids-check-helper.py
Log Message:
-----------
[ids-check] Add support for ignoring symbols (#208241)
`llvmGetPassPluginInfo()` is not exported from the LLVM dylib. It is
meant to be the entry point for a pass plugin in another dylib. As it
is, the ids-check workflow would automatically add the `LLVM_ABI`
annotation to it, which is incorrect.
This fixes the issue by explicitly marking the symbol as ignored.
The effort to build LLVM as a DLL is tracked in #109483.
Commit: abc27e39ab4d0d17820159329ee3faeaf31261ae
https://github.com/llvm/llvm-project/commit/abc27e39ab4d0d17820159329ee3faeaf31261ae
Author: Eli Friedman <efriedma at qti.qualcomm.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
A llvm/test/DebugInfo/AArch64/machine-cp-updates-dbg-reg-subreg.mir
Log Message:
-----------
[MachineCopyPropagation] Fix debug info referring to subregisters. (#207861)
When copy propagation removes a copy, it fixes debug info that refers to
the old register to instead refer to the new register. This logic didn't
really deal with subregisters; it took any DBG_VALUE that pointed to a
subregister of the old register, and replaced it with the full new
register.
This patch adds logic for subregisters: if a DBG_VALUE refers to a
subregister of the source register, find the corresponding subregister
of the destination register.
Fixes #207682
Commit: 6ed1ae68fa74c290c19ae8854469037ce105ae4a
https://github.com/llvm/llvm-project/commit/6ed1ae68fa74c290c19ae8854469037ce105ae4a
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/ptrauth-isel.ll
M llvm/test/CodeGen/AArch64/ptrauth-isel.mir
Log Message:
-----------
[AArch64][PAC] Reset `killed` operand flag in custom inserter of PAC pseudo (#158699)
If custom inserter changes the `AddrDisc` operand of `AArch64::PAC`
pseudo instruction, conservatively reset its `killed` flag. Keeping this
flag without checking if it is still legal may result in code of the
form
%disc = MOVKXi %addr(tied-def 0), 1234, 48
%signed = PAC %ptr(tied-def 0), 2, 0, killed %disc
# %addr is used past this point and %disc is not
being turned into
%signed = PAC %ptr(tied-def 0), 2, 1234, killed %addr
# %addr is used past this point, but the operand of
# the above instruction has killed flag
Commit: c7c7cab93eb2e96d96820668c029f9e1b7e4a00b
https://github.com/llvm/llvm-project/commit/c7c7cab93eb2e96d96820668c029f9e1b7e4a00b
Author: Rafael Auler <rafaelauler at meta.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M bolt/lib/Core/DIEBuilder.cpp
M bolt/test/X86/dwarf5-locexpr-addrx.s
Log Message:
-----------
[BOLT] Fix DW_FORM_implicit_const values lost during DWARF5 rewriting (#192166)
Summary:
Fix two bugs in DIEBuilder that caused DW_FORM_implicit_const values to
be zeroed out when rewriting DWARF5 debug sections
(--update-debug-sections).
1. In constructDIEFast(), DWARFFormValue was constructed with just the
form code, leaving the value at 0. For DW_FORM_implicit_const,
extractValue() is a no-op since the value is expected to be pre-set.
Fix: use AttrSpec.getFormValue() which initializes the value from the
abbreviation table.
2. In assignAbbrev(), AddAttribute(Attr.getAttribute(), Attr.getForm())
used the two-argument overload which discards the implicit_const value.
Fix: use AddAttribute(Attr) to copy the full DIEAbbrevData.
Fixes https://github.com/llvm/llvm-project/issues/192084
Commit: 2c6a3d29636a54246738347f801c77cb15ac8241
https://github.com/llvm/llvm-project/commit/2c6a3d29636a54246738347f801c77cb15ac8241
Author: Drew Kersnar <dkersnar at nvidia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/SimplifyCFG/rangereduce.ll
Log Message:
-----------
[SimplifyCFG] Improve reduceSwitchRange to avoid unnecessary subtractions (#198374)
Dense switch cases can sometimes be achieved with only a shift, avoiding
a subtract. Change reduceSwitchRange to check for such cases before
falling back to using a subtract.
The changes to test9 demonstrates that for the purpose of lookup-table
lowering (triggered by the switch-to-lookup flag), the switch range
still ends up normalized to start at 0, the subtraction just happens
after the fshl.
test10 demonstrates where this change is useful, resulting in a dense
switch case with one less subtract.
test11 demonstrates cases where the subtract is still needed in order to
form a dense switch case.
Commit: bd9554f5da14d3a627fb8effc1769541ca05e4f9
https://github.com/llvm/llvm-project/commit/bd9554f5da14d3a627fb8effc1769541ca05e4f9
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/FunctionExtras.h
Log Message:
-----------
[ADT][NFC] UniqueFunction MSVC fix (#208293)
Fixup of #208251 for MSVC, which erroneously treats uses of non-static
constexpr variables as odr-use and requires them to be captured.
Commit: e07cdf3cf22db202d9a29b66a78f9e5f83f21660
https://github.com/llvm/llvm-project/commit/e07cdf3cf22db202d9a29b66a78f9e5f83f21660
Author: DylanFleming-arm <85629460+DylanFleming-arm at users.noreply.github.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
A libc/src/mathvec/aarch64/CMakeLists.txt
A libc/src/mathvec/aarch64/common.h
A libc/src/mathvec/aarch64/expf.cpp
Log Message:
-----------
[libc][mathvec][aarch64] Add AdvSIMD optimised expf (#206776)
This PR adds an AdvSIMD optimised version of the generic expf, using
intrinsics.
Commit: 031b773b01700acf82f5977a5aa6024621b8211c
https://github.com/llvm/llvm-project/commit/031b773b01700acf82f5977a5aa6024621b8211c
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang-tools-extra/clang-tidy/misc/DefinitionsInHeadersCheck.cpp
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/refactor/tweaks/DefineInline.cpp
M clang/docs/LibASTMatchersReference.html
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/JSONNodeDumper.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/ASTMatchers/ASTMatchersInternal.h
M clang/include/clang/Basic/Specifiers.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTDumper.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/Comment.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/ASTMatchers/Dynamic/Registry.cpp
M clang/lib/Analysis/ExprMutationAnalyzer.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
M clang/lib/CodeGen/CGVTables.cpp
M clang/lib/Index/IndexingContext.cpp
M clang/lib/InstallAPI/Visitor.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/StaticAnalyzer/Core/BugSuppression.cpp
M clang/lib/Tooling/Syntax/BuildTree.cpp
M clang/test/AST/ast-dump-templates-pattern.cpp
M clang/test/CXX/basic/basic.link/p11.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg7xx.cpp
M clang/test/CXX/temp/temp.arg/temp.arg.template/p3-2a.cpp
M clang/test/CXX/temp/temp.constr/temp.constr.decl/p4.cpp
M clang/test/CXX/temp/temp.decls/temp.spec.partial/temp.spec.partial.member/p2.cpp
M clang/test/CXX/temp/temp.spec/temp.expl.spec/p7.cpp
M clang/test/CodeGenCXX/default-arguments.cpp
M clang/test/CodeGenCXX/explicit-instantiation.cpp
A clang/test/Modules/GH208100.cpp
M clang/test/SemaCXX/GH195416.cpp
M clang/test/SemaCXX/constant-expression-cxx14.cpp
M clang/test/SemaCXX/deduced-return-type-cxx14.cpp
M clang/test/SemaCXX/member-class-11.cpp
A clang/test/SemaTemplate/GH202358.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/test/SemaTemplate/friend-template.cpp
M clang/test/SemaTemplate/instantiate-scope.cpp
M clang/test/Templight/templight-default-func-arg.cpp
M clang/test/Templight/templight-empty-entries-fix.cpp
M clang/tools/libclang/CIndex.cpp
M clang/unittests/AST/ASTImporterTest.cpp
M clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
Log Message:
-----------
[clang] Reland: fix getTemplateInstantiationArgs (#208285)
Relands https://github.com/llvm/llvm-project/pull/199528
Previous: https://github.com/llvm/llvm-project/pull/207825
This implements a new strategy for collecting the template arguments, by
relying on the qualifiers and template parameter lists to navigate the
template
context of out-of-line definitions.
This greatly simplifies the signature of that function, by removing a
bunch
of workarounds, and simpliffying a couple that weren't removed yet.
Since this now relies on qualifiers and template parameter lists,
this patch expends most of its effort making sure these are placed,
transformed and propagated to template instantiations.
Also makes the explicit specialization AST nodes stop abusing the
template
parameter lists by storing it's own template parameter list, creating a
dedicated field for them, similar to partial specializations.
Fixes https://github.com/llvm/llvm-project/issues/202106
Fixes https://github.com/llvm/llvm-project/issues/202109
Fixes #208100
Fixes #202358
Changes since last landing:
* Instantiated method decls uses a separate path, also needs merging of
deduced return type.
* Handle failures instantiating redeclaration for default arguments
(fails in some error recovery scenarios).
Commit: 9fde8452156883976b6264afffa9f8f259e733ec
https://github.com/llvm/llvm-project/commit/9fde8452156883976b6264afffa9f8f259e733ec
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M .github/new-prs-labeler.yml
M llvm/docs/AddingConstrainedIntrinsics.rst
A llvm/docs/LangRef.md
R llvm/docs/LangRef.rst
Log Message:
-----------
[docs] Rename LangRef.{rst|md} (#201974)
Tracking issue: #201242
Migration guide docs: https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
RFC: https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/90840
This commit does not use valid markdown, so the docs will not build, but
they will be fixed in an immediate follow-up commit that does the
migration.
Commit: 2cb32e4e72ce1e6094abc534510b405c1c84c5be
https://github.com/llvm/llvm-project/commit/2cb32e4e72ce1e6094abc534510b405c1c84c5be
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/docs/LangRef.md
Log Message:
-----------
[docs] Rewrite LangRef.md as Markdown (#201975)
Tracking issue: #201242
Migration guide docs:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
RFC:
https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/90840
This change migrates LangRef by itself, since it is quite a large
document with many idiosyncracies.
LangRef makes extensive use of definition lists, which apparently
require enabling the deflist MyST extension in Sphinx conf.py. In part
because definition list boundaries are controlled by indentation,
several of them required manual fixups to get the nesting right. Some of
the issues were pre-existing broken indentation, but this should now be
much better.
I have a verification script that tracks all anchors and ensures that
all previous anchors are carried over to the new document, so no
mid-document links are broken.
Commit: b7cf10c60748049efede67b5e1bf8aed87daea70
https://github.com/llvm/llvm-project/commit/b7cf10c60748049efede67b5e1bf8aed87daea70
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/docs/PointerAuthentication.rst
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Headers/ptrauth.h
M clang/lib/Sema/SemaChecking.cpp
M clang/test/CodeGen/ptrauth-intrinsics.c
M clang/test/Sema/ptrauth-intrinsics-macro.c
M clang/test/Sema/ptrauth.c
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
A llvm/test/CodeGen/AArch64/ptrauth-intrinsic-auth-with-pc-and-resign.ll
Log Message:
-----------
[arm64e] Add a builtin + intrinsic for arm64e PAuth_LR: __builtin_ptr_auth_auth_with_pc_and_resign (#202742)
The new builtin behaves like __builtin_ptrauth_auth_and_resign, but
incorporates the address of the signing instruction (i.e. the
`pacibsppc`/`paciasppc`) when performing the auth side, and subsequently
re-signs using a different scheme. Authenticating the re-signed value
will fail if and only if authenticating the original value with the
incorporated pc would have failed.
Commit: 23cead908f2d662e8f157b9a826fd489574b1f81
https://github.com/llvm/llvm-project/commit/23cead908f2d662e8f157b9a826fd489574b1f81
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC] Fix getInsertExtractIndex for ExtractElement and use unsigned indices
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/208317
Commit: 19c1b2c3f741b55a437e940417fab46b2bf5afda
https://github.com/llvm/llvm-project/commit/19c1b2c3f741b55a437e940417fab46b2bf5afda
Author: Alex Langford <alangford at apple.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M lldb/include/lldb/DataFormatters/DataVisualization.h
M lldb/include/lldb/DataFormatters/FormatManager.h
M lldb/include/lldb/DataFormatters/TypeCategoryMap.h
M lldb/source/DataFormatters/DataVisualization.cpp
M lldb/source/DataFormatters/TypeCategoryMap.cpp
Log Message:
-----------
[lldb] Remove unused AnyMatches functions from DataFormatters (#208288)
The only `AnyMatches` function actually used is in TypeCategoryImpl and
TieredFormatterContainer.
Commit: 41c4167cd066e8a9c3185917cafa9bef2cbfdb6d
https://github.com/llvm/llvm-project/commit/41c4167cd066e8a9c3185917cafa9bef2cbfdb6d
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
R llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-memops.ll
Log Message:
-----------
Revert "[AMDGPU] Use wavefront scope for single-wave workgroup synchronization (#187673)" (#208280)
This reverts commit ebc56070eb8d25c8dc73a2e97caaeb4db0f7c9fa.
Revert justified by correctness issues around DMA operations as seen in
https://github.com/llvm/llvm-project/pull/207473 .
Commit: f550160b2d59a780ed86ae2a72cd2e3b8b3a70fa
https://github.com/llvm/llvm-project/commit/f550160b2d59a780ed86ae2a72cd2e3b8b3a70fa
Author: Moazin K. <mkhatti at nvidia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/OpenACC/locations.f90
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
Log Message:
-----------
[flang][OpenACC] Attach `OpenACCLoopLocAttr` to `acc.loop` op (#208238)
Introduce an attribute `OpenACCLoopLocAttr` that can be attached to an
`acc.loop` operation to record loop locations and directive location
separately.
Attach it to `acc.loop` when building the op in flang.
Commit: a56885a9dcd578f9633132e9aa8420e0f7504569
https://github.com/llvm/llvm-project/commit/a56885a9dcd578f9633132e9aa8420e0f7504569
Author: Ikhlas Ajbar <iajbar at quicinc.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
A llvm/test/CodeGen/Hexagon/pr183850.ll
Log Message:
-----------
[Hexagon] Drop artificial VF sub-registers from W0-W15 (PR183850) (#208260)
Declaring VF0-VF15 as an artificial (vsub_fake) third sub-register of
W0-W15 caused MachineCopyPropagation to associate DBG_VALUEs of $wN with
unrelated $vM COPYs via reg-unit overlap, tripping the
hasDebugOperandForReg assertion in updateDbgUsersToReg.
Remove the fake sub-register from W0-W15. The reverse-alias WR0-WR15
keep vsub_fake intentionally.
Commit: e6b0517a80bc68784998c7f37740f8d2700b8249
https://github.com/llvm/llvm-project/commit/e6b0517a80bc68784998c7f37740f8d2700b8249
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
A llvm/test/Transforms/IndVarSimplify/eliminate-max-from-min-exit.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
Log Message:
-----------
[LV,IndVars] Add tests for missed SCEV min/max reasoning (NFC) (#208314)
Add extra tests for missed SCEV min/max reasoning, including
https://github.com/llvm/llvm-project/pull/204083.
Commit: b8cc84591b6a9b314b1e486b0db643f9f399cf90
https://github.com/llvm/llvm-project/commit/b8cc84591b6a9b314b1e486b0db643f9f399cf90
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/config.bzl
Log Message:
-----------
[bazel] Correct config.h definitions for musl (#207295)
The Bazel overlay encodes several configure-time config.h results
manually. It currently treats all Linux platforms as having
execinfo.h/backtrace() and mallinfo(). That matches glibc, but is false
when the build is configured for musl libc.
The upstream .bazelrc provides --config=hermetic-toolchain. A musl build
can be selected by pairing that with the platform labels from the
external Bazel module named llvm, for example:
bazel build --config=hermetic-toolchain \
--platforms=@llvm//platforms:linux_x86_64_musl \
--extra_execution_platforms=@llvm//toolchain:linux_x86_64_platform \
@llvm-project//llvm:not
Only define HAVE_BACKTRACE/BACKTRACE_HEADER when not targeting musl, and
only define HAVE_MALLINFO for GNU libc. With the old definitions, this
fails in LLVM Support, e.g.:
Unix/Process.inc:95:19: error: variable has incomplete type 'struct
mallinfo'
Unix/Signals.inc:51:10: fatal error: 'execinfo.h' file not found
Drafted with LLM assistance.
Commit: 362cd64fab04219913d89a14fc54767376a9a737
https://github.com/llvm/llvm-project/commit/362cd64fab04219913d89a14fc54767376a9a737
Author: Adel Ejjeh <adel.ejjeh at amd.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
A llvm/test/Transforms/SimpleLoopUnswitch/trivial-unswitch-convergent.ll
Log Message:
-----------
[SimpleLoopUnswitch] Don't latch-redirect trivial unswitch across convergent ops (#207047)
The trivial-unswitch case added in #204934 can redirect a loop-invariant
branch's latch edge to the loop exit, turning it into an exit branch
that then gets hoisted to the preheader. That changes how many
iterations (and, on GPUs, which lanes) execute the loop body.
When the loop contains a convergent operation that runs each iteration,
hoisting the branch lets one (possibly non-uniform) path bypass the loop
entirely and skip the convergent op. Concretely, this miscompiles an
AMDGPU warp reduction (llvm.amdgcn.update.dpp): lanes drop out of the
cross-lane shuffle, so block reductions come back with partial results.
Guard the new latch-redirect transform with the same convergent /
cross-block-token check that isSafeForNonTrivialUnswitching already
applies (refactored into a shared loopContainsConvergentOrTokenOp
helper). Adds a target-independent lit test that fails before this
change and passes after.
Co-authored-by: Claude Opus
Commit: 790fbc8fe5bfe69ffee21431d4a5f9da18efeda0
https://github.com/llvm/llvm-project/commit/790fbc8fe5bfe69ffee21431d4a5f9da18efeda0
Author: Ivan R. Ivanov <iivanov at nvidia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/test/Dialect/OpenACC/ops.mlir
Log Message:
-----------
[mlir][acc] Add acc.on_device op (#208096)
Add an operation to represent the runtime call to acc_on_device.
This runtime call is important to fold early in the compilation pipeline
and having an operation allows us to easily recognize it when emitted by
frontends.
Commit: 0bd936eee21f0272dbb604608afba33af19aedc0
https://github.com/llvm/llvm-project/commit/0bd936eee21f0272dbb604608afba33af19aedc0
Author: Fabian Parzefall <parzefall at meta.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/AArch64/computed-goto.s
M bolt/test/X86/indirect-goto.test
M bolt/test/indirect-goto-relocs.test
Log Message:
-----------
[BOLT] Register PIE indirect goto relocations (#206819)
PIE binaries use R_*_RELATIVE dynamic relocations for indirect goto jump
tables. BOLT creates entry points for their targets but does not mark
these addresses as targets from data relocations, so indirect jumps with
unknown control flow (which originates from indirect goto) have no CFG
successors and are interpreted as potential tail calls, while the jump
targets are incorrectly identified as additional entry points.
Add these offsets to the function's list of non-entry relocation
references instead of marking them as entry points. Extend relocation
rewriting to also check whether a block is externally referenced. This
mirrors behavior of data-to-code relocations in non-pie binaries.
Commit: 69e2ec6e7c0a9c58f5f99cf2a84895c511d7abf6
https://github.com/llvm/llvm-project/commit/69e2ec6e7c0a9c58f5f99cf2a84895c511d7abf6
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M utils/docs/llvm_sphinx/__init__.py
Log Message:
-----------
[docs] Enable colon_fence myst extension, fix admonitions (#208322)
The colon_fence myst extension enables triple-colon fences for
admonitions, as in:
:::{note}
**Regular** _markdown_ text, not code.
:::
Using triple colon fences for admonition blocks helps markdown editors
treat the body as markdown text, rather than fixed-width code with a
syntax highlight.
This change fixes a live doc bug in MyFirstTypoFix.md, which uses this
admonition style:
https://llvm.org/docs/MyFirstTypoFix.html
Currently ":::{note} The code changes presented" leaks through in the
HTML, and this one line change fixes it.
Commit: 470e52cf6d0c0548700eba9ec1517b24add367ad
https://github.com/llvm/llvm-project/commit/470e52cf6d0c0548700eba9ec1517b24add367ad
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
Log Message:
-----------
[PowerPC] Use INT64_MAX instead of LONG_MAX. (#208249)
The value of LONG_MAX is dependent on the host environment used to build
the compiler. For example, X86-64 Windows has a different value than
X86-64 Linux. Using LONG_MAX would give inconsistent results when cross
compiling.
Commit: 5c93fce720433b7302c4ac2e011ffb997c2fb977
https://github.com/llvm/llvm-project/commit/5c93fce720433b7302c4ac2e011ffb997c2fb977
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fold-tail-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/widen-gep-all-indices-invariant.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-saddsatcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/predicated-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/VPlan/X86/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/VPlan/buildvector-first-lane-only.ll
M llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-sink-replicate-region.ll
M llvm/test/Transforms/LoopVectorize/VPlan/tail-folding.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-before-after-all.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-alias-mask.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions-tail-folded.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-sink-scalars-and-merge.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-inbounds-flags-for-reverse-vector-pointer.ll
M llvm/test/Transforms/LoopVectorize/X86/fold-tail-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/pr81872.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorize-interleaved-accesses-gap.ll
M llvm/test/Transforms/LoopVectorize/alias-mask.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/optsize.ll
M llvm/test/Transforms/LoopVectorize/pr51614-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/reduction-order.ll
M llvm/test/Transforms/LoopVectorize/select-reduction.ll
M llvm/test/Transforms/LoopVectorize/store-reduction-results-in-tail-folded-loop.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-div.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-replicate-region.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
M llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
M llvm/test/Transforms/PhaseOrdering/ARM/arm_add_q7.ll
Log Message:
-----------
[VPlan] Model initial header mask as region value. (#196199)
Introduce a new VPRegionValue for the header mask, managed by loop
regions similar to the canonical IV.
The main benefit is we do not need to materialize the mask early and it
is trivial to find (no more need for patterns hard-coded in findHeaderMask).
It is currently materialized before computing costs, as we compute costs
for part of it currently.
PR: https://github.com/llvm/llvm-project/pull/196199
Commit: 9f709fbfe8a300257ee844ff64dda8a027e4ea73
https://github.com/llvm/llvm-project/commit/9f709fbfe8a300257ee844ff64dda8a027e4ea73
Author: ES3Q <qq571253675 at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/ACCSpecializeForHost.cpp
M mlir/test/Dialect/OpenACC/acc-specialize-for-host-fallback.mlir
Log Message:
-----------
[flang][OpenACC] Fix host fallback for acc.atomic.update (#207597)
The host fallback for `acc.atomic.update` only processed the first
operation in the region and used its result for the store, ignoring the
remaining operations and the `acc.yield` terminator. This generated
invalid IR when the region contained multiple operations.
1.Fix this by cloning all operations in the region and using the operand
of `acc.yield` as the final result to store.
2.Add tests for atomic read, write, update, and capture operations to
cover the host fallback path.
---------
Co-authored-by: ES3Q <ES3Q at QQ.COM>
Commit: c2f5040f47c8e7991b36cea3afc0b855956a5475
https://github.com/llvm/llvm-project/commit/c2f5040f47c8e7991b36cea3afc0b855956a5475
Author: Oleksandr Tarasiuk <oleksandr.tarasiuk at outlook.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M clang-tools-extra/clang-doc/Serialize.cpp
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/ASTStructuralEquivalence.h
M clang/include/clang/AST/DeclFriend.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/Basic/DeclNodes.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/Template.h
M clang/include/clang/Sema/TemplateDeduction.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ASTStructuralEquivalence.cpp
M clang/lib/AST/DeclFriend.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/ODRHash.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaAccess.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/test/CXX/class.access/class.friend/p3-cxx0x.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg19xx.cpp
M clang/test/CXX/drs/cwg28xx.cpp
M clang/test/CXX/drs/cwg6xx.cpp
M clang/test/CXX/temp/temp.decls/temp.friend/p5.cpp
R clang/test/CXX/temp/temp.decls/temp.friend/p6.cpp
M clang/test/Parser/cxx2c-variadic-friends.cpp
M clang/test/SemaCXX/many-template-parameter-lists.cpp
M clang/test/SemaTemplate/GH71595.cpp
M clang/test/SemaTemplate/concepts-friends.cpp
M clang/test/SemaTemplate/ctad.cpp
M clang/test/SemaTemplate/friend-template.cpp
Log Message:
-----------
Revert "[Clang] support friend declarations with a dependent nested-name-specifier" (#208302)
Reverts llvm/llvm-project#191268
---
Revert dependent friend support due to a crash in access checking
https://github.com/llvm/llvm-project/issues/208290
Commit: 1321b17540118f850320955e19eacd68bd1d7eef
https://github.com/llvm/llvm-project/commit/1321b17540118f850320955e19eacd68bd1d7eef
Author: Jackson Stogel <jtstogel at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/clang/unittests/BUILD.bazel
Log Message:
-----------
[bazel] Port 01846f68e5 (#208325)
Assisted-by: Gemini
Commit: bc97c56e6851858614876711e46f266dd1c1f58e
https://github.com/llvm/llvm-project/commit/bc97c56e6851858614876711e46f266dd1c1f58e
Author: Damyan Pepper <damyanp at microsoft.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
M llvm/lib/Target/DirectX/DXILOpBuilder.cpp
A llvm/test/CodeGen/DirectX/imul_umul.ll
A llvm/test/CodeGen/DirectX/overflow_intrinsics.ll
Log Message:
-----------
[DirectX] Expand {u,s}mul.with.overflow in DXILIntrinsicExpansion (#207297)
DXIL has no op for the llvm.{u,s}mul.with.overflow intrinsics. These can
be emulated by performing the full multiply using double-width values
and then checking the high-part of the result. However, this should be
avoided for 32-bit values since we don't want to make the shader start
using 64-bit values if it wasn't before. In this case we can use the
UMul and IMul DXIL operations that return the result as separate low &
high values.
Wider (64-bit) multiplies, which can't widen further, compute the high
half with same-width arithmetic instead.
Fixes #207090
---------
Co-authored-by: Copilot <223556219+Copilot at users.noreply.github.com>
Co-authored-by: Farzon Lotfi <farzonl at gmail.com>
Commit: 0842f3c80402c94e87f62be63c57a9229b3bace2
https://github.com/llvm/llvm-project/commit/0842f3c80402c94e87f62be63c57a9229b3bace2
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/test/Transforms/ConstraintElimination/constraint-overflow.ll
M llvm/test/Transforms/ConstraintElimination/induction-condition-in-loop-exit.ll
Log Message:
-----------
[ConstraintEli] Add more tests with latch guarded loops+overflows (NFC) (#208328)
Add additional tests with latch controlled loops and cases where we
currently bail out due to constraint-system overflows.
Commit: f8e18564dc4a40ed6f173f6c69449d0800070e9d
https://github.com/llvm/llvm-project/commit/f8e18564dc4a40ed6f173f6c69449d0800070e9d
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFAllocDelay.cpp
M flang/test/Transforms/CUF/cuf-alloc-delay.fir
Log Message:
-----------
[flang][cuda] Switch CUFAllocDelay to operate on fir.declare (#208334)
CUFAllocDelay previously matched hlfir.declare, requiring it to run
before HLFIR-to-FIR lowering. Match fir.declare instead so the pass can
be scheduled with the other CUF preparation passes (which also operate
on fir.declare), before cuf.alloc is lowered. The delay logic is
unchanged.
Commit: b310b1ab76f24a0e7a88c8ded76f54b816e5d542
https://github.com/llvm/llvm-project/commit/b310b1ab76f24a0e7a88c8ded76f54b816e5d542
Author: Matsu <47756807+khaki3 at users.noreply.github.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
M flang/test/Fir/CUDA/cuda-constructor-2.f90
Log Message:
-----------
[flang][cuda] Register device/constant globals as device-resident under -gpu=mem:unified (#208336)
```fortran
module m
integer, device :: aaa; bind(c, name='aaa_from_c') :: aaa
integer, constant :: zzz; bind(c, name='zzz_from_c') :: zzz
end module
```
```c
extern int aaa_from_c;
#pragma acc declare create(aaa_from_c) // same for zzz_from_c
```
In this code, under `-gpu=mem:unified` a module-scope device/constant
global is registered only as a CUDA variable. Another translation unit
that declares the same symbol on the host can make it be treated as host
memory, so the device symbol is unresolved at run time.
Fix: emit `cuf.register_variable_static` for device/constant globals
under `mem:unified` so they are additionally registered as
device-resident.
Commit: b5c94cfb1c12edc85a65be6299b0b9800b623492
https://github.com/llvm/llvm-project/commit/b5c94cfb1c12edc85a65be6299b0b9800b623492
Author: Evgenii Kudriashov <evgenii.kudriashov at intel.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/ldexp-avx512.ll
Log Message:
-----------
[X86] Split FLDEXP when AVX512 is not available (#208292)
Mark the 512-bit types Custom only under useAVX512Regs(); otherwise
generic type legalization splits FLDEXP into the legal narrower halves
that LowerFLDEXP handles.
Add a LIT test for the v8f64 -> two 256-bit vscalefpd split.
Co-authored-by: Yanliang Mu <yanliang.mu at intel.com>
Commit: c5ff07e5006598e16b0982288277e36b60842cf9
https://github.com/llvm/llvm-project/commit/c5ff07e5006598e16b0982288277e36b60842cf9
Author: Jackson Stogel <jtstogel at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[bazel] Add missing deps from 1321b17 (#208338)
Commit: 349375a83b85c481c8126ac2f3081b51bf4725d2
https://github.com/llvm/llvm-project/commit/349375a83b85c481c8126ac2f3081b51bf4725d2
Author: Adrian Prantl <aprantl at apple.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M lldb/bindings/interface/SBValueDocstrings.i
M lldb/include/lldb/API/SBValue.h
M lldb/include/lldb/Expression/DWARFExpression.h
M lldb/include/lldb/Expression/DWARFExpressionList.h
M lldb/include/lldb/ValueObject/ValueObject.h
M lldb/include/lldb/ValueObject/ValueObjectVariable.h
M lldb/source/API/SBValue.cpp
M lldb/source/Expression/DWARFExpression.cpp
M lldb/source/Expression/DWARFExpressionList.cpp
M lldb/source/ValueObject/ValueObject.cpp
M lldb/source/ValueObject/ValueObjectVariable.cpp
M lldb/test/API/python_api/value/change_values/TestChangeValueAPI.py
M lldb/unittests/Expression/DWARFExpressionTest.cpp
Log Message:
-----------
[LLDB] Add an API to check whether a variable is writable (#208042)
IDEs may offer functionality to set a variable to a specific value.
There are many situations where this isn't actually possible, for
example, if the variable's value is a constant or the result of a
complex DWARF expression. Instead of offering to change a value only to
have it fail with an error, this API lets the IDE query whether setting
a value is generally feasible so it can hide the action where it isn't
applicable.
rdar://142358140
Assisted-by: claude
Commit: 5d800d3285c1dd8cd438346d5256c35528d744c4
https://github.com/llvm/llvm-project/commit/5d800d3285c1dd8cd438346d5256c35528d744c4
Author: Eli Friedman <efriedma at qti.qualcomm.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/lib/Sema/SemaInit.cpp
A clang/test/AST/ast-dump-init.cpp
Log Message:
-----------
[clang] Fix type of the MaterializeTemporaryExpr with incomplete array type. (#187618)
This affects constructs like `int f(int (&&x)[]); int z = f({1});`.
A temporary logically can't have incomplete type: if we don't know the
type, we can't materialize it. Rearrange the casts to make more sense.
I'm not sure this has any practical effects at the moment due to the way
we use skipRValueSubobjectAdjustments; we usually end up ignoring the
type of the MaterializeTemporaryExpr.
Commit: 20a0cd83dcaade1912330a678063275ec3d47c2d
https://github.com/llvm/llvm-project/commit/20a0cd83dcaade1912330a678063275ec3d47c2d
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/fma-reduce-regression.ll
Log Message:
-----------
[SLP][NFC]Add a test with the regression in reduction, which should remain scalar FMAs
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/208349
Commit: 7a0aea35a25a4e21dca6c939456fedf8f6964319
https://github.com/llvm/llvm-project/commit/7a0aea35a25a4e21dca6c939456fedf8f6964319
Author: Ivan R. Ivanov <iivanov at nvidia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
A flang/include/flang/Optimizer/Builder/OpenACCIntrinsicCall.h
M flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Optimizer/Builder/CMakeLists.txt
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
A flang/lib/Optimizer/Builder/OpenACCIntrinsicCall.cpp
M flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp
Log Message:
-----------
[flang][acc] Emit acc.on_device operation for acc_on_device call (#208098)
It is important we recognize acc_on_device calls as they need to be
folded during compilation. Emitting this operation helps with the
recognition of the runtime call in the optimizer.
Commit: a8264ae5b4bd5ed460699e582e1612a76ed0c595
https://github.com/llvm/llvm-project/commit/a8264ae5b4bd5ed460699e582e1612a76ed0c595
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M clang/test/SemaCXX/deduced-return-type-cxx14.cpp
Log Message:
-----------
[clang] add triple to `test/SemaCXX/deduced-return-type-cxx14.cpp` (#208340)
Fixes issue reported here:
https://github.com/llvm/llvm-project/pull/208285#issuecomment-4919717057
Since that test file now uses the `cdecl` attribute, which is not
supported in some targets, pin that test to x86_64 triple.
Commit: 0fbdfc85b3bca4edc949966324c8b9cb57693194
https://github.com/llvm/llvm-project/commit/0fbdfc85b3bca4edc949966324c8b9cb57693194
Author: Ivan R. Ivanov <iivanov at nvidia.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.h
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/lib/Dialect/OpenACC/Transforms/ACCSpecializeForDevice.cpp
M mlir/test/Dialect/OpenACC/acc-specialize-for-device.mlir
Log Message:
-----------
[mlir][acc] Specialize acc.on_device with constant arg for device (#208099) (#208351)
Fold known result acc.on_device to a constant in device-side code.
Re-submitted PR due to accidental stack PR merge
Commit: 82fc0835cfddbca9594bdc797fa4fbe3f86b90fa
https://github.com/llvm/llvm-project/commit/82fc0835cfddbca9594bdc797fa4fbe3f86b90fa
Author: Max Graey <maxgraey at gmail.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M mlir/lib/Transforms/Utils/CMakeLists.txt
Log Message:
-----------
[MLIR] Add missing MLIRPass dep when DMLIR_ENABLE_PDL_IN_PATTERNMATCH=OFF used (NFC) (#208289)
When PDL dialect is disabled during build stage
(`DMLIR_ENABLE_PDL_IN_PATTERNMATCH=OFF`) we got a compiler errors due to
some of pdl deps transitively includes `MLIRPass` but without PDL this
dep missing and lead to compile errors
Commit: 060f128beedd8a6fa0bbab137dae9c4c82200a23
https://github.com/llvm/llvm-project/commit/060f128beedd8a6fa0bbab137dae9c4c82200a23
Author: Mark Zhuang <mark.zhuang at spacemit.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/TargetParser/Host.cpp
Log Message:
-----------
[RISCV] Map spacemit uarch strings to CPU names in host detection (#207636)
-mcpu/-mtune=native first tries hwprobe;
when that yields no usable CPU model it falls back to the
cpuinfo uarch line. Add spacemit,x60/x100/a100 there.
Commit: 232f98e8a873c374a00d64f70cedff6c61ee87d8
https://github.com/llvm/llvm-project/commit/232f98e8a873c374a00d64f70cedff6c61ee87d8
Author: hulxv <hulxxv at gmail.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M libc/shared/builtins.h
A libc/shared/builtins/divsf3.h
M libc/src/__support/builtins/CMakeLists.txt
A libc/src/__support/builtins/divsf3.h
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_builtins_test.cpp
Log Message:
-----------
[libc] add shared divsf3 builtin (#205679)
Re-exposes LLVM-libc's `__divsf3` as `shared::divsf3` for reuse by
compiler-rt's builtins.
Stacked change - merge these first:
- #200094
- #205669
- #205670
- #205671
- #205672
- #205673
- #205674
- #205675
- #205676
- #205677
- #205678
Part of #197824
Commit: 533470ead993440e3cd79c48d77a21218e165ff2
https://github.com/llvm/llvm-project/commit/533470ead993440e3cd79c48d77a21218e165ff2
Author: AZero13 <gfunni234 at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Transforms/ObjCARC/ObjCARCOpts.cpp
M llvm/test/Transforms/ObjCARC/test_autorelease_pool.ll
Log Message:
-----------
[ObjCARC] Improve empty autorelease pool elimination in OptimizeAutoreleasePools (#200310)
Verify push/pop pairing before popping the stack, clear the pool stack
on mismatch, and erase the push before the pop for consistency.
Commit: 57e7ceed3398ed1ddf28afdf78ba81cc2638c665
https://github.com/llvm/llvm-project/commit/57e7ceed3398ed1ddf28afdf78ba81cc2638c665
Author: Kito Cheng <kito.cheng at sifive.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/IRBuilder.h
M llvm/lib/CodeGen/ReplaceWithVeclib.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/unittests/Analysis/ValueTrackingTest.cpp
M llvm/unittests/IR/IRBuilderTest.cpp
Log Message:
-----------
[IRBuilder] Add FMFSource overloads for CreateCall (#208171)
CreateCall had no way to set fast-math-flags at creation time, so
callers had to build the call and copy the flags in a second step:
CallInst *C = B.CreateCall(Fn, Args);
C->copyFastMathFlags(Src);
Add FMFSource overloads (mirroring CreateIntrinsic) so the flags can be
copied from a source instruction or FastMathFlags in one call:
CallInst *C = B.CreateCall(Fn, Args, /*FMFSource=*/Src);
The FMFSource parameter has no default, so existing CreateCall callers
are unaffected and overload resolution stays unambiguous.
Assisted-by: Opus 4.8
Commit: 76028e1199ad4d1a380c7cf367a072095f6dba01
https://github.com/llvm/llvm-project/commit/76028e1199ad4d1a380c7cf367a072095f6dba01
Author: Jim Lin <jim at andestech.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
Log Message:
-----------
[RISCV] Fix RISCVFoldMemOffset to report when it makes changes (#208149)
runOnMachineFunction initialized MadeChange to false and returned it,
but never set it to true even though the fold path rewrites memory
offsets, replaces registers, and erases the ADDI. As a result the pass
always reported that it made no changes, so the pass manager could keep
stale analyses valid after the function had actually been modified.
Set MadeChange to true after folding an ADDI.
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: 2df2a51c7593baa6286610ff45693b97dda9ea5c
https://github.com/llvm/llvm-project/commit/2df2a51c7593baa6286610ff45693b97dda9ea5c
Author: TelGome <93700071+TelGome at users.noreply.github.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsRISCV.td
M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
M clang/lib/Headers/riscv_packed_simd.h
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
Log Message:
-----------
[RISCV][P-ext] Support Packed Saturating Absolute Value. (#207978)
Commit: 2592df6cb04e72f548685a152cf93b46b30cee21
https://github.com/llvm/llvm-project/commit/2592df6cb04e72f548685a152cf93b46b30cee21
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
Log Message:
-----------
[NFCI][AMDGPU] Change foldOperand to return changed (#208352)
Commit: 697bd9704894691d6b0f40b3150d70047a6f181f
https://github.com/llvm/llvm-project/commit/697bd9704894691d6b0f40b3150d70047a6f181f
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M mlir/include/mlir/IR/Block.h
M mlir/include/mlir/IR/Region.h
M mlir/include/mlir/IR/RegionGraphTraits.h
M mlir/lib/IR/Region.cpp
Log Message:
-----------
Give each mlir::Block a stable ID within its parent region (#207617)
Assign each mlir::Block a stable ID within its parent region, mirroring
llvm::BasicBlock/llvm::Function (called ID, not number, since a block/op
number denotes position in MLIR): Block gains getBlockID() and reads -1u
while it has no parent region; Region gains nextBlockID with
getMaxBlockID() and getBlockIDEpoch(); the block ilist traits assign the
ID on add/transfer and invalidate it on removal; and
GraphTraits<mlir::Block*>/<mlir::Region*> expose
getNumber/getMaxNumber/getNumberEpoch. This makes
GraphHasNodeNumbers<mlir::Block*> true, moving MLIR's CFGLoopInfo and
dominator tree onto the number-indexed path. MLIR never renumbers
blocks,
so the epoch is a fixed 0.
Prerequisite for requiring GraphHasNodeNumbers in llvm::LoopInfoBase and
dropping its DenseMap fallback.
Aided by Claude Opus 4.8
Commit: 78b56d968c54ad6453a4324fe739cb5ec236e2d7
https://github.com/llvm/llvm-project/commit/78b56d968c54ad6453a4324fe739cb5ec236e2d7
Author: Kazu Hirata <kazu at google.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/ProfileData/SampleProf.h
M llvm/include/llvm/ProfileData/SampleProfReader.h
M llvm/include/llvm/ProfileData/SampleProfWriter.h
M llvm/lib/ProfileData/SampleProfReader.cpp
M llvm/lib/ProfileData/SampleProfWriter.cpp
M llvm/unittests/ProfileData/SampleProfTest.cpp
Log Message:
-----------
[ProfileData] Support format version 104 for extensible binary sample profiles (#206297)
This patch adds initial support for format version 104 in extensible
binary sample profiles to support the upcoming on-disk hash table.
This patch sets up the versioning scheme in the reader and writer as a
preparation step without actually introducing the on-disk hash table.
The reader is updated to support format version 104. The writer can
now write format version 104 profiles when requested via
-sample-profile-format-version, but continues to default to version
103 as version 104 is a work in progress. We plan to promote the
default version to 104 once the on-disk hash table support is fully
integrated in a subsequent patch.
RFC:
https://discourse.llvm.org/t/rfc-faster-sample-profile-loading/90957/4
Assisted-by: Antigravity
Commit: 720d986d66a0a437fd7f9b0d5dd0fa155dcb27f5
https://github.com/llvm/llvm-project/commit/720d986d66a0a437fd7f9b0d5dd0fa155dcb27f5
Author: Kazu Hirata <kazu at google.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/include/llvm/ProfileData/SampleProfReader.h
M llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
Log Message:
-----------
[SampleProfile] Introduce SampleProfileNameSet (NFC) (#208114)
This patch introduces a helper class SampleProfileNameSet to
encapsulate the construction of the name set and provide a contains
method.
I'm planning to speed up the membership queries into the name table.
With this patch, changes to the underlying data structure won't affect
use sites.
Assisted-by: Antigravity
Commit: 34b0a6e6d863a6f91698b435c72e69fcfebf13f2
https://github.com/llvm/llvm-project/commit/34b0a6e6d863a6f91698b435c72e69fcfebf13f2
Author: Yihan Wang <yronglin777 at gmail.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M clang/test/Interpreter/cxx20-modules.cppm
M clang/test/Interpreter/dynamic-library.cpp
M clang/test/Interpreter/lit.local.cfg
Log Message:
-----------
[clang-repl] Avoid use `$LD_LIBRARY_PATH` in lit tests (#208170)
Strengthen clang-repl lit tests by Avoid use `$LD_LIBRARY_PATH`. The
lit's internal shell does not expand shell variables such as
`$LD_LIBRARY_PATH`, so provide the current value as a lit substitution.
This PR can fix the following failures when user build llvm with
non-system C++ standard library.
```
# executed command: env 'LD_LIBRARY_PATH=<build dir>/tools/clang/test/Interpreter/Output/cxx20-modules.cppm.tmp:$LD_LIBRARY_PATH' <build dir>/bin/clang-repl -Xcc=-std=c++20 -Xcc=-fmodule-file=M=<build dir>/tools/clang/test/Interpreter/Output/cxx20-modules.cppm.tmp/mod.pcm -Xcc=--target=x86_64-linux-gnu
# .---command stderr------------
# | <build dir>/bin/clang-repl: /lib64/libstdc++.so.6: version `GLIBCXX_3.4.26' not found (required by <build dir>/bin/clang-repl)
# | <build dir>/bin/clang-repl: /lib64/libstdc++.so.6: version `GLIBCXX_3.4.29' not found (required by <build dir>/bin/clang-repl)
# | <build dir>/bin/clang-repl: /lib64/libstdc++.so.6: version `GLIBCXX_3.4.30' not found (required by <build dir>/bin/clang-repl)
# | <build dir>/bin/clang-repl: /lib64/libstdc++.so.6: version `CXXABI_1.3.13' not found (required by <build dir>/bin/clang-repl)
# `-----------------------------
```
Signed-off-by: yronglin <yronglin777 at gmail.com>
Commit: 7f3d91d14ae33a8206b536ac1ffe69565423ced3
https://github.com/llvm/llvm-project/commit/7f3d91d14ae33a8206b536ac1ffe69565423ced3
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s
Log Message:
-----------
[RISCV][MCA] Avoid deriving EMUL without SEW (#207986)
When only an LMUL instrument is active, SEW is unavailable. Avoid
deriving EMUL for vector memory instructions in that case and fall back
to the base scheduling class.
Closes #170118.
Commit: 1325d8591159527e99683aac8240b9134b5d1cfa
https://github.com/llvm/llvm-project/commit/1325d8591159527e99683aac8240b9134b5d1cfa
Author: vporpo <vasileios.porpodas at amd.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Scheduler.cpp
Log Message:
-----------
[SandboxVec][Scheduler][NFC] Cleanup: Use interval in loop and reset sched state (#205465)
Replace the for loop that iterates between TopI and LowestI with a range
loop over ResetIntvl and move the reset of the scheduling state to this
loop.
We iterate over the loop in the reverse order than before but the
functionality should not change.
Commit: 06488f6c8d8941cda4973df32d420c71877be3e6
https://github.com/llvm/llvm-project/commit/06488f6c8d8941cda4973df32d420c71877be3e6
Author: Nikhil Kalra <nikhil.kalra at gmail.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M mlir/include/mlir/Bindings/Python/IRCore.h
Log Message:
-----------
[mlir] Make the Python binding type casters well-formed under C++23 (#208093)
The nanobind type/attr/loc/value casters in IRCore.h return a by-value
PyType/PyAttribute/PyLocation/PyValue as their DerivedTy result.
Under pre-C++23 rules, this was a rvalue that would decay to a lvalue
when passed to the DerivedTy constructor.
Under C++23's P2266 (implicit move on return), that return operand is an
xvalue, which cannot bind the PyConcrete* constructors that take a
non-const lvalue reference.
This patch constructs the derived type explicitly (return
DerivedTy(arg);) using the lvalue constructor; this preserves the
pre-C++23 behavior on C++23 builds.
Commit: 4899b8d6f6b9d48349d89528ec6898704b289672
https://github.com/llvm/llvm-project/commit/4899b8d6f6b9d48349d89528ec6898704b289672
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll
Log Message:
-----------
[RISCV] Don't require splats to have a single use in performReverseEVLCombine. (#208326)
Test was written by Claude
Commit: 91746ca146d4047e9d0ec98fd7d4a3d91f88a759
https://github.com/llvm/llvm-project/commit/91746ca146d4047e9d0ec98fd7d4a3d91f88a759
Author: qyingwu <46992476+qyingwu at users.noreply.github.com>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M mlir/cmake/modules/CMakeLists.txt
M mlir/cmake/modules/MLIRConfig.cmake.in
Log Message:
-----------
[mlir][cmake] Export MLIR_LINK_MLIR_DYLIB in MLIRConfig.cmake (#207336)
Fixes #197175.
`MLIRConfig.cmake` did not propagate `MLIR_LINK_MLIR_DYLIB` to out-of-tree MLIR users. Standalone projects using `find_package(MLIR CONFIG)` and `include(AddMLIR)` therefore could not observe the value used by `mlir_target_link_libraries(...)` when MLIR was configured with `-DMLIR_LINK_MLIR_DYLIB=ON`.
Export `MLIR_LINK_MLIR_DYLIB` through `MLIRConfig.cmake`.
AI tool usage:
I used ChatGPT/Codex to help understand the issue, identify the analogous LLVM CMake pattern, and draft the PR description. I manually reviewed the final patch and verification.
Commit: 21be7ef4473615a774f7c26beeebba3161b72322
https://github.com/llvm/llvm-project/commit/21be7ef4473615a774f7c26beeebba3161b72322
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/CMakeLists.txt
A libc/include/err.yaml
M libc/src/CMakeLists.txt
A libc/src/err/CMakeLists.txt
A libc/src/err/err.cpp
A libc/src/err/err.h
A libc/src/err/errx.cpp
A libc/src/err/errx.h
A libc/src/err/report.cpp
A libc/src/err/report.h
A libc/src/err/verr.cpp
A libc/src/err/verr.h
A libc/src/err/verrx.cpp
A libc/src/err/verrx.h
A libc/src/err/vwarn.cpp
A libc/src/err/vwarn.h
A libc/src/err/vwarnx.cpp
A libc/src/err/vwarnx.h
A libc/src/err/warn.cpp
A libc/src/err/warn.h
A libc/src/err/warnx.cpp
A libc/src/err/warnx.h
M libc/test/src/CMakeLists.txt
A libc/test/src/err/CMakeLists.txt
A libc/test/src/err/err_test.cpp
A libc/test/src/err/errx_test.cpp
A libc/test/src/err/verr_test.cpp
A libc/test/src/err/verrx_test.cpp
A libc/test/src/err/vwarn_test.cpp
A libc/test/src/err/vwarnx_test.cpp
A libc/test/src/err/warn_test.cpp
A libc/test/src/err/warnx_test.cpp
Log Message:
-----------
[libc] Implement BSD extensions in <err.h> (#199055)
Implemented the BSD-extension functions defined in <err.h>:
- err, errx, verr, verrx
- warn, warnx, vwarn, vwarnx
Added an internal reporting helper in src/__support/Err. The err family
functions call internal::exit directly to satisfy [[noreturn]]
requirements. Enabled these entrypoints for aarch64, riscv, and x86_64.
Assisted-by: Automated tooling, human reviewed.
Commit: 9354d5ceac1ab8a9f6f5ca86e5400909acab4bf6
https://github.com/llvm/llvm-project/commit/9354d5ceac1ab8a9f6f5ca86e5400909acab4bf6
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M clang-tools-extra/clang-tidy/cppcoreguidelines/RvalueReferenceParamNotMovedCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/RvalueReferenceParamNotMovedCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/rvalue-reference-param-not-moved.rst
A clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/rvalue-reference-param-not-moved-allow-implicit.cpp
Log Message:
-----------
[clang-tidy] Add AllowImplicitMove option to rvalue-reference-param-not-moved (#190541)
Fixes https://github.com/llvm/llvm-project/issues/132419.
Commit: 594655d1a76fea809fd11099da97a74360f56f59
https://github.com/llvm/llvm-project/commit/594655d1a76fea809fd11099da97a74360f56f59
Author: Jim Lin <jim at andestech.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
Log Message:
-----------
[RISCV] Remove duplicate addRequired in RISCVDeadRegisterDefinitions (#208366)
getAnalysisUsage called AU.addRequired<LiveIntervalsWrapperPass>() twice.
Drop the redundant second call.
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: bea7080fe3ce45d397c2aefda3e27dff868f7746
https://github.com/llvm/llvm-project/commit/bea7080fe3ce45d397c2aefda3e27dff868f7746
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/ByteCode/Program.h
A clang/test/AST/ByteCode/module-dummy-redecl.cpp
Log Message:
-----------
[clang][bytecode] Use first decl in redeclaration chain to cache dummy pointers (#208377)
Commit: be40b8ec4edad70106c9a81de11f1cf24c8b80f9
https://github.com/llvm/llvm-project/commit/be40b8ec4edad70106c9a81de11f1cf24c8b80f9
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-08 (Wed, 08 Jul 2026)
Changed paths:
M bolt/include/bolt/Core/BinaryBasicBlock.h
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/lib/Core/BinaryFunction.cpp
Log Message:
-----------
[BOLT] Give BinaryBasicBlock a GraphTraits block number (#207899)
LoopInfoBase (and DominatorTreeBase) keep a DenseMap fallback for block
types whose GraphTraits lacks getNumber() (#103400); BOLT's
BinaryLoopInfo is one of the last two users.
BinaryBasicBlock already carries a dense [0, size) index (getIndex(),
assigned by updateBBIndices()). Expose it as the GraphTraits node
number, mirroring llvm::BasicBlock/Function.
This makes `GraphHasNodeNumbers<BinaryBasicBlock *>` true, moving BOLT's
LoopInfo and DominatorTree onto the number-indexed (SmallVector) path.
Prerequisite for requiring GraphHasNodeNumbers in LoopInfoBase.
Aided by Claude Opus 4.8
Commit: 5ccca5f215939645995035ecd5fe40759e2cc0a6
https://github.com/llvm/llvm-project/commit/5ccca5f215939645995035ecd5fe40759e2cc0a6
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Cleanup print functions of recipes (NFC) (#207434)
In particular, VPPhiAccessors should not query the derivative recipe's
operands, and query incoming values instead. The printPhiOperands
function would crash if used in more derivative recipes.
Commit: 9b4d930bc49953735bc34318edd701bb4d2492a8
https://github.com/llvm/llvm-project/commit/9b4d930bc49953735bc34318edd701bb4d2492a8
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
A llvm/test/CodeGen/WebAssembly/fast-isel-atomic-fold.ll
Log Message:
-----------
[FastISel][WebAssembly] Don't perform load folding for atomic load (#207728)
Don't try to fold an atomic load into other instructions. Atomic loads
may require different instructions / barriers / etc.
Wasm started using this functionality in
https://github.com/llvm/llvm-project/pull/182767. It's not really
specific to wasm, but the problem is masked on some other targets (e.g.
on X86 even a seq_cst atomic load can be lowered to a plain load).
Commit: c0ef9c53ecca5f033dc6a022da2a986f6925c70e
https://github.com/llvm/llvm-project/commit/c0ef9c53ecca5f033dc6a022da2a986f6925c70e
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/WebAssembly.td
M llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp
M llvm/test/MC/WebAssembly/function-alias.ll
Log Message:
-----------
[WebAssembly] Use SubtargetFeature's Implies field (#206643)
This makes use of `SubtargetFeature`'s `Implies` field, which lets us
define feature dependencies:
https://github.com/llvm/llvm-project/blob/442c59c75ca384db53a6d6d81686b17ea4b397c3/llvm/include/llvm/Target/Target.td#L568-L571
and removes C++ code that specified feature dependencies.
These are the dependencies specified. EH dependencies are currently only
specified in clang options, and others are specified in
`WebAssemblySubtarget.cpp`.
- exception-handling implies multivalue and reference-types
- bulk-memory implifes bulk-memory-opt
- gc implies reference-types
- reference-types implies call-indirect-overlong
The features in `WebAssembly.td` were sorted in the alphabetical order,
but this changes it because implied features have to come before the
implying feature, e.g., multivalue and reference-types have to come
before exception-handling.
---
One semantic difference from the current code, is, when reference-types
implies call-indirect-overlong,
```console
llc -mattr=+reference-types,-call-indirect-overlong
```
this currently forces call-indirect-overlong to be true despite there is
`-call-indirect-overlong`, because
https://github.com/llvm/llvm-project/blob/442c59c75ca384db53a6d6d81686b17ea4b397c3/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp#L63-L67
But with the `Implies` field, disabling call-indirect-overlong disabled
both features, because TableGen thinks reference-types depends on
call-indirect-overlong, so without call-indirect-overlong,
reference-types can't be enabled. This is not exactly true with the
relationship of reference-types and call-indirect-overlong, but
generally makes sense for true dependencies, like exception-handling
implying (=depending on) multivalue and reference-types.
Also this wouldn't really affect the end users because these are `llc`
flags.
Commit: 6b7cd6499b1638ad4341148ab70f28cd5ac23e20
https://github.com/llvm/llvm-project/commit/6b7cd6499b1638ad4341148ab70f28cd5ac23e20
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M libc/test/UnitTest/BazelFilePath.cpp
Log Message:
-----------
[libc][bazel] Append '/' to TEST_UNDECLARED_OUTPUTS_DIR (#207710)
The environment variable does not end with a slash, so we need to add
one. Without this, the tests work, but don't achieve the intended effect
of writing to the undeclared outputs dir.
Commit: 832402097e77794095c3b59be9ea60bbaa4ce0f3
https://github.com/llvm/llvm-project/commit/832402097e77794095c3b59be9ea60bbaa4ce0f3
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M lldb/source/Symbol/Type.cpp
M lldb/test/API/python_api/type/TestTypeList.py
M lldb/test/API/python_api/type/main.cpp
Log Message:
-----------
[lldb] Make SBType::FindDirectNestedType work with dynamic types (#207743)
This makes it possible to find the nested type just by knowing the
dynamic type of the value. To get the previous behavior, get the type
from a static view of the value (SBValue::GetStaticValue).
Commit: d6c521c5642e66c02bb6776f811d93b7c320537d
https://github.com/llvm/llvm-project/commit/d6c521c5642e66c02bb6776f811d93b7c320537d
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
A utils/bazel/llvm-project-overlay/libc/test/src/arpa/inet/BUILD.bazel
Log Message:
-----------
[bazel][libc] Add htons function family and tests (#208201)
Add bazel build targets for the arpa/inet byte order functions (htonl,
htons, ntohl, ntohs) and their corresponding unittests.
Assisted by Gemini.
Commit: e795686d2eb7fbee7e594451b46687a3c8d1f575
https://github.com/llvm/llvm-project/commit/e795686d2eb7fbee7e594451b46687a3c8d1f575
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/FIRToMemRef.cpp
A flang/test/Transforms/FIRToMemRef/emboxed-slice-array-coor.mlir
A flang/test/Transforms/FIRToMemRef/emboxed-slice-non-unit-stride-non-unit-lb.mlir
A flang/test/Transforms/FIRToMemRef/emboxed-slice-rank-reduction-nonprefix.mlir
A flang/test/Transforms/FIRToMemRef/emboxed-slice-rank-reduction.mlir
A flang/test/Transforms/FIRToMemRef/emboxed-slice-stride.mlir
Log Message:
-----------
[FIRToMemRef] Fix wrong indexing for converted array_coor over sliced fir.embox (#207749)
FIRToMemRef::convertArrayCoorOp routes through getMemrefIndices, which
only folds the first `rank` triples of sliceInfo.sliceVec into the
memref indices (i.e. the array_coor's own slice); the embox's slice
triples -- which sit at [rank*3 .. 2*rank*3-1] when both are present --
were dropped. Three consequences, three fixes here:
1. Non-collapsed embox slice lbs contribute (lb - 1) per Fortran dim to
each memref index. Fold them in in memref order (reversed Fortran order)
so the reinterpret_cast view lands at the right column.
2. The shapeVec-else stride path used shapeVec[0..rank-1] to build the
outer strides. With both slices present, that's the box's (slice's)
extents. Use shapeVec[rank..2*rank-1] instead -- the parent's extents --
so the outer stride is the parent's leading dim rather than the slice's
own size.
3. Rank-reducing embox slices (undef ub/step triples) have no memref
index position for their (lb - 1) shift. Fold the collapsed dim's (lb -
1) * parent_stride into the reinterpret_cast's flat offset and override
the corresponding memref index entry to 0.
---------
Co-authored-by: Claude Opus 4.7 <noreply at anthropic.com>
Commit: 8fd8daebd18a4d4ccd74942b44f3322a3c52c001
https://github.com/llvm/llvm-project/commit/8fd8daebd18a4d4ccd74942b44f3322a3c52c001
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
A llvm/test/CodeGen/AArch64/expand-form-transposed-tuple.mir
A llvm/test/CodeGen/AArch64/misched-push-form-transposed-tuple-to-users.mir
M llvm/test/CodeGen/AArch64/sme2-multivec-regalloc.mir
Log Message:
-----------
[AArch64] Expand FORM_TRANSPOSED_REG_TUPLE to copies before regalloc (#207205)
Previously, we kept the FORM_TRANSPOSED_REG_TUPLE nodes around during
register allocation. The problem with this approach is that it does not
model the potential overlap in live ranges between the destination and
source operands.
As a result, the register allocator assumes it has complete freedom to
allocate registers to the operands. For example, there is nothing
stopping it from allocating:
```
{z0, z1, z2, z3} = FORM_TRANSPOSED_X4 z3, z2, z1, z0
```
However, such cases are hard to expand later, either requiring spills or
complex shuffles. The current expansions of FORM_TRANSPOSED_REG_TUPLE
miscompile in cases like this because, when naively expanded into copies
after register allocation, earlier copies can clobber values that are
still needed by later ones.
For the above case, the incorrect expansion would be:
```
z0 = COPY z3 // z0 clobbered
z1 = COPY z2 // z1 clobbered
z2 = COPY z1 // reads the wrong value of z1
z3 = COPY z0 // reads the wrong value of z0
```
This patch fixes the issue by expanding FORM_TRANSPOSED_REG_TUPLEs into
copy sequences immediately before register allocation (in
`aarch64-post-coalescer`).
For example:
```
%v4:zpr4mul4 = FORM_TRANSPOSED_X4 %v0:0, %v1:0, %v2:0, %v3:0
```
Expands to:
```
undef %v4.zsub0:zpr4mul4 = COPY_INTO_TRANSPOSED_TUPLE %v0:0
%v4.zsub1:zpr4mul4 = COPY_INTO_TRANSPOSED_TUPLE %v1:0
%v4.zsub2:zpr4mul4 = COPY_INTO_TRANSPOSED_TUPLE %v2:0
%v4.zsub3:zpr4mul4 = COPY_INTO_TRANSPOSED_TUPLE %v3:0
```
This is similar to how REG_SEQUENCE is expanded and allows the register
allocator to reason about how the copies may interfere with one another.
To ensure our register allocation hints still apply, we encourage the
scheduler to place FORM_TRANSPOSED_REG_TUPLE nodes immediately before
their users. This keeps the live ranges of the hint nodes
(COPY_INTO_TRANSPOSED_TUPLE) short while extending the live ranges of
their operands. As a result, the register allocator is more likely to
allocate registers to the copy sources first, which works best for our
allocation hints.
Commit: 7f31e0c7e67bd05918cb60af978edacb231d52fb
https://github.com/llvm/llvm-project/commit/7f31e0c7e67bd05918cb60af978edacb231d52fb
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M orc-rt/test/CMakeLists.txt
R orc-rt/test/init.test
R orc-rt/test/lit.cfg.py
R orc-rt/test/lit.site.cfg.py.in
A orc-rt/test/regression/init.test
A orc-rt/test/regression/lit.cfg.py
A orc-rt/test/regression/lit.site.cfg.py.in
Log Message:
-----------
[orc-rt] Move the regression tests into test/regression (#208391)
Move the regression lit config and the existing tests into
test/regression/, and point the check-orc-rt suite there.
This is a first step towards consolidating tests and test infrastructure
under orc-rt/test. Upcoming commits will add a test tools directory, and
move the existing unit tests (under orc-rt/unittests) into
orc-rt/test/unit.
Commit: a443951eb3717c27149ba491cc8ba632c1a2da5e
https://github.com/llvm/llvm-project/commit/a443951eb3717c27149ba491cc8ba632c1a2da5e
Author: Fangrui Song <i at maskray.me>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/include/llvm/Support/GenericLoopInfo.h
M llvm/include/llvm/Support/GenericLoopInfoImpl.h
Log Message:
-----------
Require GraphHasNodeNumbers in llvm::LoopInfoBase; drop the DenseMap fallback (#207905)
LoopInfoBase kept a DenseMap fallback for block types whose GraphTraits
has no getNumber() (std::conditional_t on GraphHasNodeNumbers). With the
last such in-tree users now numbered (mlir::Block #207617 and BOLT's
BinaryBasicBlock #207899), require GraphHasNodeNumbers via static_assert
and make BBMap unconditionally a SmallVector indexed by block number,
dropping the DenseMap branch in
getLoopFor/changeLoopFor/removeBlock/analyze/verify.
Aided by Claude Opus 4.8
Commit: b94defea8ba4194a5ade1657c38c2b218981ab1e
https://github.com/llvm/llvm-project/commit/b94defea8ba4194a5ade1657c38c2b218981ab1e
Author: Ömer Sinan Ağacan <omeragacan at gmail.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/fast-isel-int-ext.ll
Log Message:
-----------
[AArch64][FastISel] Update arm64-fast-isel-int-ext.ll check lines (NFC) (#207996)
Similar to #207159 (merged as 15b3882), update the CHECK lines
automatically in prep for new tests and bug fixes.
Commit: 6ae5965f26e53d7338a779a73725a597a4d136e5
https://github.com/llvm/llvm-project/commit/6ae5965f26e53d7338a779a73725a597a4d136e5
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/PassManagerInternal.h
Log Message:
-----------
Revert "[IR][NFC] Drop vtable from PassConcept/PassModel" (#208389)
Breaks ASan builds due to new-delete mismatch.
Closes #208381.
Reverts llvm/llvm-project#208168
Commit: c378bc38dde2a30f04e0aac0d053cea620800a99
https://github.com/llvm/llvm-project/commit/c378bc38dde2a30f04e0aac0d053cea620800a99
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/include/llvm/ObjectYAML/ContiguousBlobAccumulator.h
M llvm/lib/ObjectYAML/ContiguousBlobAccumulator.cpp
Log Message:
-----------
[ObjectYAML] Fix issues found in review of #207306 (#208160)
- checkLimit(): avoid uint64_t overflow.
- writeAsBinary(): check the limit against the bytes actually written.
- updateDataAt(): take const void *Data.
Commit: f22e7b5a6f9b2fcc968bda860253e3b4b363aada
https://github.com/llvm/llvm-project/commit/f22e7b5a6f9b2fcc968bda860253e3b4b363aada
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/include/llvm/DWARFLinker/Classic/DWARFLinkerCompileUnit.h
M llvm/lib/DWARFLinker/Classic/DWARFLinkerCompileUnit.cpp
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.cpp
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.cpp
A llvm/test/tools/dsymutil/X86/dwarf6-language-name-odr.test
Log Message:
-----------
[dsymutil] Use DWARFDie::getLanguage instead of manually finding DW_AT_language (#208174)
With DWARFv6, CUs may not have a `DW_AT_language` (but a
`DW_AT_language_name` instead). In
https://github.com/llvm/llvm-project/pull/207151 we made
`DWARFDie::getLanguage` account for this possibility. However, dsymutil
explicitly tries to find `DW_AT_language` in several places.
This patch ensures we go through `DWARFDie::getLanguage` instead in most
of them.
The only way I found this to be testable/observable is by testing the
`isODRLanguage` code paths. Added a test that exercises this.
There is one remaining use of `DW_AT_language` in
`DependencyTracker.cpp`. But was going to address that in a separate
change.
AI usage:
- Test written with the help of Claude
Commit: 9c747b3ed9116841c48913eb06ccb5fad13ad1a7
https://github.com/llvm/llvm-project/commit/9c747b3ed9116841c48913eb06ccb5fad13ad1a7
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M clang/lib/Serialization/ASTReaderDecl.cpp
A clang/test/Modules/GH207581.cpp
Log Message:
-----------
[clang] [serialization] Step into UsingShadowDecl when find existing decl (#208393)
Close https://github.com/llvm/llvm-project/issues/207581
The root cause of the problem is that：enum constant decl, for which its
parent is not enum class, is special. They can be accessed directly
without access its parent. When modules join the game, it becomes more
complex. As for members in other entities like class, we can assume the
member is accessable if their parent are accesable. But it is a
different story for enums. See
https://github.com/llvm/llvm-project/issues/131058 for the whole story
of the backrgound.
Then we didn't write enum constant decl to the lookup table of its
parent of parent in the ASTWriter. So that if other consumer in Sema
wants to access them, they have to get it by entities like exported
using decls. However, the problem is, in ASTReader, when we merge decls,
we use noload_lookup to find existing decls. And the absense of unnamed
enum decl in the parent of its parent's lookup table makes the merge
fails. For enum constant decl in named enum, they will still have a name
lookup table. So we will merge them somehow. But for enum constants in
unnamed enum, they were removed from the only lookup table so the merge
fails. This is the whole story of the current issue.
To fix this, when we merge decls, we step into the UsingShadowDecl to
find the real decls. This is fine as we never merge decls with different
kinds. We can even call this a tiny optimization.
Commit: d7ccd02c9c78b6576ca2caa3f4d2435ebda50744
https://github.com/llvm/llvm-project/commit/d7ccd02c9c78b6576ca2caa3f4d2435ebda50744
Author: Osama Abdelkader <osama.abdelkader at gmail.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/DeclSpec.h
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Sema/DeclSpec.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.stc/p2.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p3-1y.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p3-generic-lambda-1y.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p3.cpp
M clang/test/CXX/dcl/dcl.fct/p17.cpp
M clang/test/CXX/drs/cwg3xx.cpp
M clang/test/Parser/c2x-auto.c
M clang/test/SemaCXX/auto-cxx0x.cpp
M clang/test/SemaCXX/class.cpp
M clang/test/SemaCXX/static-data-member.cpp
Log Message:
-----------
[clang] Reject 'auto' storage class with type specifier in C++ (#166004)
Fixes #164273
---------
Signed-off-by: Osama Abdelkader <osama.abdelkader at gmail.com>
Commit: f6b50ceeca020729445239b5375343e909d3dc51
https://github.com/llvm/llvm-project/commit/f6b50ceeca020729445239b5375343e909d3dc51
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M libcxx/include/__vector/layout.h
M libcxx/include/__vector/vector.h
Log Message:
-----------
[libc++] Remove some unnecessary functions from __vector_layout (#207152)
This removes functions which produce identical IR after the first
InstCombine pass after inlining compared to their replacements.
Commit: e0dce75190a862b3bcfdcd165ea794fa77412b58
https://github.com/llvm/llvm-project/commit/e0dce75190a862b3bcfdcd165ea794fa77412b58
Author: Tomas Matheson <Tomas.Matheson at arm.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-lse2.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-lse2_lse128.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc3.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-load-lse2.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-load-lse2_lse128.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-load-rcpc3.ll
M llvm/test/CodeGen/AArch64/Atomics/generate-tests.py
M llvm/test/CodeGen/AArch64/GlobalISel/v8.4-atomic-128.ll
M llvm/test/CodeGen/AArch64/v8.4-atomic-128.ll
Log Message:
-----------
[AArch64] fix 128-bit Sequentially Consistent load (#206936)
Emit 128-bit SC loads the way that the AArch64 atomics ABI requires, by
introducing an LDAR before the LDP. See atomicsabi64.pdf at
https://github.com/ARM-software/abi-aa/releases.
Commit: d0487fec8ee5ca05645dfc69093b49959cf51dbc
https://github.com/llvm/llvm-project/commit/d0487fec8ee5ca05645dfc69093b49959cf51dbc
Author: Stefan Gränitz <stefan.graenitz at gmail.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/include/llvm/Debuginfod/BuildIDFetcher.h
M llvm/include/llvm/Object/BuildID.h
M llvm/lib/DebugInfo/Symbolize/Symbolize.cpp
M llvm/lib/Debuginfod/BuildIDFetcher.cpp
M llvm/lib/Object/BuildID.cpp
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
M llvm/lib/ProfileData/InstrProfCorrelator.cpp
M llvm/tools/llvm-debuginfod-find/llvm-debuginfod-find.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
Log Message:
-----------
Reland [llvm] Errorize DebuginfodFetcher for inspection at call-sites (#194872)
Failure to fetch debuginfod is rarely an error, but there are case where
we want to distinguish error reasons down the line, for example in order
to test connection timeouts.
Commit: 3282c06fc30e742ae230fd5341d9c06103e671fd
https://github.com/llvm/llvm-project/commit/3282c06fc30e742ae230fd5341d9c06103e671fd
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/test/CodeGen/X86/udiv-const-optimization.ll
Log Message:
-----------
[X86] udiv-const-optimization.ll - regenerate test checks (#208403)
Remove noise from #207634
Commit: 12e54164e7a7cdd4596667ebe11f76dbdaccdb56
https://github.com/llvm/llvm-project/commit/12e54164e7a7cdd4596667ebe11f76dbdaccdb56
Author: Philipp Rados <philipp.rados at openchip.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
M llvm/test/CodeGen/RISCV/stack-offset-large.ll
Log Message:
-----------
[RISCV] Adjust max stack-threshold on 64bit systems (#208223)
Shouldn't emit [-Wframe-larger-than] warning on 64-bit systems, when
stack-size is greater than UINT32_MAX (the previous default). Update the
maximum stack-size-threshold on 64-bit systems to INT64_MAX.
NOTE: GCC has both rv32/rv64 thresholds set to the respective signed
maximum unlike LLVM.
Commit: 75c9ff22df22ed1cf98a1badde790a620998c11a
https://github.com/llvm/llvm-project/commit/75c9ff22df22ed1cf98a1badde790a620998c11a
Author: Mel Chen <mel.chen at sifive.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/versioning-dead-load.ll
Log Message:
-----------
[LV] Add test for interleave group with dead member under stride versioning. nfc (#208190)
Co-authored-by: Luke Lau <luke at igalia.com>
Commit: 6c2f267a209a0b4bd0447c589a855c9334fd598c
https://github.com/llvm/llvm-project/commit/6c2f267a209a0b4bd0447c589a855c9334fd598c
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
M llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.ll
M llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.mir
Log Message:
-----------
[AArch64] Add missing TB(N)Z achors to arith+CBZ clustering (#207725)
This patch adds missing TBZ+TBNZ anchors for arith+CBZ clustering. They
have similar nature to CBZ as specific kinds of it, so this patch
classifies them under the same subtarget feature name compactly. This is
better for Apple CPU. They can be reasonably expected to behave
similarly on AArch64 targets.
Commit: 4452323fef2ef4735df6c0f2bdfed0a668df25f2
https://github.com/llvm/llvm-project/commit/4452323fef2ef4735df6c0f2bdfed0a668df25f2
Author: Michael Platings <michael.platings at arm.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Gate NVPTXCodeGen behind llvm_targets (#208041)
Fixes another case of issue #63135
Commit: 170a479b64ef5837c760b640d04a91ebc950d265
https://github.com/llvm/llvm-project/commit/170a479b64ef5837c760b640d04a91ebc950d265
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M clang/include/clang/Options/FlangOptions.td
M clang/lib/Driver/ToolChains/Flang.cpp
M flang/include/flang/Frontend/CodeGenOptions.def
M flang/include/flang/Lower/LoweringOptions.def
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/Bridge.cpp
M flang/test/Driver/driver-help.f90
A flang/test/Driver/real-sum-reassociation.f90
M flang/test/Lower/split-sum-expression-tree-lowering.f90
Log Message:
-----------
[flang][Driver] Add option for real sum reassociation (#207377)
Compiler driver option for #207371: -freal-sum-reassociation.
Disabled by default.
Assisted-by: Codex
Commit: d85e8e7b7744e587d46231f782d44ccfb30f3723
https://github.com/llvm/llvm-project/commit/d85e8e7b7744e587d46231f782d44ccfb30f3723
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
M llvm/test/Transforms/LoopVectorize/vscale-cost.ll
Log Message:
-----------
[VPlan] Add VPInstruction::Intrinsic opcode, use for scalar intrinsics. (#207541)
This patch adds a new Intrinsic opcode to VPInstruction, initially used
for generating calls to scalar intrinsics. The intrinsic ID as integer
is the last operand (i.e. the called function). Alternatively we could
also create the needed intrinsic declarations and pass the function
directly, but that would add potentially unused declarations, if we
decide to not vectorize.
The first patch migrates just VScale, but there are other opcodes
matching directly to intrinsics, which will be replaced in follow ups.
It also gives more flexibility going forward, e.g. allows emitting
min/max intrinsics when expanding SCEV min/max expressions.
PR: https://github.com/llvm/llvm-project/pull/207541
Commit: 3fe9d5d6d3d1a9bcec7959aa0cac7a6fe6808744
https://github.com/llvm/llvm-project/commit/3fe9d5d6d3d1a9bcec7959aa0cac7a6fe6808744
Author: MITSUNARI Shigeo <herumi at nifty.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/AArch64/udiv-const-optimization.ll
M llvm/test/CodeGen/RISCV/udiv-const-optimization.ll
M llvm/test/CodeGen/X86/divide-by-constant.ll
M llvm/test/CodeGen/X86/udiv-const-optimization.ll
Log Message:
-----------
[SelectionDAG] Widen even 33-bit-magic udiv on free-zext targets (#207634)
On 64-bit targets, #181288 lowers a 32-bit unsigned division by a
constant with a 33-bit magic number (the `IsAdd` case) to a widened
64-bit high-multiply (`MULHU`/`UMUL_LOHI`), e.g. `x / 7` becomes a
single `mulq`/`umulh`/`mulhu`. That only reaches odd divisors. This
patch extends it to even divisors on targets where the `i32 -> i64`
zero-extension is free.
Commit: 38570cae05860a5addf29f236faa273b99baffe3
https://github.com/llvm/llvm-project/commit/38570cae05860a5addf29f236faa273b99baffe3
Author: Varad Rahul Kamthe <133588066+varadk27 at users.noreply.github.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
M llvm/test/CodeGen/NVPTX/tanhf.ll
Log Message:
-----------
[NVPTX] Add native `tanh.approx` support for f16/f16x2/bf16/bf16x2 (#203257)
Adds NVPTX backend support for the native PTX `tanh.approx` instructions on half-precision and bfloat types:
- `tanh.approx.f16` and `tanh.approx.f16x2` (PTX 7.0+, sm_75+)
- `tanh.approx.bf16` and `tanh.approx.bf16x2` (PTX 7.8+, sm_90+)
Adds a `FTANHInst` TableGen class with the new patterns in NVPTXInstrInfo.td and splits `ISD::FTANH` out of the unconditional `f16/bf16 -> f32` promotion loop in NVPTXISelLowering.cpp, marking it Legal when the target supports it (scalars promote, vectors expand on older targets). Also guards `tanh.approx.f32` behind sm_75 and adds the
missing `AddPromotedToType` for bf16.
PTX Spec Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-tanh
Signed-off-by: Varad Rahul Kamthe <vkamthe at nvidia.com>
Commit: 1f55374f8d05bda4844a192848368a84e976a8ec
https://github.com/llvm/llvm-project/commit/1f55374f8d05bda4844a192848368a84e976a8ec
Author: Lucas Mellone <github.snugness349 at passinbox.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M libcxx/include/__ranges/lazy_split_view.h
A libcxx/test/libcxx/ranges/range.adaptors/range.lazy.split/nodiscard.verify.cpp
Log Message:
-----------
[libc++][ranges] Applied [[nodiscard]] to `lazy_split` (#208036)
[[nodiscard]] should be applied to functions where discarding the return
value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html
- https://wg21.link/range.lazy.split
Towards https://github.com/llvm/llvm-project/issues/172124
---------
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Commit: 4500116810d69622da80469993ca4d1e2e9ae2c8
https://github.com/llvm/llvm-project/commit/4500116810d69622da80469993ca4d1e2e9ae2c8
Author: michaelselehov <michael.selehov at amd.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/Object/OffloadBundle.cpp
M llvm/test/tools/llvm-objdump/Offloading/fatbin-coff-compress.test
Log Message:
-----------
[Offload] Make compressed offload bundle header little-endian (#206744)
The compressed offload bundle (CCOB) header integer fields (Version,
Method, FileSize, UncompressedFileSize, Hash) were serialized and read
in
host-native byte order. The on-disk format is little-endian, so on
big-endian hosts these fields were byte-swapped: writing produced a
malformed header, and reading misparsed the size, making
`llvm-objdump --offloading` crash/misbehave on s390x. This is also why
the
earlier bundle-size fix had to be reverted.
Make the header little-endian on every host:
- Read side: declare the `RawCompressedBundleHeader` fields as
`support::ulittle16_t` / `ulittle32_t` / `ulittle64_t`, so the bytes are
always interpreted as little-endian regardless of host.
- Write side: emit the header with
`support::endian::Writer(OS, endianness::little)` instead of host-native
`OS.write(&field, sizeof field)`.
Also revert the temporary big-endian test skip added in #205999
(host-byteorder-little-endian guard on fatbin-coff-compress.test): with
the
header now little-endian, the test runs correctly on big-endian hosts.
---------
Co-authored-by: Michael Selehov <michael.selehov at amd.com>
Co-authored-by: Nikita Popov <npopov at redhat.com> (LE approach)
Commit: 095e9a16eaf0982208006138a2f03ec0a540d73e
https://github.com/llvm/llvm-project/commit/095e9a16eaf0982208006138a2f03ec0a540d73e
Author: Avi Patel <aviipatel06 at gmail.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M libcxx/docs/Status/Cxx26Issues.csv
M libcxx/include/__atomic/atomic_ref.h
M libcxx/test/std/atomics/atomics.ref/ctor.pass.cpp
Log Message:
-----------
[libc++] Implement LWG4472: std::atomic_ref<const T> can be constructed from temporaries (#208131)
## Summary
- Implements LWG4472, i.e., adds a deleted `atomic_ref(T&&)` overload to
the primary template and three partial specializations of `atomic_ref`.
## Test
- Added `static_assert`s in `ctor.pass.cpp` asserting
`atomic_ref<T>`/`atomic_ref<const T>` reject construction from
`T&&`/`const T&&`.
Resolve #189840
Commit: 361720cfd50e9610dbceca75c31f28e20b45d7e1
https://github.com/llvm/llvm-project/commit/361720cfd50e9610dbceca75c31f28e20b45d7e1
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Eliminate some vec temps with ArrayRef (NFC) (#207432)
The enabling change is e56187575 ([ArrayRef] Make iterator_range
constructor const-agnostic, #205183).
Commit: 015162dacdd5f0752cea50fc400d454a15b6afbe
https://github.com/llvm/llvm-project/commit/015162dacdd5f0752cea50fc400d454a15b6afbe
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M flang/lib/Optimizer/OpenMP/HostOpFiltering.cpp
M flang/test/Transforms/OpenMP/function-filtering-host-ops.mlir
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/omptarget-declare-target-all-device-types-device.mlir
M mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-device.mlir
Log Message:
-----------
[Flang][MLIR][OpenMP] Fix declare_target globals visibility (#208188)
This patch introduces various changes to the handling of
`declare_target` global variables in Flang:
- Non-`declare_target` globals are unconditionally made "internal" when
compiling for an OpenMP offload target. This prevents potential symbol
redefinition issues related to globals that don't actually exist on the
device.
- Local SAVE variables handling for OpenMP offloading programs is fixed
to prevent their associated "internal" linkage from producing broken
device code for `declare_target enter(...)`.
- When globals are indirectly accessed from the target device (e.g.
`declare_target link(...)`), the associated and unused full-storage
global is marked with "internal" linkage to facilitate later removal.
- `declare_target device_type(host) enter(...)` variables are set to
external linkage when compiling for a target device, causing linker
errors if accessed. This mirrors Clang's behavior.
Fixes #195188, fixes #195468.
Assisted-by: Claude Opus 4.8.
Commit: 50d186480ee9b0fa3f2500c4b963a47ee78db902
https://github.com/llvm/llvm-project/commit/50d186480ee9b0fa3f2500c4b963a47ee78db902
Author: Scott Manley <rscottmanley at gmail.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/ACCRecipeMaterialization.cpp
M mlir/test/Dialect/OpenACC/acc-recipe-materialization-reduction.mlir
Log Message:
-----------
[OpenACC] apply par dims to reductions in parallel regions (#208258)
For reductions that come from parallel constructs, explicitly set the
GPU parallel dimensions attribute to blockXDim on the acc.reduction_init
and acc.reduction_combine* ops since they will always be gang private
Commit: 5b9fa24dbd7b504b99143ebd2f5f12f8560c6331
https://github.com/llvm/llvm-project/commit/5b9fa24dbd7b504b99143ebd2f5f12f8560c6331
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M flang/include/flang/Optimizer/OpenMP/Passes.td
M flang/lib/Optimizer/OpenMP/CMakeLists.txt
M flang/lib/Optimizer/OpenMP/FunctionFiltering.cpp
R flang/lib/Optimizer/OpenMP/HostOpFiltering.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/test/Fir/basic-program.fir
A flang/test/Lower/OpenMP/function-filtering-4.f90
M flang/test/Lower/OpenMP/host-eval.f90
R flang/test/Transforms/OpenMP/function-filtering-host-ops.mlir
M mlir/include/mlir/Dialect/OpenMP/Transforms/Passes.td
M mlir/lib/Dialect/OpenMP/Transforms/CMakeLists.txt
A mlir/lib/Dialect/OpenMP/Transforms/HostOpFiltering.cpp
A mlir/test/Dialect/OpenMP/host-op-filtering.mlir
Log Message:
-----------
[Flang][MLIR][OpenMP] Move host op filtering to the omp dialect (#208189)
The MLIR pass that removes operations exclusively intended for the host
from OpenMP target offload modules is currently defined as part of
Flang. However, this is a feature that would benefit from being reusable
by other frontends, as removing such operations is a requirement for all
OpenMP target device modules prior to LLVM IR translation.
By moving the `omp-host-op-filtering` pass out of Flang, it had to be
updated to work on a lower-level LLVM dialect-based representation,
rather than FIR. This simplified some of the existing edge cases, such
as `fir.declare` ops and `fir.boxchar` type handling. In addition, new
function arguments are introduced as placeholders and return values from
host-only functions are removed, producing a cleaner result and
simplifying the pass as compared to previously.
As a result of a later execution of this pass, dynamic dispatch of host
functions via dispatch table using `fir.dispatch`, `fir.type_info` and
`fir.dt_entry` ops would break due to the removal of `fir.dt_entry`
operations pointing to deleted host functions, while `fir.dispatch` ops
pointing to the same functions would remain. The
`omp-function-filtering` pass is updated to prevent `fir.dt_entry` from
being deleted and let them point to an undefined symbol. This lets FIR
lowering to LLVM work well enough to get to the host op filtering stage,
where any resulting operations for this host dynamic dispatch are
cleaned up.
Commit: 841e01daa0126941cd3b1b322b3e3b5605fcd03c
https://github.com/llvm/llvm-project/commit/841e01daa0126941cd3b1b322b3e3b5605fcd03c
Author: Ammar Askar <aaskar at google.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/test/CodeGen/X86/insert.ll
Log Message:
-----------
[ISEL] Fix x86-64 instruction selection bug leaking upper 32 bits (#205600)
The x86 backend had optimization patterns that matched:
`(or (and GR32:$dst, -256), (i32 (zextloadi8 addr:$src)))`
and lowered it to:
`(INSERT_SUBREG (i32 (COPY $dst)), (MOV8rm i8mem:$src), sub_8bit)`
INSERT_SUBREG for sub_8bit emits a movb instruction which preserves the
upper 56 bits. Now, if the GR32 dst came from a node that does not zero
the upper 32 bits (like IMPLICIT_DEF or EXTRACT_SUBREG), those upper 32
bits would be leaked into the resulting register without being zeroed.
This fixes it by ensuring the input operand satisfies def32 which
requires the upper 32 bits of the register to be set.
Commit: eceb9d55a2c526798480a1ceb8dfedb85b5b6c9b
https://github.com/llvm/llvm-project/commit/eceb9d55a2c526798480a1ceb8dfedb85b5b6c9b
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M orc-rt/test/CMakeLists.txt
M orc-rt/test/regression/lit.cfg.py
A orc-rt/test/regression/smoke-check.test
A orc-rt/test/tools/CMakeLists.txt
A orc-rt/test/tools/orc-rt-smoke-check.cpp
Log Message:
-----------
[orc-rt] Add regression test-tool infrastructure (#208398)
Set up the infrastructure for regression tests that build and run a
helper tool, in preparation for testing the logging backends.
- Add test/tools/ for test-support binaries, with a first tool,
orc-rt-smoke-check, wired into ORC_RT_TEST_DEPS and onto lit's PATH.
- Add test/regression/smoke-check.test, which runs the tool and matches
its output with FileCheck, exercising the tool-build and lit plumbing
end to end.
Commit: 724ad1150d5d38c96ac9d848ea21cad165415bd7
https://github.com/llvm/llvm-project/commit/724ad1150d5d38c96ac9d848ea21cad165415bd7
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/include/llvm/MC/MCDXContainerWriter.h
M llvm/lib/MC/MCDXContainerWriter.cpp
M llvm/lib/Target/DirectX/DXContainerGlobals.cpp
M llvm/lib/Target/DirectX/DXContainerPDB.cpp
M llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
A llvm/test/CodeGen/DirectX/ContainerData/ContainerFlags.ll
M llvm/test/CodeGen/DirectX/ContainerData/DebugName-default-output.test
M llvm/test/CodeGen/DirectX/ContainerData/DebugName-user-directory.test
A llvm/test/CodeGen/DirectX/ContainerData/DebugName-user-specified.test
A llvm/test/CodeGen/DirectX/ContainerData/DebugName.test
M llvm/test/CodeGen/DirectX/ContainerData/PDBParts.test
M llvm/test/CodeGen/DirectX/ContainerData/SourceInfo-Args.ll
M llvm/test/CodeGen/DirectX/ContainerData/SourceInfo-Compressed.ll
M llvm/test/CodeGen/DirectX/ContainerData/SourceInfo-Uncompressed.ll
M llvm/test/CodeGen/DirectX/embed-ildb.ll
Log Message:
-----------
[DirectX] Add `--dx-embed-debug` and `--dx-pdb-path` flags (#204166)
Add flags for DirectX in `llc`:
* `--dx-embed-debug` to embed debug info into ILDB part of DXContainer
* `--dx-pdb-path` to specify filename/path for PDB file output
This patch does not add flags for clang Driver, they will be implemented
later.
Commit: d855251d603623f790cf94079126ad8ab6684d9d
https://github.com/llvm/llvm-project/commit/d855251d603623f790cf94079126ad8ab6684d9d
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M orc-rt/CMakeLists.txt
M orc-rt/test/CMakeLists.txt
A orc-rt/test/unit/AllocActionTest.cpp
A orc-rt/test/unit/AllocActionTestUtils.h
A orc-rt/test/unit/BitmaskEnumTest.cpp
A orc-rt/test/unit/BootstrapInfoTest.cpp
A orc-rt/test/unit/CMakeLists.txt
A orc-rt/test/unit/CallSPSCITest.cpp
A orc-rt/test/unit/CallableTraitsHelperTest.cpp
A orc-rt/test/unit/CommonTestUtils.h
A orc-rt/test/unit/DirectCaller.h
A orc-rt/test/unit/EndianTest.cpp
A orc-rt/test/unit/ErrorCAPITest.cpp
A orc-rt/test/unit/ErrorExceptionInteropTest.cpp
A orc-rt/test/unit/ErrorTest.cpp
A orc-rt/test/unit/ExecutorAddressTest.cpp
A orc-rt/test/unit/ExecutorProcessInfoTest.cpp
A orc-rt/test/unit/InProcessControllerAccessTest.cpp
A orc-rt/test/unit/Inputs/NativeDylibManagerTestLib.cpp
A orc-rt/test/unit/IntervalMapTest.cpp
A orc-rt/test/unit/IntervalSetTest.cpp
A orc-rt/test/unit/LockedAccessTest.cpp
A orc-rt/test/unit/LoggingTest.cpp
A orc-rt/test/unit/MacroUtilsTest.cpp
A orc-rt/test/unit/MathTest.cpp
A orc-rt/test/unit/MemoryAccessSPSCITest.cpp
A orc-rt/test/unit/MemoryFlagsTest.cpp
A orc-rt/test/unit/NativeDylibManagerSPSCITest.cpp
A orc-rt/test/unit/NativeDylibManagerTest.cpp
A orc-rt/test/unit/QueueingRunnerTest.cpp
A orc-rt/test/unit/RTTITest.cpp
A orc-rt/test/unit/SPSAllocActionTest.cpp
A orc-rt/test/unit/SPSMemoryFlagsTest.cpp
A orc-rt/test/unit/SPSWrapperFunctionBufferTest.cpp
A orc-rt/test/unit/SPSWrapperFunctionTest.cpp
A orc-rt/test/unit/SessionTest.cpp
A orc-rt/test/unit/SimpleNativeMemoryMapSPSCITest.cpp
A orc-rt/test/unit/SimpleNativeMemoryMapTest.cpp
A orc-rt/test/unit/SimplePackedSerializationTest.cpp
A orc-rt/test/unit/SimplePackedSerializationTestUtils.h
A orc-rt/test/unit/SimpleSymbolTableTest.cpp
A orc-rt/test/unit/StandaloneMachOUnwindInfoRegistrarTest.cpp
A orc-rt/test/unit/TaskGroupTest.cpp
A orc-rt/test/unit/ThreadPoolRunnerTest.cpp
A orc-rt/test/unit/WrapperFunctionBufferTest.cpp
A orc-rt/test/unit/bind-test.cpp
A orc-rt/test/unit/bit-test.cpp
A orc-rt/test/unit/iterator_range-test.cpp
M orc-rt/test/unit/lit.cfg.py
A orc-rt/test/unit/move_only_function-test.cpp
A orc-rt/test/unit/scope_exit-test.cpp
A orc-rt/test/unit/span-test.cpp
R orc-rt/unittests/AllocActionTest.cpp
R orc-rt/unittests/AllocActionTestUtils.h
R orc-rt/unittests/BitmaskEnumTest.cpp
R orc-rt/unittests/BootstrapInfoTest.cpp
R orc-rt/unittests/CMakeLists.txt
R orc-rt/unittests/CallSPSCITest.cpp
R orc-rt/unittests/CallableTraitsHelperTest.cpp
R orc-rt/unittests/CommonTestUtils.h
R orc-rt/unittests/DirectCaller.h
R orc-rt/unittests/EndianTest.cpp
R orc-rt/unittests/ErrorCAPITest.cpp
R orc-rt/unittests/ErrorExceptionInteropTest.cpp
R orc-rt/unittests/ErrorTest.cpp
R orc-rt/unittests/ExecutorAddressTest.cpp
R orc-rt/unittests/ExecutorProcessInfoTest.cpp
R orc-rt/unittests/InProcessControllerAccessTest.cpp
R orc-rt/unittests/Inputs/NativeDylibManagerTestLib.cpp
R orc-rt/unittests/IntervalMapTest.cpp
R orc-rt/unittests/IntervalSetTest.cpp
R orc-rt/unittests/LockedAccessTest.cpp
R orc-rt/unittests/LoggingTest.cpp
R orc-rt/unittests/MacroUtilsTest.cpp
R orc-rt/unittests/MathTest.cpp
R orc-rt/unittests/MemoryAccessSPSCITest.cpp
R orc-rt/unittests/MemoryFlagsTest.cpp
R orc-rt/unittests/NativeDylibManagerSPSCITest.cpp
R orc-rt/unittests/NativeDylibManagerTest.cpp
R orc-rt/unittests/QueueingRunnerTest.cpp
R orc-rt/unittests/RTTITest.cpp
R orc-rt/unittests/SPSAllocActionTest.cpp
R orc-rt/unittests/SPSMemoryFlagsTest.cpp
R orc-rt/unittests/SPSWrapperFunctionBufferTest.cpp
R orc-rt/unittests/SPSWrapperFunctionTest.cpp
R orc-rt/unittests/SessionTest.cpp
R orc-rt/unittests/SimpleNativeMemoryMapSPSCITest.cpp
R orc-rt/unittests/SimpleNativeMemoryMapTest.cpp
R orc-rt/unittests/SimplePackedSerializationTest.cpp
R orc-rt/unittests/SimplePackedSerializationTestUtils.h
R orc-rt/unittests/SimpleSymbolTableTest.cpp
R orc-rt/unittests/StandaloneMachOUnwindInfoRegistrarTest.cpp
R orc-rt/unittests/TaskGroupTest.cpp
R orc-rt/unittests/ThreadPoolRunnerTest.cpp
R orc-rt/unittests/WrapperFunctionBufferTest.cpp
R orc-rt/unittests/bind-test.cpp
R orc-rt/unittests/bit-test.cpp
R orc-rt/unittests/iterator_range-test.cpp
R orc-rt/unittests/move_only_function-test.cpp
R orc-rt/unittests/scope_exit-test.cpp
R orc-rt/unittests/span-test.cpp
Log Message:
-----------
[orc-rt] Move the unit tests into test/unit (#208431)
Move unit tests from orc-rt/unittests into orc-rt/test/unit, completing
the consolidation of the runtime's tests under orc-rt/test (alongside
test/regression and test/tools).
Commit: 1008b485e4807476c831910cf404a0315f06c788
https://github.com/llvm/llvm-project/commit/1008b485e4807476c831910cf404a0315f06c788
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/cmake/modules/LLVMConfig.cmake.in
Log Message:
-----------
cmake: Remove cmake_crosscompiling check on LLVMSupport target export (#208420)
Revert exported target check added in
00b2f81418233397e601afaeea6d62c47a6c368a
to fix reported mingw cross compile regression. This is the quick fix
which restores the cmake warnings when building libc for amdgpu.
Commit: 05c0a297bcad51642f55e4ba25f408128e88982f
https://github.com/llvm/llvm-project/commit/05c0a297bcad51642f55e4ba25f408128e88982f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/test/CodeGen/X86/subvectorwise-store-of-vector-splat.ll
Log Message:
-----------
[X86] subvectorwise-store-of-vector-splat.ll - regenerate test checks to reduce diff in #189971 (#208419)
Add AVX1ORAVX2 check prefix to distinguish from AVX512 codegen
Commit: 7919d61966d84821d60edc8cf23ebdab8d3eb9d0
https://github.com/llvm/llvm-project/commit/7919d61966d84821d60edc8cf23ebdab8d3eb9d0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/test/CodeGen/X86/sat-add.ll
Log Message:
-----------
[X86] sat-add.ll - regenerate test check to reduce diff in #189971 (#208418)
Commit: 24a5231188bf92e2ce9fe38e29e4cb75bab51414
https://github.com/llvm/llvm-project/commit/24a5231188bf92e2ce9fe38e29e4cb75bab51414
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/lib/Basic/OffloadArch.cpp
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Sema/SemaAMDGPU.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/test/Driver/amdgpu-toolchain.c
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M flang/include/flang/Tools/TargetSetup.h
M flang/lib/Optimizer/CodeGen/Target.cpp
M lld/ELF/InputFiles.cpp
M lldb/source/Utility/ArchSpec.cpp
M lldb/unittests/ObjectFile/ELF/TestObjectFileELF.cpp
M lldb/unittests/Utility/ArchSpecTest.cpp
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/Object/ELFObjectFile.h
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/Frontend/OpenMP/OMPContext.cpp
M llvm/lib/Object/RelocationResolver.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
M llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.h
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/TargetParser/TargetDataLayout.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/IPO/ExpandVariadics.cpp
M llvm/lib/Transforms/IPO/OpenMPOpt.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
A llvm/test/CodeGen/AMDGPU/amdgpu-triple.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch.ll
A llvm/test/CodeGen/AMDGPU/march-amdgcn-legacy-arch-name.ll
A llvm/test/CodeGen/AMDGPU/target-id-from-triple.ll
A llvm/test/CodeGen/AMDGPU/validate-subtarget-subarch-empty-module.ll
A llvm/test/CodeGen/AMDGPU/validate-subtarget-subarch.ll
M llvm/test/CodeGen/MIR/AMDGPU/init-whole.wave.ll
A llvm/test/Linker/Inputs/amdgpu-amdpal-no-subarch.ll
A llvm/test/Linker/Inputs/amdgpu-no-subarch.ll
A llvm/test/Linker/Inputs/amdgpu10-subarch.ll
A llvm/test/Linker/Inputs/amdgpu9.00-subarch.ll
A llvm/test/Linker/amdgpu-triple-os-mismatch.ll
A llvm/test/Linker/amdgpu-triple-subarch.ll
M llvm/test/MC/AMDGPU/amd-amdgpu-isa-malformed-target-id.s
A llvm/test/MC/AMDGPU/amdgcn-target-directive-subarch-cpu-field.s
M llvm/test/MC/AMDGPU/amdgcn-target-malformed-target-id.s
M llvm/test/MC/AMDGPU/amdgcn_target_directive_from_eflags.s
A llvm/test/MC/AMDGPU/arch-amdgcn-legacy-arch-name.s
M llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
M llvm/test/Object/AMDGPU/objdump.s
A llvm/test/tools/llvm-objdump/AMDGPU/arch-amdgcn-legacy-arch-name.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s
A llvm/test/tools/llvm-objdump/ELF/AMDGPU/subarch-triple.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/unittests/Object/ELFObjectFileTest.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/unittests/TargetParser/TripleTest.cpp
M llvm/utils/UpdateTestChecks/asm.py
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
Log Message:
-----------
AMDGPU: Introduce amdgpu triple arch (#206480)
Move towards using the triple for representing incompatible
ISA changes. Use the subarch field to represent the various
incompatible cases. Previously we pretended a single triple arch
was universally compatible, and only distinguished by function
level subtargets. Move towards using distinct triples to enable
more sophisticated toolchain handling in the future, like proper
runtime library linking.
Introduce a new subarch per unique ISA, but also introduce
"major subarches" which are compatible by a set of covered
minor ISA versions. These map to the existing generic targets.
There are a few placeholder subarch entries, which currently
have missing backing generic arches for codegen.
This should be the preferred triple arch name going forward,
but is treated as an alias of amdgcn. This does not yet change
clang to emit the new triples.
Part of #154925
Commit: cfa5d6f59db9c891c1046edcbb8b5a273be0a59c
https://github.com/llvm/llvm-project/commit/cfa5d6f59db9c891c1046edcbb8b5a273be0a59c
Author: Narayan <nsreekumar6 at gmail.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenModule.h
M clang/test/CodeGen/X86/avx512fp16-abi.c
M clang/test/CodeGen/X86/bfloat-half-abi.c
M clang/test/CodeGen/X86/fp128-abi.c
M llvm/include/llvm/ABI/TargetInfo.h
M llvm/include/llvm/ABI/Types.h
M llvm/lib/ABI/CMakeLists.txt
M llvm/lib/ABI/IRTypeMapper.cpp
M llvm/lib/ABI/TargetInfo.cpp
A llvm/lib/ABI/Targets/X86.cpp
M llvm/lib/ABI/Types.cpp
Log Message:
-----------
[LLVMABI] Implement the System V X86-64 ABI (#194718)
This PR implements the System V X86-64 ABI for the LLVM ABI Library
prototyped in https://github.com/llvm/llvm-project/pull/140112, and
wires it into clang's Codegen.
`X86_64TargetInfo` is a direct parallel to
`clang::CodeGen::X86_64ABIInfo`, but operates entirely on the
`llvm::abi` type system.
The AMD64 ABI classification spec, argument/return lowering , and the
supporting helpers are all reproduced against `llvm::abi::Type` and
FunctionInfo, keeping the ABI logic frontend-independent.
This, similar to the [BPF ABI implementaiton
](https://github.com/llvm/llvm-project/pull/194031/changes)is gated
under the `-fexperimental-abi-lowering` flag.
Commit: d2395c4eea4ac363786c7568eabe2a958c7b7c9c
https://github.com/llvm/llvm-project/commit/d2395c4eea4ac363786c7568eabe2a958c7b7c9c
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/DeclSpec.h
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Sema/DeclSpec.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.stc/p2.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p3-1y.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p3-generic-lambda-1y.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p3.cpp
M clang/test/CXX/dcl/dcl.fct/p17.cpp
M clang/test/CXX/drs/cwg3xx.cpp
M clang/test/Parser/c2x-auto.c
M clang/test/SemaCXX/auto-cxx0x.cpp
M clang/test/SemaCXX/class.cpp
M clang/test/SemaCXX/static-data-member.cpp
Log Message:
-----------
Revert "[clang] Reject 'auto' storage class with type specifier in C++" (#208436)
Reverts llvm/llvm-project#166004.
Breaks stage 2 build, see comments on PR.
Commit: 099ffad0a794880b647bd82a28ca4f3f6627dcbd
https://github.com/llvm/llvm-project/commit/099ffad0a794880b647bd82a28ca4f3f6627dcbd
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
R llvm/test/CodeGen/X86/combine-pmadd.ll
A llvm/test/CodeGen/X86/combine-pmaddubsw.ll
A llvm/test/CodeGen/X86/combine-pmaddwd.ll
Log Message:
-----------
[X86] combine-pmadd.ll - split into combine-pmaddwd.ll and combine-pmaddubsw.ll (#208430)
Allows better SSE2 test coverage for PMADDWD combines
Commit: 092f4451cecaf52c14f1be6c8741882f0b3c9de6
https://github.com/llvm/llvm-project/commit/092f4451cecaf52c14f1be6c8741882f0b3c9de6
Author: Hans Wennborg <hans at hanshq.net>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M clang-tools-extra/clang-tidy/misc/DefinitionsInHeadersCheck.cpp
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/refactor/tweaks/DefineInline.cpp
M clang/docs/LibASTMatchersReference.html
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/JSONNodeDumper.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/ASTMatchers/ASTMatchersInternal.h
M clang/include/clang/Basic/Specifiers.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTDumper.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/Comment.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/ASTMatchers/Dynamic/Registry.cpp
M clang/lib/Analysis/ExprMutationAnalyzer.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
M clang/lib/CodeGen/CGVTables.cpp
M clang/lib/Index/IndexingContext.cpp
M clang/lib/InstallAPI/Visitor.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/StaticAnalyzer/Core/BugSuppression.cpp
M clang/lib/Tooling/Syntax/BuildTree.cpp
M clang/test/AST/ast-dump-templates-pattern.cpp
M clang/test/CXX/basic/basic.link/p11.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg7xx.cpp
M clang/test/CXX/temp/temp.arg/temp.arg.template/p3-2a.cpp
M clang/test/CXX/temp/temp.constr/temp.constr.decl/p4.cpp
M clang/test/CXX/temp/temp.decls/temp.spec.partial/temp.spec.partial.member/p2.cpp
M clang/test/CXX/temp/temp.spec/temp.expl.spec/p7.cpp
M clang/test/CodeGenCXX/default-arguments.cpp
M clang/test/CodeGenCXX/explicit-instantiation.cpp
R clang/test/Modules/GH208100.cpp
M clang/test/SemaCXX/GH195416.cpp
M clang/test/SemaCXX/constant-expression-cxx14.cpp
M clang/test/SemaCXX/deduced-return-type-cxx14.cpp
M clang/test/SemaCXX/member-class-11.cpp
R clang/test/SemaTemplate/GH202358.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/test/SemaTemplate/friend-template.cpp
M clang/test/SemaTemplate/instantiate-scope.cpp
M clang/test/Templight/templight-default-func-arg.cpp
M clang/test/Templight/templight-empty-entries-fix.cpp
M clang/tools/libclang/CIndex.cpp
M clang/unittests/AST/ASTImporterTest.cpp
M clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
Log Message:
-----------
Revert "[clang] Reland: fix getTemplateInstantiationArgs (#208285)" (#208426)
It caused various breakages; see comments on the PR.
This reverts commit 031b773b01700acf82f5977a5aa6024621b8211c.
Commit: 274a34579ffd8bdbe57a58768ec199a6a23f0489
https://github.com/llvm/llvm-project/commit/274a34579ffd8bdbe57a58768ec199a6a23f0489
Author: michaelselehov <michael.selehov at amd.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M clang/lib/Driver/OffloadBundler.cpp
A clang/test/Driver/Inputs/clang-offload-bundler-magic-collision.co
A clang/test/Driver/Inputs/clang-offload-bundler-magic-collision.py
A clang/test/Driver/clang-offload-bundler-magic-collision.c
M llvm/lib/Object/OffloadBundle.cpp
A llvm/test/tools/llvm-objdump/Offloading/fatbin-magic-collision.test
Log Message:
-----------
[OffloadBundler] Bound compressed bundles by header size, not magic scan (#206745)
When multiple offload bundles are concatenated, the unbundler
(clang-offload-bundler) and llvm-objdump --offloading located the end of
a compressed bundle, and the start of the next one, by scanning for the
next "CCOB" magic string starting right after the current header.
A zstd/zlib-compressed payload can legally contain those four bytes, so
the scan could stop in the middle of the compressed data and truncate
the bundle, corrupting the embedded code object. In practice this
produced a "decomposition" failure for hipBLASLt bf16 GEMMs on gfx942.
Use the authoritative total-size field recorded in the compressed bundle
header (format V2/V3) to compute the exact bundle boundary, and only
scan for the next magic past that point. Legacy bundles without a
recorded size (V1) keep the previous magic-scan fallback.
A skippable-frame fixture that embeds "CCOB" inside the compressed
payload is added to exercise the boundary logic from both
clang-offload-bundler and llvm-objdump --offloading.
Commit: c138fc9acfdd34ad674c772dc2433402dc3823fe
https://github.com/llvm/llvm-project/commit/c138fc9acfdd34ad674c772dc2433402dc3823fe
Author: Kunal Pathak <kupathak at meta.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/br-cond-merging-loaded-operands.ll
M llvm/test/CodeGen/AArch64/ragreedy-csr.ll
Log Message:
-----------
[AArch64] Don't merge branch conditions that both compare memory loads (#206504)
`shouldKeepJumpConditionsTogether` decides whether to fold two integer
branch conditions into a CMP/CCMP chain by pricing the RHS
dependency-chain latency. That ignores register pressure: when both
conditions compare loaded values, merging pins all the loaded operands
live at once to feed the chain instead of consuming them at each split
compare-and-branch. On a load-store target that extends their live
ranges across the region the branch dominates.
Decline to merge when both sides are integer compares of loaded values,
mirroring the machine CCMP pass (which won't speculate loads).
Reference:
https://github.com/llvm/llvm-project/pull/201486#issuecomment-4812845942
Commit: 73077ed0279054407517083bfe580b7cb40e864d
https://github.com/llvm/llvm-project/commit/73077ed0279054407517083bfe580b7cb40e864d
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M lldb/test/API/commands/platform/connect/TestPlatformConnect.py
Log Message:
-----------
[lldb][Windows] mark TestPlatformProcessConnect as XFAIL (#208445)
https://github.com/llvm/llvm-project/pull/202688 incorrectly marked
`TestPlatformProcessConnect.py` as PASS on Windows with `lldb-server`.
They do not work and are failing just like with the in process plugin.
Re-mark both of them as XFAIL.
rdar://181797532
Commit: c0ddc3c5ce0eab49e1935a413570afd3bc4adfac
https://github.com/llvm/llvm-project/commit/c0ddc3c5ce0eab49e1935a413570afd3bc4adfac
Author: Fred Tingaud <95592999+frederic-tingaud-sonarsource at users.noreply.github.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/include/llvm/Demangle/Demangle.h
M llvm/include/llvm/Demangle/MicrosoftDemangleNodes.h
M llvm/lib/Demangle/MicrosoftDemangle.cpp
M llvm/lib/Demangle/MicrosoftDemangleNodes.cpp
M llvm/unittests/Demangle/CMakeLists.txt
A llvm/unittests/Demangle/MicrosoftDemangleTest.cpp
Log Message:
-----------
[MSVC][Demangling] Make Microsoft demangling more configurable
The goal for us is to be able to demangle Microsoft mangled function
names toward something that reads more like AST function names and
Itanium demangled names. All defaults remain the same and no existing
code or tool user should be impacted by the change.
* Make the OF_NoTagSpecifier flag accessible from `microsoftDemangle`
* Add a flag to skip the "void" keyword when there is no parameter
* Add a flag to skip the type descriptions
* Respect MSDF_NoCallingConvention with function pointers
* Add unit tests.
Assisted-by: Claude
--
CPP-7550
Commit: 061cd69c466ef49dfaafc81d79875cf2f7afa9fa
https://github.com/llvm/llvm-project/commit/061cd69c466ef49dfaafc81d79875cf2f7afa9fa
Author: Ricardo Jesus <rjj at nvidia.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
A clang/test/Driver/aarch64-nvidia-rigel.c
A clang/test/Driver/print-enabled-extensions/aarch64-rigel.c
M clang/test/Misc/target-invalid-cpu-note/aarch64.c
M llvm/lib/Target/AArch64/AArch64Processors.td
M llvm/lib/TargetParser/Host.cpp
M llvm/test/CodeGen/AArch64/cpus.ll
M llvm/unittests/TargetParser/Host.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64] Add initial support for -mcpu=rigel. (#208017)
This patch adds support for the NVIDIA Rigel core.
This does not add any special tuning decisions, and those may come
later.
Commit: 31ef7389463b1121ceecced9d8cf68e0b515bc41
https://github.com/llvm/llvm-project/commit/31ef7389463b1121ceecced9d8cf68e0b515bc41
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SMInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/test/MC/AMDGPU/gfx1250_asm_smem.s
M llvm/test/MC/AMDGPU/gfx1250_asm_smem_err.s
Log Message:
-----------
[AMDGPU][GFX1250] Add cpol support for some prefetch instructions (#208368)
Fixes ROCM-27516.
Commit: 700442d9e4312fad3e42860bb19692fff7c94cd6
https://github.com/llvm/llvm-project/commit/700442d9e4312fad3e42860bb19692fff7c94cd6
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
M llvm/test/Transforms/SLPVectorizer/X86/commutative-copyable-external-phi-use.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-operand-non-scheduled-parent-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
Log Message:
-----------
[SLP]Add AShr as a main opcode for copyables
Added AShr opcode in analysis and minbitwidth analysis
Reviewers: RKSimon, hiraditya, bababuck
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/207841
Commit: 34149b085c630aefe61b0df00a21c691a3421ca5
https://github.com/llvm/llvm-project/commit/34149b085c630aefe61b0df00a21c691a3421ca5
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-09 (Thu, 09 Jul 2026)
Changed paths:
M .github/new-prs-labeler.yml
M .github/workflows/commit-access-greeter.yml
A .github/workflows/libcxx-pr-benchmark.yml
R .github/workflows/libcxx-run-benchmarks.yml
M .github/workflows/test-suite.yml
M .github/workflows/test-suite/x86_64.cmake
M bolt/include/bolt/Core/BinaryBasicBlock.h
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Core/DIEBuilder.cpp
M bolt/lib/Passes/IndirectCallPromotion.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
M bolt/test/AArch64/computed-goto.s
A bolt/test/AArch64/icp-inline.c
A bolt/test/AArch64/icp.c
M bolt/test/AArch64/unsupported-passes.test
M bolt/test/X86/dwarf5-locexpr-addrx.s
M bolt/test/X86/indirect-goto.test
M bolt/test/indirect-goto-relocs.test
M clang-tools-extra/clang-tidy/cppcoreguidelines/RvalueReferenceParamNotMovedCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/RvalueReferenceParamNotMovedCheck.h
M clang-tools-extra/clang-tidy/cppcoreguidelines/SpecialMemberFunctionsCheck.cpp
M clang-tools-extra/clang-tidy/misc/DefinitionsInHeadersCheck.cpp
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/refactor/tweaks/DefineInline.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/rvalue-reference-param-not-moved.rst
A clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/rvalue-reference-param-not-moved-allow-implicit.cpp
A clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/special-member-functions-implicit-delete.cpp
M clang/cmake/modules/ClangConfig.cmake.in
M clang/docs/LibASTMatchersReference.html
M clang/docs/PointerAuthentication.rst
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/JSONNodeDumper.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/StmtVisitor.h
M clang/include/clang/AST/TypeBase.h
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/ASTMatchers/ASTMatchersInternal.h
M clang/include/clang/Basic/ABIVersions.def
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsRISCV.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/Specifiers.h
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Driver/Action.h
M clang/include/clang/Options/FlangOptions.td
M clang/include/clang/Options/Options.td
A clang/include/clang/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointers.h
M clang/include/clang/ScalableStaticAnalysis/BuiltinAnchorSources.def
A clang/include/clang/ScalableStaticAnalysis/SourceTransformation/YAMLSourceEditFormat.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTDumper.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/ByteCode/Program.h
M clang/lib/AST/CXXInheritance.cpp
M clang/lib/AST/Comment.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/AST/Type.cpp
M clang/lib/ASTMatchers/Dynamic/Registry.cpp
M clang/lib/Analysis/ExprMutationAnalyzer.cpp
M clang/lib/Basic/OffloadArch.cpp
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/CodeGen/TargetInfo.cpp
M clang/lib/CIR/CodeGen/TargetInfo.h
A clang/lib/CIR/CodeGen/Targets/NVPTX.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGCoroutine.cpp
M clang/lib/CodeGen/CGVTables.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenModule.h
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
M clang/lib/CodeGen/Targets/BPF.cpp
M clang/lib/CodeGen/Targets/X86.cpp
M clang/lib/Driver/Action.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/OffloadBundler.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/HIPAMD.h
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Driver/ToolChains/MSVC.h
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/lib/Driver/ToolChains/MinGW.h
M clang/lib/Frontend/ASTConsumers.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/lib/Headers/ptrauth.h
M clang/lib/Headers/riscv_packed_simd.h
M clang/lib/Index/IndexingContext.cpp
M clang/lib/InstallAPI/Visitor.cpp
M clang/lib/Lex/LiteralSupport.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/CMakeLists.txt
A clang/lib/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointersExtractor.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/SSAFAnalysesCommon.h
M clang/lib/ScalableStaticAnalysis/SourceTransformation/CMakeLists.txt
A clang/lib/ScalableStaticAnalysis/SourceTransformation/YAMLSourceEditFormat.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaAMDGPU.cpp
M clang/lib/Sema/SemaCXXScopeSpec.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/StaticAnalyzer/Core/BugSuppression.cpp
M clang/lib/Tooling/Syntax/BuildTree.cpp
A clang/test/AST/ByteCode/module-dummy-redecl.cpp
A clang/test/AST/ast-dump-init.cpp
M clang/test/AST/ast-dump-templates-pattern.cpp
A clang/test/CIR/CodeGenCUDA/surface.cu
M clang/test/CXX/basic/basic.link/p11.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg7xx.cpp
M clang/test/CXX/temp/temp.arg/temp.arg.template/p3-2a.cpp
M clang/test/CXX/temp/temp.constr/temp.constr.decl/p4.cpp
M clang/test/CXX/temp/temp.decls/temp.spec.partial/temp.spec.partial.member/p2.cpp
M clang/test/CXX/temp/temp.spec/temp.expl.spec/p7.cpp
M clang/test/CodeGen/AArch64/neon/fullfp16.c
M clang/test/CodeGen/AArch64/neon/subtraction.c
M clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M clang/test/CodeGen/X86/avx512fp16-abi.c
M clang/test/CodeGen/X86/bfloat-half-abi.c
M clang/test/CodeGen/X86/fp128-abi.c
M clang/test/CodeGen/X86/mmx-inline-asm-error.c
A clang/test/CodeGen/bpf-struct-return-regs.c
A clang/test/CodeGen/bpf-struct-return.c
M clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
M clang/test/CodeGen/lto-newpm-pipeline.c
M clang/test/CodeGen/ptrauth-intrinsics.c
A clang/test/CodeGen/target-avx-abi-diag-knr.c
M clang/test/CodeGen/target-builtin-error-3.c
M clang/test/CodeGen/target-features-error-2.c
M clang/test/CodeGenCUDA/builtins-amdgcn.cu
M clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
M clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
M clang/test/CodeGenCXX/default-arguments.cpp
M clang/test/CodeGenCXX/dtor-local-lambda-mangle.cpp
M clang/test/CodeGenCXX/dynamic-cast-exact.cpp
M clang/test/CodeGenCXX/explicit-instantiation.cpp
M clang/test/CodeGenCXX/mangle-lambdas-gh88906.cpp
A clang/test/CodeGenCXX/mangle-lambdas-in-dmi-local-class.cpp
A clang/test/CodeGenCXX/target-avx-abi-diag.cpp
M clang/test/CodeGenCoroutines/coro-elide.cpp
M clang/test/CodeGenCoroutines/coro-halo.cpp
M clang/test/CodeGenCoroutines/pr65018.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
A clang/test/Driver/Inputs/clang-offload-bundler-magic-collision.co
A clang/test/Driver/Inputs/clang-offload-bundler-magic-collision.py
A clang/test/Driver/aarch64-nvidia-rigel.c
M clang/test/Driver/amdgpu-toolchain.c
A clang/test/Driver/arm64x.c
A clang/test/Driver/clang-offload-bundler-magic-collision.c
M clang/test/Driver/hip-phases.hip
M clang/test/Driver/hip-toolchain-device-only.hip
M clang/test/Driver/msvc-link.c
A clang/test/Driver/print-enabled-extensions/aarch64-rigel.c
M clang/test/Frontend/compiler-options-dump.cpp
M clang/test/Interpreter/cxx20-modules.cppm
M clang/test/Interpreter/dynamic-library.cpp
M clang/test/Interpreter/lit.local.cfg
M clang/test/Misc/target-invalid-cpu-note/aarch64.c
M clang/test/Misc/warning-wall.c
A clang/test/Modules/GH207581.cpp
A clang/test/Modules/modules-using-enum-class-scope.cppm
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
M clang/test/Sema/attr-target.c
M clang/test/Sema/ptrauth-intrinsics-macro.c
M clang/test/Sema/ptrauth.c
M clang/test/SemaCXX/GH195416.cpp
M clang/test/SemaCXX/constant-expression-cxx14.cpp
M clang/test/SemaCXX/deduced-return-type-cxx14.cpp
M clang/test/SemaCXX/member-class-11.cpp
M clang/test/SemaCXX/warn-func-not-needed.cpp
M clang/test/SemaCXX/warn-variable-not-needed.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/test/SemaTemplate/friend-template.cpp
M clang/test/SemaTemplate/fun-template-def.cpp
M clang/test/SemaTemplate/instantiate-scope.cpp
M clang/test/Templight/templight-default-func-arg.cpp
M clang/test/Templight/templight-empty-entries-fix.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/libclang/CIndex.cpp
M clang/unittests/AST/ASTImporterTest.cpp
M clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
A clang/unittests/ScalableStaticAnalysis/Analyses/OperatorNewDelete/OperatorNewDeletePointersExtractorTest.cpp
M clang/unittests/ScalableStaticAnalysis/CMakeLists.txt
A clang/unittests/ScalableStaticAnalysis/SourceTransformation/YAMLFormatTest.cpp
A cmake/Modules/GetTripleCMakeSystemName.cmake
A cmake/Modules/NormalizeTriple.cmake
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M flang-rt/lib/runtime/io-api-server.cpp
M flang-rt/lib/runtime/time-intrinsic.cpp
M flang-rt/unittests/Runtime/tools.h
M flang/docs/FAQ.md
M flang/include/flang/Common/constexpr-bitset.h
M flang/include/flang/Common/idioms.h
M flang/include/flang/Decimal/binary-floating-point.h
M flang/include/flang/Evaluate/expression.h
M flang/include/flang/Evaluate/fold-designator.h
M flang/include/flang/Evaluate/fold.h
M flang/include/flang/Evaluate/intrinsics.h
M flang/include/flang/Evaluate/rewrite.h
M flang/include/flang/Evaluate/shape.h
M flang/include/flang/Evaluate/tools.h
M flang/include/flang/Evaluate/traverse.h
M flang/include/flang/Evaluate/type.h
M flang/include/flang/Frontend/CodeGenOptions.def
M flang/include/flang/Frontend/CodeGenOptions.h
M flang/include/flang/Frontend/TextDiagnostic.h
M flang/include/flang/Lower/Allocatable.h
M flang/include/flang/Lower/CUDA.h
M flang/include/flang/Lower/CallInterface.h
M flang/include/flang/Lower/ConvertExprToHLFIR.h
M flang/include/flang/Lower/ConvertType.h
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Lower/HostAssociations.h
M flang/include/flang/Lower/LoweringOptions.def
M flang/include/flang/Lower/Mangler.h
M flang/include/flang/Lower/OpenMP.h
M flang/include/flang/Lower/Runtime.h
M flang/include/flang/Lower/Support/ReductionProcessor.h
M flang/include/flang/Lower/Support/Utils.h
M flang/include/flang/Lower/SymbolMap.h
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/include/flang/Optimizer/Builder/DirectivesCommon.h
M flang/include/flang/Optimizer/Builder/Factory.h
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/include/flang/Optimizer/Builder/MIFCommon.h
A flang/include/flang/Optimizer/Builder/OpenACCIntrinsicCall.h
M flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h
M flang/include/flang/Optimizer/Builder/Runtime/Character.h
M flang/include/flang/Optimizer/Builder/Runtime/RTBuilder.h
M flang/include/flang/Optimizer/Builder/Todo.h
M flang/include/flang/Optimizer/CodeGen/CodeGenOpenMP.h
M flang/include/flang/Optimizer/CodeGen/TypeConverter.h
M flang/include/flang/Optimizer/Dialect/CUF/CUFDialect.h
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/include/flang/Optimizer/Dialect/FIRCG/CGOps.h
M flang/include/flang/Optimizer/Dialect/MIF/MIFDialect.h
M flang/include/flang/Optimizer/Dialect/SafeTempArrayCopyAttrInterface.h
M flang/include/flang/Optimizer/OpenACC/Analysis/FIROpenACCSupportAnalysis.h
M flang/include/flang/Optimizer/OpenMP/Passes.td
M flang/include/flang/Optimizer/Passes/Pipelines.h
M flang/include/flang/Optimizer/Support/InitFIR.h
M flang/include/flang/Optimizer/Support/InternalNames.h
M flang/include/flang/Optimizer/Support/Utils.h
M flang/include/flang/Optimizer/Transforms/CUDA/CUFAllocationConversion.h
M flang/include/flang/Optimizer/Transforms/CUFGPUToLLVMConversion.h
M flang/include/flang/Optimizer/Transforms/CUFOpConversion.h
M flang/include/flang/Optimizer/Transforms/MIFOpConversion.h
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/include/flang/Parser/char-block.h
M flang/include/flang/Parser/char-buffer.h
M flang/include/flang/Parser/openmp-utils.h
M flang/include/flang/Parser/parse-state.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Parser/token-sequence.h
M flang/include/flang/Parser/unparse.h
M flang/include/flang/Parser/user-state.h
M flang/include/flang/Runtime/CUDA/common.h
M flang/include/flang/Runtime/CUDA/kernel.h
M flang/include/flang/Runtime/array-constructor-consts.h
M flang/include/flang/Runtime/random.h
M flang/include/flang/Runtime/reduce.h
M flang/include/flang/Runtime/reduction.h
M flang/include/flang/Runtime/support.h
M flang/include/flang/Semantics/attr.h
M flang/include/flang/Semantics/expression.h
M flang/include/flang/Semantics/openmp-dsa.h
M flang/include/flang/Semantics/openmp-utils.h
M flang/include/flang/Semantics/runtime-type-info.h
M flang/include/flang/Semantics/semantics.h
M flang/include/flang/Semantics/type.h
M flang/include/flang/Semantics/unparse-with-symbols.h
M flang/include/flang/Tools/CrossToolHelpers.h
M flang/include/flang/Tools/TargetSetup.h
M flang/lib/Decimal/big-radix-floating-point.h
M flang/lib/Decimal/decimal-to-binary.cpp
M flang/lib/Evaluate/expression.cpp
M flang/lib/Evaluate/fold-implementation.h
M flang/lib/Evaluate/host.h
M flang/lib/Evaluate/intrinsics-library.cpp
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Evaluate/real.cpp
M flang/lib/Evaluate/tools.cpp
M flang/lib/Evaluate/variable.cpp
M flang/lib/Frontend/CodeGenOptions.cpp
M flang/lib/Frontend/CompilerInstance.cpp
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Frontend/FrontendAction.cpp
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
M flang/lib/Lower/Allocatable.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Lower/ConvertArrayConstructor.cpp
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Lower/ConvertExpr.cpp
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/CustomIntrinsicCall.cpp
M flang/lib/Lower/HostAssociations.cpp
M flang/lib/Lower/IO.cpp
M flang/lib/Lower/Mangler.cpp
M flang/lib/Lower/MultiImageFortran.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/Atomic.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.h
M flang/lib/Lower/OpenMP/Decomposer.cpp
M flang/lib/Lower/OpenMP/Decomposer.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/PFTBuilder.cpp
M flang/lib/Lower/Runtime.cpp
M flang/lib/Lower/Support/ReductionProcessor.cpp
M flang/lib/Lower/SymbolMap.cpp
M flang/lib/Lower/VectorSubscripts.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Builder/CMakeLists.txt
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/lib/Optimizer/Builder/CUFCommon.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Builder/MIFCommon.cpp
A flang/lib/Optimizer/Builder/OpenACCIntrinsicCall.cpp
M flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp
M flang/lib/Optimizer/Builder/Runtime/Character.cpp
M flang/lib/Optimizer/Builder/Runtime/Derived.cpp
M flang/lib/Optimizer/Builder/Runtime/Intrinsics.cpp
M flang/lib/Optimizer/Builder/Runtime/Main.cpp
M flang/lib/Optimizer/CodeGen/BoxedProcedure.cpp
M flang/lib/Optimizer/CodeGen/CodeGenOpenMP.cpp
M flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp
M flang/lib/Optimizer/CodeGen/PassDetail.h
M flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp
M flang/lib/Optimizer/CodeGen/TBAABuilder.cpp
M flang/lib/Optimizer/CodeGen/Target.cpp
M flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
M flang/lib/Optimizer/Dialect/CUF/Attributes/CUFAttr.cpp
M flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Dialect/MIF/MIFOps.cpp
M flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
M flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp
M flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/HLFIR/Transforms/PropagateFortranVariableAttributes.cpp
M flang/lib/Optimizer/HLFIR/Transforms/ScheduleOrderedAssignments.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/lib/Optimizer/OpenACC/Analysis/CMakeLists.txt
M flang/lib/Optimizer/OpenACC/Analysis/FIROpenACCSupportAnalysis.cpp
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCAttributes.cpp
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
M flang/lib/Optimizer/OpenMP/CMakeLists.txt
M flang/lib/Optimizer/OpenMP/DeleteUnreachableTargets.cpp
M flang/lib/Optimizer/OpenMP/FunctionFiltering.cpp
R flang/lib/Optimizer/OpenMP/HostOpFiltering.cpp
M flang/lib/Optimizer/OpenMP/LowerWorkdistribute.cpp
M flang/lib/Optimizer/OpenMP/LowerWorkshare.cpp
M flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
M flang/lib/Optimizer/OpenMP/MapsForPrivatizedSymbols.cpp
M flang/lib/Optimizer/OpenMP/Support/FIROpenMPAttributes.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Support/DataLayout.cpp
M flang/lib/Optimizer/Support/InternalNames.cpp
M flang/lib/Optimizer/Transforms/AddAliasTags.cpp
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/lib/Optimizer/Transforms/AffineDemotion.cpp
M flang/lib/Optimizer/Transforms/AffinePromotion.cpp
M flang/lib/Optimizer/Transforms/AssumedRankOpConversion.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFAllocDelay.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFAllocationConversion.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFComputeSharedMemoryOffsetsAndSize.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFDeviceFuncTransform.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFDeviceGlobal.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFFunctionRewrite.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFGPUToLLVMConversion.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFLaunchAttachAttr.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversionLate.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFPredefinedVarToGPU.cpp
M flang/lib/Optimizer/Transforms/CompilerGeneratedNames.cpp
M flang/lib/Optimizer/Transforms/ControlFlowConverter.cpp
M flang/lib/Optimizer/Transforms/ConvertComplexPow.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.h
M flang/lib/Optimizer/Transforms/ExternalNameConversion.cpp
M flang/lib/Optimizer/Transforms/FIRToMemRef.cpp
M flang/lib/Optimizer/Transforms/FIRToSCF.cpp
M flang/lib/Optimizer/Transforms/GenRuntimeCallsForTest.cpp
M flang/lib/Optimizer/Transforms/LoopInvariantCodeMotion.cpp
M flang/lib/Optimizer/Transforms/LoopVersioning.cpp
M flang/lib/Optimizer/Transforms/MIFOpConversion.cpp
M flang/lib/Optimizer/Transforms/MemRefDataFlowOpt.cpp
M flang/lib/Optimizer/Transforms/MemoryAllocation.cpp
M flang/lib/Optimizer/Transforms/MemoryUtils.cpp
M flang/lib/Optimizer/Transforms/OptimizeArrayRepacking.cpp
M flang/lib/Optimizer/Transforms/PolymorphicOpConversion.cpp
M flang/lib/Optimizer/Transforms/SetRuntimeCallAttributes.cpp
M flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp
M flang/lib/Optimizer/Transforms/SimplifyRegionLite.cpp
M flang/lib/Optimizer/Transforms/StackArrays.cpp
M flang/lib/Optimizer/Transforms/StackReclaim.cpp
M flang/lib/Optimizer/Transforms/VScaleAttr.cpp
M flang/lib/Parser/basic-parsers.h
M flang/lib/Parser/executable-parsers.cpp
M flang/lib/Parser/expr-parsers.cpp
M flang/lib/Parser/message.cpp
M flang/lib/Parser/openmp-utils.cpp
M flang/lib/Parser/parse-tree.cpp
M flang/lib/Parser/preprocessor.cpp
M flang/lib/Parser/prescan.cpp
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Parser/source.cpp
M flang/lib/Parser/token-parsers.h
M flang/lib/Semantics/assignment.cpp
M flang/lib/Semantics/canonicalize-omp.cpp
M flang/lib/Semantics/check-acc-structure.cpp
M flang/lib/Semantics/check-case.cpp
M flang/lib/Semantics/check-data.cpp
M flang/lib/Semantics/check-data.h
M flang/lib/Semantics/check-deallocate.cpp
M flang/lib/Semantics/check-do-forall.cpp
M flang/lib/Semantics/check-if-stmt.cpp
M flang/lib/Semantics/check-nullify.cpp
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-select-rank.cpp
M flang/lib/Semantics/check-select-type.cpp
M flang/lib/Semantics/check-stop.cpp
M flang/lib/Semantics/compute-offsets.cpp
M flang/lib/Semantics/mod-file.cpp
M flang/lib/Semantics/openmp-dsa.cpp
M flang/lib/Semantics/openmp-utils.cpp
M flang/lib/Semantics/pointer-assignment.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-labels.cpp
M flang/lib/Semantics/resolve-names-utils.cpp
M flang/lib/Semantics/resolve-names-utils.h
M flang/lib/Semantics/runtime-type-info.cpp
M flang/lib/Semantics/scope.cpp
M flang/lib/Support/LangOptions.cpp
M flang/lib/Support/Version.cpp
M flang/lib/Testing/fp-testing.cpp
M flang/test/Driver/driver-help.f90
A flang/test/Driver/real-sum-reassociation.f90
M flang/test/Fir/CUDA/cuda-constructor-2.f90
M flang/test/Fir/CUDA/cuda-function-rewrite.mlir
M flang/test/Fir/FirToSCF/do-loop.fir
M flang/test/Fir/basic-program.fir
M flang/test/Fir/target-rewrite-arg-position.fir
M flang/test/Lower/OpenACC/locations.f90
A flang/test/Lower/OpenMP/collapse-imperfect-nest.f90
A flang/test/Lower/OpenMP/collapse-loop-transform.f90
A flang/test/Lower/OpenMP/declare-reduction-operator-host-assoc.f90
A flang/test/Lower/OpenMP/function-filtering-4.f90
M flang/test/Lower/OpenMP/host-eval.f90
A flang/test/Lower/OpenMP/reduction-array-element.f90
A flang/test/Lower/split-sum-expression-tree-lowering.f90
M flang/test/Semantics/OpenMP/do-collapse.f90
M flang/test/Semantics/OpenMP/do-concurrent-collapse-60.f90
M flang/test/Semantics/OpenMP/do-concurrent-collapse.f90
M flang/test/Semantics/OpenMP/do08.f90
M flang/test/Semantics/OpenMP/do10.f90
M flang/test/Semantics/OpenMP/do13.f90
M flang/test/Semantics/OpenMP/do15.f90
M flang/test/Semantics/OpenMP/do16.f90
M flang/test/Semantics/OpenMP/do22.f90
A flang/test/Semantics/OpenMP/doacross-nesting-omp60.f90
A flang/test/Semantics/OpenMP/ordered-nesting-omp50.f90
A flang/test/Semantics/OpenMP/ordered-nesting-omp51.f90
M flang/test/Transforms/CUF/cuf-alloc-delay.fir
A flang/test/Transforms/FIRToMemRef/emboxed-slice-array-coor.mlir
A flang/test/Transforms/FIRToMemRef/emboxed-slice-non-unit-stride-non-unit-lb.mlir
A flang/test/Transforms/FIRToMemRef/emboxed-slice-rank-reduction-nonprefix.mlir
A flang/test/Transforms/FIRToMemRef/emboxed-slice-rank-reduction.mlir
A flang/test/Transforms/FIRToMemRef/emboxed-slice-stride.mlir
R flang/test/Transforms/OpenMP/function-filtering-host-ops.mlir
M flang/test/Transforms/stack-arrays.fir
M flang/unittests/Optimizer/CMakeLists.txt
A flang/unittests/Optimizer/OpenACC/FIROpenACCSupportAnalysisTest.cpp
M libc/config/gpu/amdgpu/entrypoints.txt
M libc/config/gpu/nvptx/entrypoints.txt
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/headers/stdfix.rst
M libc/fuzzing/arpa/inet/CMakeLists.txt
A libc/fuzzing/arpa/inet/inet_ntop_differential_fuzz.cpp
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/sa_family_t.h
M libc/include/CMakeLists.txt
A libc/include/err.yaml
M libc/shared/builtins.h
A libc/shared/builtins/divsf3.h
A libc/shared/builtins/mulsf3.h
M libc/src/CMakeLists.txt
M libc/src/__support/CPP/string.h
M libc/src/__support/File/linux/CMakeLists.txt
M libc/src/__support/File/linux/file.cpp
R libc/src/__support/OSUtil/fcntl.h
M libc/src/__support/OSUtil/linux/CMakeLists.txt
R libc/src/__support/OSUtil/linux/fcntl.cpp
M libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
M libc/src/__support/OSUtil/linux/syscall_wrappers/dup2.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/fcntl.h
M libc/src/__support/builtins/CMakeLists.txt
A libc/src/__support/builtins/divsf3.h
A libc/src/__support/builtins/mulsf3.h
A libc/src/err/CMakeLists.txt
A libc/src/err/err.cpp
A libc/src/err/err.h
A libc/src/err/errx.cpp
A libc/src/err/errx.h
A libc/src/err/report.cpp
A libc/src/err/report.h
A libc/src/err/verr.cpp
A libc/src/err/verr.h
A libc/src/err/verrx.cpp
A libc/src/err/verrx.h
A libc/src/err/vwarn.cpp
A libc/src/err/vwarn.h
A libc/src/err/vwarnx.cpp
A libc/src/err/vwarnx.h
A libc/src/err/warn.cpp
A libc/src/err/warn.h
A libc/src/err/warnx.cpp
A libc/src/err/warnx.h
M libc/src/fcntl/linux/CMakeLists.txt
M libc/src/fcntl/linux/fcntl.cpp
A libc/src/mathvec/aarch64/CMakeLists.txt
A libc/src/mathvec/aarch64/common.h
A libc/src/mathvec/aarch64/expf.cpp
M libc/src/spawn/linux/CMakeLists.txt
M libc/src/spawn/linux/posix_spawn.cpp
R libc/src/stdfix/bitusk.cpp
M libc/src/stdio/printf_core/float_hex_converter.h
M libc/test/UnitTest/BazelFilePath.cpp
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_builtins_test.cpp
M libc/test/src/CMakeLists.txt
M libc/test/src/__support/CPP/string_test.cpp
A libc/test/src/err/CMakeLists.txt
A libc/test/src/err/err_test.cpp
A libc/test/src/err/errx_test.cpp
A libc/test/src/err/verr_test.cpp
A libc/test/src/err/verrx_test.cpp
A libc/test/src/err/vwarn_test.cpp
A libc/test/src/err/vwarnx_test.cpp
A libc/test/src/err/warn_test.cpp
A libc/test/src/err/warnx_test.cpp
M libc/test/src/stdfix/CMakeLists.txt
A libc/test/src/stdfix/IdivFxTest.h
R libc/test/src/stdfix/IdivTest.h
M libc/test/src/stdfix/idivk_test.cpp
M libc/test/src/stdfix/idivlk_test.cpp
M libc/test/src/stdfix/idivlr_test.cpp
M libc/test/src/stdfix/idivr_test.cpp
M libc/test/src/stdfix/idivuk_test.cpp
M libc/test/src/stdfix/idivulk_test.cpp
M libc/test/src/stdfix/idivulr_test.cpp
M libc/test/src/stdfix/idivur_test.cpp
M libc/test/src/sys/socket/linux/CMakeLists.txt
M libc/test/src/sys/socket/linux/bind_test.cpp
M libc/test/src/sys/socket/linux/connect_accept_test.cpp
M libc/test/src/sys/socket/linux/sockaddr_storage_helper.cpp
M libc/test/src/sys/socket/linux/sockaddr_storage_test.cpp
M libc/test/src/sys/socket/linux/sockname_test.cpp
M libcxx/docs/ReleaseNotes/23.rst
M libcxx/docs/Status/Cxx26Issues.csv
M libcxx/include/__algorithm/pstl.h
M libcxx/include/__algorithm/simd_utils.h
M libcxx/include/__atomic/atomic_ref.h
M libcxx/include/__chrono/duration.h
M libcxx/include/__configuration/attributes.h
M libcxx/include/__locale_dir/support/no_locale/characters.h
M libcxx/include/__locale_dir/support/no_locale/conversions.h
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/__mutex/lock_guard.h
M libcxx/include/__mutex/mutex.h
M libcxx/include/__pstl/backend_fwd.h
M libcxx/include/__pstl/backends/default.h
M libcxx/include/__ranges/lazy_split_view.h
M libcxx/include/__ranges/zip_view.h
M libcxx/include/__vector/layout.h
M libcxx/include/__vector/vector.h
M libcxx/include/chrono
M libcxx/include/mutex
M libcxx/include/shared_mutex
A libcxx/test/extensions/clang/thread/thread.mutex/thread_safety_scoped_lock.pass.cpp
A libcxx/test/extensions/clang/thread/thread.mutex/thread_safety_scoped_lock.verify.cpp
M libcxx/test/libcxx/algorithms/pstl.iterator-requirements.verify.cpp
M libcxx/test/libcxx/algorithms/pstl.nodiscard.verify.cpp
A libcxx/test/libcxx/ranges/range.adaptors/range.lazy.split/nodiscard.verify.cpp
M libcxx/test/libcxx/ranges/range.adaptors/range.zip.transform/nodiscard.verify.cpp
A libcxx/test/libcxx/ranges/range.adaptors/range.zip/nodiscard.verify.cpp
A libcxx/test/libcxx/ranges/range.adaptors/range_adaptor_types.h
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find.first.of/find_first_of.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find.first.of/find_first_of_pred.pass.cpp
A libcxx/test/std/algorithms/alg.nonmodifying/alg.find.first.of/pstl.find_first_of.pass.cpp
A libcxx/test/std/algorithms/alg.nonmodifying/alg.find.first.of/pstl.find_first_of_pred.pass.cpp
M libcxx/test/std/algorithms/pstl.exception_handling.pass.cpp
M libcxx/test/std/atomics/atomics.ref/ctor.pass.cpp
A libcxx/test/std/time/time.duration/duration.verify.cpp
M libcxx/test/std/utilities/memory/specialized.algorithms/uninitialized.move/uninitialized_move.pass.cpp
M libcxx/test/std/utilities/memory/specialized.algorithms/uninitialized.move/uninitialized_move_n.pass.cpp
M libunwind/test/aarch64_za_unwind.pass.cpp
M lld/COFF/Driver.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
A lld/test/COFF/arm64x-hybridobj.s
M lld/test/ELF/compressed-debug-level.test
M lld/test/ELF/lto/devirt_vcall_vis_export_dynamic.ll
M lld/test/ELF/lto/devirt_vcall_vis_public.ll
M lld/test/ELF/lto/devirt_vcall_vis_shared_def.ll
M lldb/bindings/interface/SBValueDocstrings.i
M lldb/bindings/python/get-python-config.py
M lldb/include/lldb/API/SBValue.h
M lldb/include/lldb/DataFormatters/DataVisualization.h
M lldb/include/lldb/DataFormatters/FormatManager.h
M lldb/include/lldb/DataFormatters/TypeCategoryMap.h
M lldb/include/lldb/Expression/DWARFExpression.h
M lldb/include/lldb/Expression/DWARFExpressionList.h
M lldb/include/lldb/Target/DynamicRegisterInfo.h
M lldb/include/lldb/Target/Process.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/Utility/Policy.h
M lldb/include/lldb/ValueObject/ValueObject.h
M lldb/include/lldb/ValueObject/ValueObjectVariable.h
M lldb/include/lldb/lldb-forward.h
M lldb/source/API/SBBreakpointName.cpp
M lldb/source/API/SBTarget.cpp
M lldb/source/API/SBValue.cpp
M lldb/source/Breakpoint/BreakpointIDList.cpp
M lldb/source/Commands/CommandObjectBreakpoint.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/DataFormatters/DataVisualization.cpp
M lldb/source/DataFormatters/TypeCategoryMap.cpp
M lldb/source/Expression/DWARFExpression.cpp
M lldb/source/Expression/DWARFExpressionList.cpp
M lldb/source/Expression/FunctionCaller.cpp
M lldb/source/Expression/IRInterpreter.cpp
M lldb/source/Expression/LLVMUserExpression.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusNameParser.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h
M lldb/source/Plugins/Process/gdb-remote/ThreadGDBRemote.cpp
M lldb/source/Plugins/Process/gdb-remote/ThreadGDBRemote.h
M lldb/source/Plugins/Process/wasm/ProcessWasm.h
M lldb/source/Plugins/Process/wasm/RegisterContextWasm.cpp
M lldb/source/Plugins/Process/wasm/RegisterContextWasm.h
M lldb/source/Plugins/Process/wasm/UnwindWasm.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Symbol/Type.cpp
M lldb/source/Target/DynamicRegisterInfo.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/StackFrameList.cpp
M lldb/source/Target/StopInfo.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/Thread.cpp
M lldb/source/Utility/ArchSpec.cpp
M lldb/source/Utility/FileSpec.cpp
M lldb/source/Utility/FileSpecList.cpp
M lldb/source/Utility/Policy.cpp
M lldb/source/ValueObject/ValueObject.cpp
M lldb/source/ValueObject/ValueObjectVariable.cpp
M lldb/test/API/commands/platform/connect/TestPlatformConnect.py
M lldb/test/API/functionalities/gdb_remote_client/TestWasm.py
A lldb/test/API/functionalities/scripted_frame_provider/register_command_status/Makefile
A lldb/test/API/functionalities/scripted_frame_provider/register_command_status/TestFrameProviderRegisterCommandStatus.py
A lldb/test/API/functionalities/scripted_frame_provider/register_command_status/frame_provider.py
A lldb/test/API/functionalities/scripted_frame_provider/register_command_status/main.c
M lldb/test/API/python_api/type/TestTypeList.py
M lldb/test/API/python_api/type/main.cpp
M lldb/test/API/python_api/value/change_values/TestChangeValueAPI.py
M lldb/unittests/Expression/DWARFExpressionTest.cpp
M lldb/unittests/Language/CPlusPlus/CPlusPlusLanguageTest.cpp
M lldb/unittests/ObjectFile/ELF/TestObjectFileELF.cpp
M lldb/unittests/Utility/ArchSpecTest.cpp
M lldb/unittests/Utility/PolicyTest.cpp
M llvm/Maintainers.md
M llvm/cmake/modules/FindLibXml2.cmake
M llvm/cmake/modules/LLVMConfig.cmake.in
M llvm/cmake/modules/LLVMExternalProjectUtils.cmake
M llvm/docs/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack.md
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/AddingConstrainedIntrinsics.rst
M llvm/docs/HowToUpdateDebugInfo.rst
M llvm/docs/LFI.rst
A llvm/docs/LangRef.md
R llvm/docs/LangRef.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/ABI/TargetInfo.h
M llvm/include/llvm/ABI/Types.h
M llvm/include/llvm/ADT/FunctionExtras.h
M llvm/include/llvm/Analysis/BranchProbabilityInfo.h
M llvm/include/llvm/Analysis/CtxProfAnalysis.h
M llvm/include/llvm/Bitcode/BitcodeReader.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGenTypes/MachineValueType.h
M llvm/include/llvm/DWARFLinker/Classic/DWARFLinkerCompileUnit.h
M llvm/include/llvm/Debuginfod/BuildIDFetcher.h
M llvm/include/llvm/Demangle/Demangle.h
M llvm/include/llvm/Demangle/MicrosoftDemangleNodes.h
M llvm/include/llvm/IR/GlobalObject.h
M llvm/include/llvm/IR/GlobalValue.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/include/llvm/IR/Module.h
M llvm/include/llvm/IR/ModuleSummaryIndex.h
M llvm/include/llvm/IR/PassManagerInternal.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/LTO/LTO.h
M llvm/include/llvm/MC/MCDXContainerWriter.h
M llvm/include/llvm/Object/BuildID.h
M llvm/include/llvm/Object/ELFObjectFile.h
M llvm/include/llvm/ObjectYAML/ContiguousBlobAccumulator.h
M llvm/include/llvm/Passes/PassBuilder.h
M llvm/include/llvm/Plugins/PassPlugin.h
M llvm/include/llvm/ProfileData/SampleProf.h
M llvm/include/llvm/ProfileData/SampleProfReader.h
M llvm/include/llvm/ProfileData/SampleProfWriter.h
M llvm/include/llvm/Support/AutoConvert.h
M llvm/include/llvm/Support/BranchProbability.h
M llvm/include/llvm/Support/Compiler.h
M llvm/include/llvm/Support/GenericLoopInfo.h
M llvm/include/llvm/Support/GenericLoopInfoImpl.h
M llvm/include/llvm/Support/thread.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/include/llvm/TargetParser/Triple.h
A llvm/include/llvm/Transforms/Utils/AssignGUID.h
M llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
M llvm/include/llvm/Transforms/Utils/Debugify.h
M llvm/include/llvm/Transforms/Utils/Local.h
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/lib/ABI/CMakeLists.txt
M llvm/lib/ABI/IRTypeMapper.cpp
M llvm/lib/ABI/TargetInfo.cpp
A llvm/lib/ABI/Targets/X86.cpp
M llvm/lib/ABI/Types.cpp
M llvm/lib/Analysis/AssumptionCache.cpp
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
M llvm/lib/Analysis/CtxProfAnalysis.cpp
M llvm/lib/Analysis/HashRecognize.cpp
M llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
M llvm/lib/Analysis/MemorySSA.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeAnalyzer.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/lib/CodeGen/GlobalMerge.cpp
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/CodeGen/ReplaceWithVeclib.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/DWARFLinker/Classic/DWARFLinkerCompileUnit.cpp
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.cpp
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.cpp
M llvm/lib/DebugInfo/Symbolize/Symbolize.cpp
M llvm/lib/Debuginfod/BuildIDFetcher.cpp
M llvm/lib/Demangle/MicrosoftDemangle.cpp
M llvm/lib/Demangle/MicrosoftDemangleNodes.cpp
M llvm/lib/Frontend/OpenMP/OMPContext.cpp
M llvm/lib/IR/Globals.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/LTO/LTO.cpp
M llvm/lib/LTO/LTOBackend.cpp
M llvm/lib/MC/MCDXContainerWriter.cpp
M llvm/lib/MC/MCLFI.cpp
M llvm/lib/Object/BuildID.cpp
M llvm/lib/Object/OffloadBundle.cpp
M llvm/lib/Object/RelocationResolver.cpp
M llvm/lib/ObjectYAML/ContiguousBlobAccumulator.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
M llvm/lib/ProfileData/InstrProfCorrelator.cpp
M llvm/lib/ProfileData/SampleProfReader.cpp
M llvm/lib/ProfileData/SampleProfWriter.cpp
M llvm/lib/Support/AutoConvert.cpp
M llvm/lib/Support/BranchProbability.cpp
M llvm/lib/Support/CrashRecoveryContext.cpp
M llvm/lib/Support/Unix/Path.inc
M llvm/lib/Support/Unix/Threading.inc
M llvm/lib/Support/raw_ostream.cpp
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
M llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
M llvm/lib/Target/AArch64/AArch64Processors.td
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombine.td
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/SMInstructions.td
M llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
M llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/BPF/BPFMIPeephole.cpp
M llvm/lib/Target/DirectX/DXContainerGlobals.cpp
M llvm/lib/Target/DirectX/DXContainerPDB.cpp
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
M llvm/lib/Target/DirectX/DXILOpBuilder.cpp
M llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
M llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonPatterns.td
M llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
M llvm/lib/Target/Hexagon/HexagonXQFloatGenerator.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
M llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
M llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
M llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.h
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.h
M llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.h
M llvm/lib/Target/SystemZ/SystemZInstrInfo.td
M llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/WebAssembly.td
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp
M llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp
M llvm/lib/Target/X86/MCTargetDesc/CMakeLists.txt
A llvm/lib/Target/X86/MCTargetDesc/X86MCLFIRewriter.cpp
A llvm/lib/Target/X86/MCTargetDesc/X86MCLFIRewriter.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86InstrAVX10.td
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86Subtarget.h
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/TargetDataLayout.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/IPO/ConstantMerge.cpp
M llvm/lib/Transforms/IPO/ExpandVariadics.cpp
M llvm/lib/Transforms/IPO/FunctionImport.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/lib/Transforms/IPO/OpenMPOpt.cpp
M llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
M llvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
M llvm/lib/Transforms/Instrumentation/PGOCtxProfFlattening.cpp
M llvm/lib/Transforms/Instrumentation/PGOCtxProfLowering.cpp
M llvm/lib/Transforms/ObjCARC/ObjCARCOpts.cpp
M llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
M llvm/lib/Transforms/Scalar/JumpTableToSwitch.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
A llvm/lib/Transforms/Utils/AssignGUID.cpp
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
M llvm/lib/Transforms/Utils/CMakeLists.txt
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
M llvm/lib/Transforms/Utils/CloneModule.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/lib/Transforms/Utils/FunctionImportUtils.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Scheduler.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/runtimes/CMakeLists.txt
M llvm/test/Analysis/CostModel/AArch64/mul.ll
R llvm/test/Analysis/CtxProfAnalysis/flatten-prethinlink-requires-guid-metadata.ll
M llvm/test/Analysis/HashRecognize/cyclic-redundancy-check.ll
M llvm/test/Analysis/MemorySSA/invariant-load-intrinsic.ll
M llvm/test/Assembler/index-value-order.ll
M llvm/test/Bitcode/thinlto-alias.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph-partial-sample-profile-summary.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph-pgo.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph-profile-summary.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph-sample-profile-summary.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph.ll
M llvm/test/Bitcode/thinlto-function-summary-refgraph.ll
M llvm/test/Bitcode/thinlto-function-summary.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-lse2.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-lse2_lse128.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc3.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-load-lse2.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-load-lse2_lse128.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-load-rcpc3.ll
M llvm/test/CodeGen/AArch64/Atomics/generate-tests.py
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abds.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abdu.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-abs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-add.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-ashr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-assertzext.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-buildvector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-concat.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-const.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-ctls.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-cttz.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-extract-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-fshl-fshr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-rotl-rotr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-saddo.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sdiv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shl.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shuffle.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-smulh.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-srem.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-stepvector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sub.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sve-splat.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-trunk.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uaddo.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-udiv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-umulh.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-unmerge.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownbits-zext.mir
M llvm/test/CodeGen/AArch64/GlobalISel/uaddo-8-16-bits.mir
M llvm/test/CodeGen/AArch64/GlobalISel/v8.4-atomic-128.ll
M llvm/test/CodeGen/AArch64/arm64-fp128.ll
M llvm/test/CodeGen/AArch64/arm64-neon-v1i1-setcc.ll
A llvm/test/CodeGen/AArch64/br-cond-merging-loaded-operands.ll
M llvm/test/CodeGen/AArch64/cpus.ll
M llvm/test/CodeGen/AArch64/div-i256.ll
A llvm/test/CodeGen/AArch64/expand-form-transposed-tuple.mir
M llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
M llvm/test/CodeGen/AArch64/fast-isel-int-ext.ll
M llvm/test/CodeGen/AArch64/fcmp.ll
M llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.ll
M llvm/test/CodeGen/AArch64/misched-fusion-arith-cbz.mir
A llvm/test/CodeGen/AArch64/misched-push-form-transposed-tuple-to-users.mir
A llvm/test/CodeGen/AArch64/ptrauth-intrinsic-auth-with-pc-and-resign.ll
M llvm/test/CodeGen/AArch64/ptrauth-isel.ll
M llvm/test/CodeGen/AArch64/ptrauth-isel.mir
M llvm/test/CodeGen/AArch64/ragreedy-csr.ll
M llvm/test/CodeGen/AArch64/sbc-add-constant.ll
A llvm/test/CodeGen/AArch64/smax-allones.ll
M llvm/test/CodeGen/AArch64/sme-aarch64-svcount.ll
M llvm/test/CodeGen/AArch64/sme2-multivec-regalloc.mir
M llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
A llvm/test/CodeGen/AArch64/sve-interleave-low-vf.ll
A llvm/test/CodeGen/AArch64/sve-pred-ldst.ll
M llvm/test/CodeGen/AArch64/sve-select.ll
M llvm/test/CodeGen/AArch64/udiv-const-optimization.ll
M llvm/test/CodeGen/AArch64/v8.4-atomic-128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.atomic.cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir
M llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
M llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
M llvm/test/CodeGen/AMDGPU/agpr-csr.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ptr.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-fast.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr-fast.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-triple.ll
M llvm/test/CodeGen/AMDGPU/and.ll
M llvm/test/CodeGen/AMDGPU/andorn2.ll
M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
M llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_cond.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir
M llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir
M llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir
M llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
M llvm/test/CodeGen/AMDGPU/ctls.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2_a_v.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fceil64.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/implicit-arg-block-count.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.simple.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
A llvm/test/CodeGen/AMDGPU/march-amdgcn-legacy-arch-name.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
R llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-memops.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/siloadstoreopt-misaligned-regsequence.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl-bitcast-bv.ll
M llvm/test/CodeGen/AMDGPU/ssubo.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/structurize-hoist.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
M llvm/test/CodeGen/AMDGPU/swdev380865.ll
A llvm/test/CodeGen/AMDGPU/target-id-from-triple.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
M llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
A llvm/test/CodeGen/AMDGPU/validate-subtarget-subarch-empty-module.ll
A llvm/test/CodeGen/AMDGPU/validate-subtarget-subarch.ll
M llvm/test/CodeGen/AMDGPU/valu-i1.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/wqm.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
A llvm/test/CodeGen/ARM/unaligned_load_store_no_aeabi.ll
A llvm/test/CodeGen/BPF/aggr_ret_regs.ll
A llvm/test/CodeGen/DirectX/ContainerData/ContainerFlags.ll
M llvm/test/CodeGen/DirectX/ContainerData/DebugName-default-output.test
M llvm/test/CodeGen/DirectX/ContainerData/DebugName-user-directory.test
A llvm/test/CodeGen/DirectX/ContainerData/DebugName-user-specified.test
A llvm/test/CodeGen/DirectX/ContainerData/DebugName.test
M llvm/test/CodeGen/DirectX/ContainerData/PDBParts.test
M llvm/test/CodeGen/DirectX/ContainerData/SourceInfo-Args.ll
M llvm/test/CodeGen/DirectX/ContainerData/SourceInfo-Compressed.ll
M llvm/test/CodeGen/DirectX/ContainerData/SourceInfo-Uncompressed.ll
M llvm/test/CodeGen/DirectX/embed-ildb.ll
A llvm/test/CodeGen/DirectX/imul_umul.ll
A llvm/test/CodeGen/DirectX/overflow_intrinsics.ll
M llvm/test/CodeGen/Hexagon/autohvx/xqf-assertion1.ll
M llvm/test/CodeGen/Hexagon/autohvx/xqf-check-qf-instrs.ll
A llvm/test/CodeGen/Hexagon/autohvx/xqf-compliant-ieee-mul-qf16.ll
A llvm/test/CodeGen/Hexagon/autohvx/xqf-compliant-ieee-mul-qf32.ll
A llvm/test/CodeGen/Hexagon/autohvx/xqf-convert-elim.ll
A llvm/test/CodeGen/Hexagon/autohvx/xqf-lossy-mul-qf16.ll
A llvm/test/CodeGen/Hexagon/autohvx/xqf-lossy-mul-qf32.ll
A llvm/test/CodeGen/Hexagon/autohvx/xqf-v81/xqf-v81-compliant-ieee-mul-qf32.ll
A llvm/test/CodeGen/Hexagon/autohvx/xqf-v81/xqf-v81-lossy-mul-qf32.ll
A llvm/test/CodeGen/Hexagon/autohvx/xqf-v81/xqf-v81-vsub.ll
A llvm/test/CodeGen/Hexagon/autohvx/xqf-vsub.ll
A llvm/test/CodeGen/Hexagon/fshl-fshr-i32-mask.ll
M llvm/test/CodeGen/Hexagon/funnel-shift.ll
A llvm/test/CodeGen/Hexagon/pr183850.ll
M llvm/test/CodeGen/Hexagon/rotate.ll
M llvm/test/CodeGen/Hexagon/shadow-call-stack.ll
A llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-any-ext.ll
M llvm/test/CodeGen/LoongArch/lasx/vxi1-masks.ll
A llvm/test/CodeGen/LoongArch/lasx/xvexth.ll
A llvm/test/CodeGen/LoongArch/lsx/vexth.ll
M llvm/test/CodeGen/MIR/AMDGPU/init-whole.wave.ll
M llvm/test/CodeGen/NVPTX/tanhf.ll
M llvm/test/CodeGen/NVPTX/tcgen05-ld.ll
M llvm/test/CodeGen/NVPTX/tcgen05-st.ll
M llvm/test/CodeGen/PowerPC/test-issue-98598.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/rvp-reverse.ll
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
A llvm/test/CodeGen/RISCV/rvp-zip.ll
M llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
A llvm/test/CodeGen/RISCV/rvv/vecreduce-add-constant-fold.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll
M llvm/test/CodeGen/RISCV/stack-offset-large.ll
M llvm/test/CodeGen/RISCV/udiv-const-optimization.ll
A llvm/test/CodeGen/SPIRV/capability-Int64Atomics-weak-cmpxchg.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bfloat16_arithmetic/bfloat16-ocl-ext.ll
M llvm/test/CodeGen/SPIRV/instructions/atomic-ptr.ll
A llvm/test/CodeGen/SPIRV/instructions/phi-aggregate-call.ll
A llvm/test/CodeGen/SPIRV/instructions/phi-aggregate-with-overflow-zeroinitializer.ll
A llvm/test/CodeGen/SPIRV/instructions/phi-aggregate-with-overflow.ll
A llvm/test/CodeGen/SPIRV/instructions/select-freeze-aggregate-with-overflow.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/signed_arithmetic_overflow.ll
A llvm/test/CodeGen/SPIRV/transcoding/atomic-load-store-exchange-unsupported.ll
R llvm/test/CodeGen/SPIRV/transcoding/atomic-load-store-unsupported.ll
M llvm/test/CodeGen/SystemZ/call-zos-01.ll
M llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
M llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
M llvm/test/CodeGen/SystemZ/zos-ada.ll
M llvm/test/CodeGen/SystemZ/zos-frameaddr.ll
M llvm/test/CodeGen/SystemZ/zos-ppa1.ll
M llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll
M llvm/test/CodeGen/SystemZ/zos-stack-protector.ll
M llvm/test/CodeGen/Thumb2/vqabs.ll
M llvm/test/CodeGen/Thumb2/vqneg.ll
A llvm/test/CodeGen/WebAssembly/f128-minmax.ll
A llvm/test/CodeGen/WebAssembly/fast-isel-atomic-fold.ll
M llvm/test/CodeGen/WebAssembly/fpclamptosat.ll
M llvm/test/CodeGen/X86/apx/ccmp.ll
A llvm/test/CodeGen/X86/apx/peephole-fold-subreg-tied-copy.mir
M llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
M llvm/test/CodeGen/X86/avx512fp16-combine-shuffle-fma.ll
M llvm/test/CodeGen/X86/bmi2.ll
R llvm/test/CodeGen/X86/combine-pmadd.ll
A llvm/test/CodeGen/X86/combine-pmaddubsw.ll
A llvm/test/CodeGen/X86/combine-pmaddwd.ll
M llvm/test/CodeGen/X86/combine-smax.ll
M llvm/test/CodeGen/X86/combine-smin.ll
M llvm/test/CodeGen/X86/divide-by-constant.ll
M llvm/test/CodeGen/X86/fat-lto-section.ll
M llvm/test/CodeGen/X86/fminimum-fmaximum.ll
M llvm/test/CodeGen/X86/insert.ll
M llvm/test/CodeGen/X86/known-never-zero.ll
M llvm/test/CodeGen/X86/ldexp-avx512.ll
A llvm/test/CodeGen/X86/lfi-sibcall.ll
A llvm/test/CodeGen/X86/mulhu-v4i64-umul-lohi-guard.ll
M llvm/test/CodeGen/X86/probe-stack-eflags.ll
M llvm/test/CodeGen/X86/sat-add.ll
M llvm/test/CodeGen/X86/srem-vector-lkk.ll
M llvm/test/CodeGen/X86/subvectorwise-store-of-vector-splat.ll
M llvm/test/CodeGen/X86/udiv-const-optimization.ll
M llvm/test/CodeGen/X86/urem-vector-lkk.ll
M llvm/test/CodeGen/X86/vec-strict-cmp-128.ll
M llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
M llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
M llvm/test/CodeGen/X86/vector-narrow-binop.ll
M llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
M llvm/test/CodeGen/X86/vector-reduce-add-zext.ll
M llvm/test/CodeGen/X86/vector-reduce-ctpop.ll
M llvm/test/CodeGen/X86/vector-reduce-fmul-fast.ll
M llvm/test/CodeGen/X86/vector-trunc.ll
A llvm/test/DebugInfo/AArch64/machine-cp-updates-dbg-reg-subreg.mir
M llvm/test/LTO/Resolution/X86/not-prevailing-alias.ll
M llvm/test/LTO/Resolution/X86/not-prevailing-weak-aliasee.ll
A llvm/test/Linker/Inputs/amdgpu-amdpal-no-subarch.ll
A llvm/test/Linker/Inputs/amdgpu-no-subarch.ll
A llvm/test/Linker/Inputs/amdgpu10-subarch.ll
A llvm/test/Linker/Inputs/amdgpu9.00-subarch.ll
A llvm/test/Linker/amdgpu-triple-os-mismatch.ll
A llvm/test/Linker/amdgpu-triple-subarch.ll
M llvm/test/Linker/funcimport2.ll
M llvm/test/MC/AMDGPU/amd-amdgpu-isa-malformed-target-id.s
A llvm/test/MC/AMDGPU/amdgcn-target-directive-subarch-cpu-field.s
M llvm/test/MC/AMDGPU/amdgcn-target-malformed-target-id.s
M llvm/test/MC/AMDGPU/amdgcn_target_directive_from_eflags.s
A llvm/test/MC/AMDGPU/arch-amdgcn-legacy-arch-name.s
M llvm/test/MC/AMDGPU/gfx1250_asm_smem.s
M llvm/test/MC/AMDGPU/gfx1250_asm_smem_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
A llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc-fake16.txt
R llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
M llvm/test/MC/RISCV/corev/XCValu-invalid.s
M llvm/test/MC/RISCV/corev/XCVbitmanip-invalid.s
M llvm/test/MC/RISCV/corev/XCVmac-invalid.s
M llvm/test/MC/RISCV/corev/XCVmem-invalid.s
M llvm/test/MC/RISCV/corev/XCVsimd-invalid.s
M llvm/test/MC/RISCV/insn-invalid.s
M llvm/test/MC/RISCV/insn_c-invalid.s
M llvm/test/MC/RISCV/insn_xqci-invalid.s
M llvm/test/MC/RISCV/priv-invalid.s
M llvm/test/MC/RISCV/rv32c-invalid.s
M llvm/test/MC/RISCV/rv32i-invalid.s
M llvm/test/MC/RISCV/rv32zalrsc-invalid.s
M llvm/test/MC/RISCV/rv32zbb-invalid.s
M llvm/test/MC/RISCV/rv32zcmop-invalid.s
M llvm/test/MC/RISCV/rv64zalrsc-invalid.s
M llvm/test/MC/RISCV/rv64zbb-invalid.s
M llvm/test/MC/RISCV/rvc-hints-invalid.s
M llvm/test/MC/RISCV/rvv/zvvfmm-invalid.s
M llvm/test/MC/RISCV/rvv/zvvmm-invalid.s
M llvm/test/MC/RISCV/rvv/zvvmtls-invalid.s
M llvm/test/MC/RISCV/rvv/zvvmttls-invalid.s
M llvm/test/MC/RISCV/rvzicond-invalid.s
M llvm/test/MC/RISCV/rvzihintntl-invalid.s
M llvm/test/MC/RISCV/rvzihintntlc-invalid.s
M llvm/test/MC/RISCV/smrnmi-invalid.s
M llvm/test/MC/RISCV/tlsdesc.s
M llvm/test/MC/RISCV/xmips-invalid.s
M llvm/test/MC/RISCV/xqci-access-pseudos.s
M llvm/test/MC/RISCV/xqciint-invalid.s
M llvm/test/MC/RISCV/xqcisim-invalid.s
M llvm/test/MC/RISCV/xqcisync-invalid.s
M llvm/test/MC/RISCV/xtheadcmo-invalid.s
M llvm/test/MC/RISCV/xtheadcondmov-invalid.s
M llvm/test/MC/RISCV/xtheadsync-invalid.s
M llvm/test/MC/WebAssembly/function-alias.ll
A llvm/test/MC/X86/LFI/abi-note.s
A llvm/test/MC/X86/LFI/syscall.s
A llvm/test/MC/X86/LFI/thread-pointer-errors.s
A llvm/test/MC/X86/LFI/thread-pointer.s
M llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
M llvm/test/Object/AMDGPU/objdump.s
M llvm/test/Other/new-pm-O0-defaults.ll
M llvm/test/Other/new-pm-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
M llvm/test/ThinLTO/AArch64/aarch64_inline.ll
M llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions1.ll
M llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions2.ll
M llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions3.ll
M llvm/test/ThinLTO/X86/ctor-dtor-alias.ll
M llvm/test/ThinLTO/X86/ctor-dtor-alias2.ll
M llvm/test/ThinLTO/X86/deadstrip.ll
M llvm/test/ThinLTO/X86/devirt_function_alias.ll
M llvm/test/ThinLTO/X86/devirt_function_alias2.ll
M llvm/test/ThinLTO/X86/devirt_pure_virtual_base.ll
M llvm/test/ThinLTO/X86/devirt_vcall_vis_public.ll
M llvm/test/ThinLTO/X86/distributed_import.ll
M llvm/test/ThinLTO/X86/funcattrs-prop-exported-internal.ll
M llvm/test/ThinLTO/X86/funcattrs-prop-unknown.ll
M llvm/test/ThinLTO/X86/funcattrs-prop-weak.ll
M llvm/test/ThinLTO/X86/globals-import.ll
M llvm/test/ThinLTO/X86/hidden-escaped-symbols-alt.ll
M llvm/test/ThinLTO/X86/hidden-escaped-symbols.ll
M llvm/test/ThinLTO/X86/import-ro-constant.ll
M llvm/test/ThinLTO/X86/index-const-prop-alias.ll
M llvm/test/ThinLTO/X86/index-const-prop.ll
M llvm/test/ThinLTO/X86/linkonce_resolution_comdat.ll
M llvm/test/ThinLTO/X86/memprof-dups.ll
M llvm/test/ThinLTO/X86/memprof_callee_type_mismatch.ll
M llvm/test/ThinLTO/X86/memprof_imported_internal.ll
M llvm/test/ThinLTO/X86/memprof_imported_internal2.ll
M llvm/test/ThinLTO/X86/prevailing_weak_globals_import.ll
M llvm/test/ThinLTO/X86/visibility-elf.ll
M llvm/test/ThinLTO/X86/visibility-macho.ll
M llvm/test/ThinLTO/X86/weak_resolution.ll
M llvm/test/ThinLTO/X86/windows-vftable.ll
M llvm/test/ThinLTO/X86/writeonly.ll
A llvm/test/Transforms/AssignGUID/assign_guid.ll
M llvm/test/Transforms/ConstantMerge/merge-dbg.ll
M llvm/test/Transforms/ConstraintElimination/constraint-overflow.ll
M llvm/test/Transforms/ConstraintElimination/induction-condition-in-loop-exit.ll
A llvm/test/Transforms/DFAJumpThreading/br-debuglocs.ll
A llvm/test/Transforms/DFAJumpThreading/br-debuglocs2.ll
A llvm/test/Transforms/DropUnnecessaryAssumes/duplicate-affected-value.ll
M llvm/test/Transforms/EmbedBitcode/embed-wpd.ll
M llvm/test/Transforms/EmbedBitcode/embed.ll
M llvm/test/Transforms/FunctionImport/funcimport-debug-retained-nodes.ll
M llvm/test/Transforms/FunctionImport/funcimport.ll
M llvm/test/Transforms/GVN/invariant-load-intrinsic.ll
A llvm/test/Transforms/GlobalMerge/guid.ll
A llvm/test/Transforms/IndVarSimplify/eliminate-max-from-min-exit.ll
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-cmpeq.ll
M llvm/test/Transforms/InstCombine/invariant-load-like-sink.ll
M llvm/test/Transforms/InstCombine/rotate.ll
A llvm/test/Transforms/InstCombine/zext-sub-trunc.ll
M llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check.ll
A llvm/test/Transforms/LoopInterchange/debug-record-after-phi.ll
M llvm/test/Transforms/LoopVectorize/AArch64/alias-mask.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fold-tail-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
A llvm/test/Transforms/LoopVectorize/AArch64/sve-interleave-low-vf-cost.ll
A llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-access-low-vf.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-epilogue-vec.ll
A llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-vscale-x-UF-step.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/AArch64/widen-gep-all-indices-invariant.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-saddsatcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/predicated-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/VPlan/X86/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/VPlan/buildvector-first-lane-only.ll
M llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
M llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
M llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-sink-replicate-region.ll
M llvm/test/Transforms/LoopVectorize/VPlan/tail-folding.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-before-after-all.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-alias-mask.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions-tail-folded.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-sink-scalars-and-merge.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-inbounds-flags-for-reverse-vector-pointer.ll
M llvm/test/Transforms/LoopVectorize/X86/fold-tail-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/test/Transforms/LoopVectorize/X86/pr81872.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorize-interleaved-accesses-gap.ll
M llvm/test/Transforms/LoopVectorize/alias-mask.ll
M llvm/test/Transforms/LoopVectorize/early-exit-umin-trip-count.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/optsize.ll
M llvm/test/Transforms/LoopVectorize/pr51614-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/reduction-order.ll
M llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll
M llvm/test/Transforms/LoopVectorize/select-reduction.ll
A llvm/test/Transforms/LoopVectorize/simplify-reverse-reverse.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
M llvm/test/Transforms/LoopVectorize/store-reduction-results-in-tail-folded-loop.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-div.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-replicate-region.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
M llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
A llvm/test/Transforms/LoopVectorize/versioning-dead-load.ll
M llvm/test/Transforms/LoopVectorize/vscale-cost.ll
M llvm/test/Transforms/LowerTypeTests/cfi-icall-alias.ll
M llvm/test/Transforms/LowerTypeTests/export-icall.ll
M llvm/test/Transforms/ObjCARC/test_autorelease_pool.ll
M llvm/test/Transforms/PGOProfile/thinlto_indirect_call_promotion.ll
M llvm/test/Transforms/PhaseOrdering/ARM/arm_add_q7.ll
M llvm/test/Transforms/PhaseOrdering/X86/avg.ll
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
M llvm/test/Transforms/PhaseOrdering/speculative-devirt-then-inliner.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/fma-reduce-regression.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/long-non-power-of-2.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/partial-vec-invalid-cost.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
A llvm/test/Transforms/SLPVectorizer/X86/ashr-main-opcode-copyables.ll
M llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-postpone-for-dependency.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-reused-with-bv-subvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/c-ray.ll
M llvm/test/Transforms/SLPVectorizer/X86/commutable-node-with-non-sched-parent.ll
M llvm/test/Transforms/SLPVectorizer/X86/commutative-copyable-external-phi-use.ll
M llvm/test/Transforms/SLPVectorizer/X86/copyable-operand-non-scheduled-parent-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/debug-info-salvage.ll
M llvm/test/Transforms/SLPVectorizer/X86/delayed-gather-emission.ll
A llvm/test/Transforms/SLPVectorizer/X86/mul-shl-nsw-intmin.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-subvectors-insert.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-parent-multi-copyables.ll
M llvm/test/Transforms/SLPVectorizer/X86/poor-throughput-seeds.ll
M llvm/test/Transforms/SLPVectorizer/X86/reassociate-ops.ll
M llvm/test/Transforms/SLPVectorizer/X86/recalc-copyable-operand-deps-shared-inst.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-ordered-values-update.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-reorder-reshuffle.ll
M llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
M llvm/test/Transforms/SampleProfile/ctxsplit.ll
R llvm/test/Transforms/SampleProfile/icp_target_feature.ll
A llvm/test/Transforms/SimpleLoopUnswitch/trivial-unswitch-convergent.ll
M llvm/test/Transforms/SimplifyCFG/hoist-with-metadata.ll
M llvm/test/Transforms/SimplifyCFG/rangereduce.ll
M llvm/test/Transforms/Sink/invariant-load.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal-typeid.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal1.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal2.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc-internal.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/unsplittable.ll
A llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops-i1.ll
M llvm/test/Transforms/WholeProgramDevirt/branch-funnel-profile.ll
M llvm/test/Transforms/WholeProgramDevirt/export-single-impl.ll
M llvm/test/Transforms/WholeProgramDevirt/export-vcp.ll
M llvm/test/Transforms/WholeProgramDevirt/virtual-const-prop-interposable.ll
A llvm/test/Verifier/invariant-load-metadata-invalid.ll
A llvm/test/tools/dsymutil/X86/dwarf6-language-name-odr.test
M llvm/test/tools/gold/X86/devirt_vcall_vis_export_dynamic.ll
M llvm/test/tools/gold/X86/devirt_vcall_vis_public.ll
M llvm/test/tools/gold/X86/devirt_vcall_vis_shared_def.ll
M llvm/test/tools/gold/X86/thinlto_weak_library.ll
M llvm/test/tools/gold/X86/thinlto_weak_resolution.ll
M llvm/test/tools/gold/X86/v1.16/devirt_vcall_vis_export_dynamic.ll
A llvm/test/tools/llubi/inttoptr_ptrtoint_constantexpr.ll
M llvm/test/tools/llvm-ar/arm64x-hybridobj.yaml
M llvm/test/tools/llvm-lib/arm64x-hybridobj.yaml
M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s
A llvm/test/tools/llvm-objdump/AMDGPU/arch-amdgcn-legacy-arch-name.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s
A llvm/test/tools/llvm-objdump/ELF/AMDGPU/subarch-triple.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
M llvm/test/tools/llvm-objdump/Offloading/fatbin-coff-compress.test
A llvm/test/tools/llvm-objdump/Offloading/fatbin-magic-collision.test
M llvm/test/tools/llvm-readobj/COFF/arm64x-hybridobj.yaml
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
M llvm/tools/llubi/lib/Context.cpp
M llvm/tools/llvm-debuginfod-find/llvm-debuginfod-find.cpp
M llvm/tools/llvm-link/llvm-link.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/opt/NewPMDriver.cpp
M llvm/tools/opt/optdriver.cpp
M llvm/unittests/Analysis/ScalarEvolutionTest.cpp
M llvm/unittests/Analysis/ValueTrackingTest.cpp
M llvm/unittests/Demangle/CMakeLists.txt
A llvm/unittests/Demangle/MicrosoftDemangleTest.cpp
M llvm/unittests/IR/IRBuilderTest.cpp
M llvm/unittests/Object/ELFObjectFileTest.cpp
M llvm/unittests/ProfileData/SampleProfTest.cpp
M llvm/unittests/Support/raw_ostream_test.cpp
M llvm/unittests/TargetParser/Host.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/unittests/TargetParser/TripleTest.cpp
M llvm/unittests/Transforms/Utils/DebugifyTest.cpp
M llvm/unittests/Transforms/Vectorize/VPDomTreeTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/utils/UpdateTestChecks/asm.py
M llvm/utils/git/ids-check-helper.py
M mlir/cmake/modules/CMakeLists.txt
M mlir/cmake/modules/MLIRConfig.cmake.in
M mlir/include/mlir/Bindings/Python/IRCore.h
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationEnums.td
M mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.td
A mlir/include/mlir/Dialect/Bufferization/Transforms/StaticMemoryPlanning.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/OpenACC/Analysis/OpenACCSupport.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
A mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsType.h
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.h
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/include/mlir/Dialect/OpenMP/Transforms/Passes.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.h
M mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
M mlir/include/mlir/IR/Block.h
M mlir/include/mlir/IR/Region.h
M mlir/include/mlir/IR/RegionGraphTraits.h
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
M mlir/lib/Conversion/ComplexToSPIRV/ComplexToSPIRV.cpp
M mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp
M mlir/lib/Dialect/Bufferization/Transforms/CMakeLists.txt
M mlir/lib/Dialect/Bufferization/Transforms/StaticMemoryPlannerAnalysis.cpp
A mlir/lib/Dialect/Bufferization/Transforms/StaticMemoryPlanning.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/lib/Dialect/OpenACC/Analysis/OpenACCSupport.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCComputeLowering.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCRecipeMaterialization.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCSpecializeForDevice.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCSpecializeForHost.cpp
M mlir/lib/Dialect/OpenACC/Utils/CMakeLists.txt
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
A mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsType.cpp
M mlir/lib/Dialect/OpenMP/Transforms/CMakeLists.txt
A mlir/lib/Dialect/OpenMP/Transforms/HostOpFiltering.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToLaneDistribute.cpp
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/lib/IR/Region.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Transforms/Utils/CMakeLists.txt
M mlir/test/Conversion/ArithToSPIRV/arith-to-spirv.mlir
M mlir/test/Conversion/ArithToSPIRV/fast-math.mlir
M mlir/test/Conversion/ComplexToSPIRV/complex-to-spirv.mlir
M mlir/test/Dialect/ArmSME/vector-legalization.mlir
A mlir/test/Dialect/Bufferization/Transforms/static-memory-planner-best-fit.mlir
M mlir/test/Dialect/LLVMIR/nvvm_check_target_sm.mlir
M mlir/test/Dialect/Linalg/vectorization/extract.mlir
M mlir/test/Dialect/OpenACC/acc-recipe-materialization-reduction.mlir
M mlir/test/Dialect/OpenACC/acc-specialize-for-device.mlir
M mlir/test/Dialect/OpenACC/acc-specialize-for-host-fallback.mlir
M mlir/test/Dialect/OpenACC/ops.mlir
A mlir/test/Dialect/OpenMP/host-op-filtering.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
M mlir/test/Dialect/XeGPU/sg-to-lane-distribute-unit.mlir
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-ld.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-st.mlir
A mlir/test/Target/LLVMIR/omptarget-declare-target-all-device-types-device.mlir
M mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-device.mlir
M mlir/unittests/Dialect/OpenACC/CMakeLists.txt
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
A mlir/unittests/Dialect/OpenACC/OpenACCUtilsTypeTest.cpp
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/include/RecordReplay.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/common/src/RecordReplay.cpp
A offload/test/Inputs/declare-target-common-block-sub.f90
M offload/test/lit.cfg
A offload/test/offloading/fortran/declare-target-common-block-2.f90
A offload/test/offloading/fortran/declare-target-common-block-main.f90
A offload/test/tools/omp-kernel-replay/record-replay-ir-bitcode.cpp
M offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp
M openmp/runtime/src/kmp_dispatch.h
M orc-rt/CMakeLists.txt
M orc-rt/include/CMakeLists.txt
M orc-rt/include/orc-rt-c/Compiler.h
A orc-rt/include/orc-rt-c/Logging.h
M orc-rt/include/orc-rt-c/config.h.in
M orc-rt/test/CMakeLists.txt
R orc-rt/test/init.test
R orc-rt/test/lit.cfg.py
R orc-rt/test/lit.site.cfg.py.in
A orc-rt/test/regression/init.test
A orc-rt/test/regression/lit.cfg.py
A orc-rt/test/regression/lit.site.cfg.py.in
A orc-rt/test/regression/smoke-check.test
A orc-rt/test/tools/CMakeLists.txt
A orc-rt/test/tools/orc-rt-smoke-check.cpp
A orc-rt/test/unit/AllocActionTest.cpp
A orc-rt/test/unit/AllocActionTestUtils.h
A orc-rt/test/unit/BitmaskEnumTest.cpp
A orc-rt/test/unit/BootstrapInfoTest.cpp
A orc-rt/test/unit/CMakeLists.txt
A orc-rt/test/unit/CallSPSCITest.cpp
A orc-rt/test/unit/CallableTraitsHelperTest.cpp
A orc-rt/test/unit/CommonTestUtils.h
A orc-rt/test/unit/DirectCaller.h
A orc-rt/test/unit/EndianTest.cpp
A orc-rt/test/unit/ErrorCAPITest.cpp
A orc-rt/test/unit/ErrorExceptionInteropTest.cpp
A orc-rt/test/unit/ErrorTest.cpp
A orc-rt/test/unit/ExecutorAddressTest.cpp
A orc-rt/test/unit/ExecutorProcessInfoTest.cpp
A orc-rt/test/unit/InProcessControllerAccessTest.cpp
A orc-rt/test/unit/Inputs/NativeDylibManagerTestLib.cpp
A orc-rt/test/unit/IntervalMapTest.cpp
A orc-rt/test/unit/IntervalSetTest.cpp
A orc-rt/test/unit/LockedAccessTest.cpp
A orc-rt/test/unit/LoggingTest.cpp
A orc-rt/test/unit/MacroUtilsTest.cpp
A orc-rt/test/unit/MathTest.cpp
A orc-rt/test/unit/MemoryAccessSPSCITest.cpp
A orc-rt/test/unit/MemoryFlagsTest.cpp
A orc-rt/test/unit/NativeDylibManagerSPSCITest.cpp
A orc-rt/test/unit/NativeDylibManagerTest.cpp
A orc-rt/test/unit/QueueingRunnerTest.cpp
A orc-rt/test/unit/RTTITest.cpp
A orc-rt/test/unit/SPSAllocActionTest.cpp
A orc-rt/test/unit/SPSMemoryFlagsTest.cpp
A orc-rt/test/unit/SPSWrapperFunctionBufferTest.cpp
A orc-rt/test/unit/SPSWrapperFunctionTest.cpp
A orc-rt/test/unit/SessionTest.cpp
A orc-rt/test/unit/SimpleNativeMemoryMapSPSCITest.cpp
A orc-rt/test/unit/SimpleNativeMemoryMapTest.cpp
A orc-rt/test/unit/SimplePackedSerializationTest.cpp
A orc-rt/test/unit/SimplePackedSerializationTestUtils.h
A orc-rt/test/unit/SimpleSymbolTableTest.cpp
A orc-rt/test/unit/StandaloneMachOUnwindInfoRegistrarTest.cpp
A orc-rt/test/unit/TaskGroupTest.cpp
A orc-rt/test/unit/ThreadPoolRunnerTest.cpp
A orc-rt/test/unit/WrapperFunctionBufferTest.cpp
A orc-rt/test/unit/bind-test.cpp
A orc-rt/test/unit/bit-test.cpp
A orc-rt/test/unit/iterator_range-test.cpp
M orc-rt/test/unit/lit.cfg.py
A orc-rt/test/unit/move_only_function-test.cpp
A orc-rt/test/unit/scope_exit-test.cpp
A orc-rt/test/unit/span-test.cpp
R orc-rt/unittests/AllocActionTest.cpp
R orc-rt/unittests/AllocActionTestUtils.h
R orc-rt/unittests/BitmaskEnumTest.cpp
R orc-rt/unittests/BootstrapInfoTest.cpp
R orc-rt/unittests/CMakeLists.txt
R orc-rt/unittests/CallSPSCITest.cpp
R orc-rt/unittests/CallableTraitsHelperTest.cpp
R orc-rt/unittests/CommonTestUtils.h
R orc-rt/unittests/DirectCaller.h
R orc-rt/unittests/EndianTest.cpp
R orc-rt/unittests/ErrorCAPITest.cpp
R orc-rt/unittests/ErrorExceptionInteropTest.cpp
R orc-rt/unittests/ErrorTest.cpp
R orc-rt/unittests/ExecutorAddressTest.cpp
R orc-rt/unittests/ExecutorProcessInfoTest.cpp
R orc-rt/unittests/InProcessControllerAccessTest.cpp
R orc-rt/unittests/Inputs/NativeDylibManagerTestLib.cpp
R orc-rt/unittests/IntervalMapTest.cpp
R orc-rt/unittests/IntervalSetTest.cpp
R orc-rt/unittests/LockedAccessTest.cpp
R orc-rt/unittests/MacroUtilsTest.cpp
R orc-rt/unittests/MathTest.cpp
R orc-rt/unittests/MemoryAccessSPSCITest.cpp
R orc-rt/unittests/MemoryFlagsTest.cpp
R orc-rt/unittests/NativeDylibManagerSPSCITest.cpp
R orc-rt/unittests/NativeDylibManagerTest.cpp
R orc-rt/unittests/QueueingRunnerTest.cpp
R orc-rt/unittests/RTTITest.cpp
R orc-rt/unittests/SPSAllocActionTest.cpp
R orc-rt/unittests/SPSMemoryFlagsTest.cpp
R orc-rt/unittests/SPSWrapperFunctionBufferTest.cpp
R orc-rt/unittests/SPSWrapperFunctionTest.cpp
R orc-rt/unittests/SessionTest.cpp
R orc-rt/unittests/SimpleNativeMemoryMapSPSCITest.cpp
R orc-rt/unittests/SimpleNativeMemoryMapTest.cpp
R orc-rt/unittests/SimplePackedSerializationTest.cpp
R orc-rt/unittests/SimplePackedSerializationTestUtils.h
R orc-rt/unittests/SimpleSymbolTableTest.cpp
R orc-rt/unittests/StandaloneMachOUnwindInfoRegistrarTest.cpp
R orc-rt/unittests/TaskGroupTest.cpp
R orc-rt/unittests/ThreadPoolRunnerTest.cpp
R orc-rt/unittests/WrapperFunctionBufferTest.cpp
R orc-rt/unittests/bind-test.cpp
R orc-rt/unittests/bit-test.cpp
R orc-rt/unittests/iterator_range-test.cpp
R orc-rt/unittests/move_only_function-test.cpp
R orc-rt/unittests/scope_exit-test.cpp
R orc-rt/unittests/span-test.cpp
M runtimes/CMakeLists.txt
M utils/bazel/MODULE.bazel
M utils/bazel/MODULE.bazel.lock
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/clang/unittests/BUILD.bazel
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/OpenACC/Analysis/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
A utils/bazel/llvm-project-overlay/libc/test/src/arpa/inet/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/config.bzl
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/docs/llvm_sphinx/__init__.py
Log Message:
-----------
Rebase, address comments
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/f5584e526eb4...34149b085c63
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