[all-commits] [llvm/llvm-project] 841e01: [ISEL] Fix x86-64 instruction selection bug leakin...

[Ammar Askar via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 841e01daa0126941cd3b1b322b3e3b5605fcd03c
      https://github.com/llvm/llvm-project/commit/841e01daa0126941cd3b1b322b3e3b5605fcd03c
  Author: Ammar Askar <aaskar at google.com>
  Date:   2026-07-09 (Thu, 09 Jul 2026)

  Changed paths:
    M llvm/lib/Target/X86/X86InstrCompiler.td
    M llvm/test/CodeGen/X86/insert.ll

  Log Message:
  -----------
  [ISEL] Fix x86-64 instruction selection bug leaking upper 32 bits (#205600)

The x86 backend had optimization patterns that matched:
  `(or (and GR32:$dst, -256), (i32 (zextloadi8 addr:$src)))`
and lowered it to:
  `(INSERT_SUBREG (i32 (COPY $dst)), (MOV8rm  i8mem:$src), sub_8bit)`

INSERT_SUBREG for sub_8bit emits a movb instruction which preserves the
upper 56 bits. Now, if the GR32 dst came from a node that does not zero
the upper 32 bits (like IMPLICIT_DEF or EXTRACT_SUBREG), those upper 32
bits would be leaked into the resulting register without being zeroed.

This fixes it by ensuring the input operand satisfies def32 which
requires the upper 32 bits of the register to be set.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications