[all-commits] [llvm/llvm-project] 7f3d91: [RISCV][MCA] Avoid deriving EMUL without SEW (#207...

[Zeyi Xu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7f3d91d14ae33a8206b536ac1ffe69565423ced3
      https://github.com/llvm/llvm-project/commit/7f3d91d14ae33a8206b536ac1ffe69565423ced3
  Author: Zeyi Xu <mitchell.xu2 at gmail.com>
  Date:   2026-07-09 (Thu, 09 Jul 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s

  Log Message:
  -----------
  [RISCV][MCA] Avoid deriving EMUL without SEW (#207986)

When only an LMUL instrument is active, SEW is unavailable. Avoid
deriving EMUL for vector memory instructions in that case and fall back
to the base scheduling class.

Closes #170118.



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