[all-commits] [llvm/llvm-project] 0a015c: [AMDGPU] Replace zext pattern from reg_sequence to...

[Guo Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0a015cc516abb7f54bcdd94763f44219b6298bd9
      https://github.com/llvm/llvm-project/commit/0a015cc516abb7f54bcdd94763f44219b6298bd9
  Author: Guo Chen <guochen2 at amd.com>
  Date:   2026-07-08 (Wed, 08 Jul 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
    M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
    M llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
    M llvm/test/CodeGen/AMDGPU/ctls.ll
    M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
    M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
    M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
    M llvm/test/CodeGen/AMDGPU/idot4u.ll
    M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
    M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
    M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
    M llvm/test/CodeGen/AMDGPU/mad.u16.ll
    M llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
    M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
    M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
    M llvm/test/CodeGen/AMDGPU/srl-bitcast-bv.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll

  Log Message:
  -----------
  [AMDGPU] Replace zext pattern from reg_sequence to cvt_u32_u16 (#208045)

Isel pattern putting imm inside reg_sequence create side effects when
register coalescer join these `copy` from imm
```
%1 = v_mov_b16_t16_e64 ...
%2.hi16 = copy %1
%2.lo16 = ....
...
%3.hi16 = copy %1
%3.lo16 = ....
....
%4.hi16 = copy %1
%4.lo16 = ....
```
to
```
%1 = v_mov_b16_t16_e64 ...
%2.hi16 = copy %1
%2.lo16 = ....
...
%2.lo16 = ... (reuse %2 and repeat)
....
```
When the number of copy increase this inserts a large number of WAR
hazzards on the reused virutal reg, and the machine scheduler bail out
getting higher reg pressure after sorting.

Beside this, replacing with cvt_u32_u16 provides better code quality



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