[all-commits] [llvm/llvm-project] 006429: [Hexagon] Fix 32-bit funnel shift miscompilation w...

[Brian Cain via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 006429da6ab9527e34c63df3f84517d385c30ef2
      https://github.com/llvm/llvm-project/commit/006429da6ab9527e34c63df3f84517d385c30ef2
  Author: Brian Cain <brian.cain at oss.qualcomm.com>
  Date:   2026-07-08 (Wed, 08 Jul 2026)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonPatterns.td
    A llvm/test/CodeGen/Hexagon/fshl-fshr-i32-mask.ll
    M llvm/test/CodeGen/Hexagon/funnel-shift.ll
    M llvm/test/CodeGen/Hexagon/rotate.ll

  Log Message:
  -----------
  [Hexagon] Fix 32-bit funnel shift miscompilation with register shift amounts (#205489)

The register-variable 32-bit funnel shifts and the i32 rotates that
lower through them, realize the shift as a 64-bit asl/lsr of the {hi,lo}
combine and take one word of the result. That identity only holds for a
shift amount in [0, 31], and llvm.fshl/fshr define the amount to be
taken modulo 32. The register-form variable shift does not reduce the
amount modulo the operand width, it treats the low 7 bits as a signed
amount in [-64, 63]. So the raw, unreduced amount must be masked with
#31 before the 64-bit shift.

Without the mask, counts >= 32 or "negative" counts are miscompiled: a
count of 63 shifts left by 63, 64 becomes -64 and shifts the value out
entirely, and -1 becomes an arithmetic right shift by 1. In-range counts
0..31 come out correct, which is why a test that only sweeps 0..31 does
not catch it. This is exactly the i32.rotl/i32.rotr miscompile that
caused the WAMR Wasm spec-test suites (which invoke rotates with counts
of 32, 33, and -1) to be skipped on Hexagon.

Fix by masking the amount with (A2_andir $Ru, 31), mirroring the masking
the 64-bit patterns already use. This completes the 32-bit case left
unaddressed by 4fffee037520 ("[Hexagon] Fix 64-bit funnel shift
miscompilation with register shift amounts", #183669), which fixed only
the FShl64r/FShr64r width.



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