[all-commits] [llvm/llvm-project] 81b2e4: [SDAG][NVPTX] Enable custom legalization of v1 typ...

[Pradeep Kumar via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 81b2e47b0d29526a7bb8a7674af61acff019a5a4
      https://github.com/llvm/llvm-project/commit/81b2e47b0d29526a7bb8a7674af61acff019a5a4
  Author: Pradeep Kumar <pradeepku at nvidia.com>
  Date:   2026-07-08 (Wed, 08 Jul 2026)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsNVVM.td
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
    M llvm/test/CodeGen/NVPTX/tcgen05-ld.ll
    M llvm/test/CodeGen/NVPTX/tcgen05-st.ll
    M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
    M mlir/test/Dialect/LLVMIR/nvvm_check_target_sm.mlir
    M mlir/test/Target/LLVMIR/nvvm/tcgen05-ld.mlir
    M mlir/test/Target/LLVMIR/nvvm/tcgen05-st.mlir

  Log Message:
  -----------
  [SDAG][NVPTX] Enable custom legalization of v1 type for Intrinsic results and operands (#203237)

This commit enables custom legalization for v1 types for intrinsic results and operand by calling CustomLowerNode which gives the target a chance to custom handle the node before scalarizing

To demonstrate, I have used tcgen05.ld/st intrinsics which previously used a scalar i32 type while all wider variants used vector types

Assisted by: Claude Code



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications