[all-commits] [llvm/llvm-project] 188702: [DAGCombiner] Fold smax(X, -1)/smin(X, 0) to bitwi...

[Aayush Shrivastava via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 188702eeb742a66b8cf32722ca4d8a8d64e77f83
      https://github.com/llvm/llvm-project/commit/188702eeb742a66b8cf32722ca4d8a8d64e77f83
  Author: Aayush Shrivastava <iamaayushrivastava at gmail.com>
  Date:   2026-07-08 (Wed, 08 Jul 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    A llvm/test/CodeGen/AArch64/smax-allones.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/WebAssembly/fpclamptosat.ll
    M llvm/test/CodeGen/X86/combine-smax.ll
    M llvm/test/CodeGen/X86/combine-smin.ll
    M llvm/test/CodeGen/X86/known-never-zero.ll
    M llvm/test/CodeGen/X86/probe-stack-eflags.ll

  Log Message:
  -----------
  [DAGCombiner] Fold smax(X, -1)/smin(X, 0) to bitwise shift forms (#206242)

Fixes #206153

`smax(X, -1) = or(X,  ashr(X, BW-1))`
`smin(X,  0) = and(X, ashr(X, BW-1))`

`ashr(X, BW-1)` sign-extends the sign bit to all bits 0 for X≥0, -1 for
X<0. OR-ing with X yields X or -1 = smax(X,-1), AND-ing yields 0 or X =
smin(X,0). Both replace a `compare+cmov` with two cheap bitwise
instructions.

The fold is unconditional (not gated on code size), firing whenever the
target has no native `SMAX/SMIN` instruction for the type
(`isOperationExpand`), the type is legal (`isTypeLegal`), and the input
is not a min/max chain (preserving RISCV-P `sati` saturation patterns).



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications