[all-commits] [llvm/llvm-project] 047011: [LLVM][CodeGen][SVE] Make use of predicate load/st...

[Paul Walker via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 047011710642a63471fcdba64f009a0125f715bf
      https://github.com/llvm/llvm-project/commit/047011710642a63471fcdba64f009a0125f715bf
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2026-07-08 (Wed, 08 Jul 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
    A llvm/test/CodeGen/AArch64/sve-pred-ldst.ll

  Log Message:
  -----------
  [LLVM][CodeGen][SVE] Make use of predicate load/store "mul vl" addressing mode. (#206997)



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