[all-commits] [llvm/llvm-project] e11878: [AArch64][DAG] Port adde and sube combine to AArch...

[zip-stack-debug via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e1187834d342ae7890884dbc1ef69de7b5d9fdc1
      https://github.com/llvm/llvm-project/commit/e1187834d342ae7890884dbc1ef69de7b5d9fdc1
  Author: zip-stack-debug <doremyalt at gmail.com>
  Date:   2026-07-08 (Wed, 08 Jul 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/div-i256.ll
    M llvm/test/CodeGen/AArch64/sbc-add-constant.ll

  Log Message:
  -----------
  [AArch64][DAG] Port adde and sube combine to AArch64 (#202227)

Same principles apply in AArch64 as they do in ARM.



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