[all-commits] [llvm/llvm-project] b0d354: [MIR] Serialize/Deserialize MachineInstr::LRSplit ...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Tue Jul 7 11:55:57 PDT 2026
Branch: refs/heads/users/alexey-bataev/spr/slp-enable-full-non-power-of-2-vectorization-by-default
Home: https://github.com/llvm/llvm-project
Commit: b0d35497b666b3e0c0c4244c1f8c19f2cfdc1fb2
https://github.com/llvm/llvm-project/commit/b0d35497b666b3e0c0c4244c1f8c19f2cfdc1fb2
Author: Quentin Colombet <quentin.colombet at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/MIRParser/MILexer.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.h
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/test/CodeGen/AArch64/nested-iv-regalloc.mir
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir
M llvm/test/CodeGen/AMDGPU/dead_bundle.mir
M llvm/test/CodeGen/AMDGPU/extend-phi-subrange-not-in-parent.mir
M llvm/test/CodeGen/AMDGPU/greedy-global-heuristic.mir
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-agpr-negative-tests.mir
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av.mir
M llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir
M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
M llvm/test/CodeGen/AMDGPU/regalloc-fail-unsatisfiable-overlapping-tuple-hints.mir
M llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir
M llvm/test/CodeGen/AMDGPU/split-liverange-overlapping-copies.mir
M llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
M llvm/test/CodeGen/AMDGPU/splitkit-do-not-undo-subclass-split-with-remat.mir
M llvm/test/CodeGen/AMDGPU/splitkit.mir
M llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
A llvm/test/CodeGen/MIR/AMDGPU/lr-split-flag.mir
M llvm/test/CodeGen/RISCV/pr176001.ll
M llvm/test/CodeGen/X86/AMX/amx-greedy-ra-spill-shape.ll
M llvm/test/CodeGen/X86/apx/foldmemory.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
M llvm/test/DebugInfo/MIR/X86/dvl-livedebugvars-movements.mir
M llvm/test/DebugInfo/MIR/X86/dvl-livedebugvars-stackptr.mir
M llvm/utils/UpdateTestChecks/mir.py
Log Message:
-----------
[MIR] Serialize/Deserialize MachineInstr::LRSplit flag (#197362)
The LRSplit MachineInstr flag is set by SplitKit on copies inserted for
live-range splitting.
Until now the flag had no MIR-text representation.
This patch fixes that so that it gets easier to reproduce/capture issues
that involves SplitKit.
Round-trip coverage in
llvm/test/CodeGen/MIR/AMDGPU/lr-split-flag.mir.
Commit: c35cba42e67284a1b6b8609f20782f6d8c692a6c
https://github.com/llvm/llvm-project/commit/c35cba42e67284a1b6b8609f20782f6d8c692a6c
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/include/llvm/SandboxIR/PassManager.h
M llvm/unittests/SandboxIR/PassTest.cpp
Log Message:
-----------
[SandboxIR] Fix pass pipeline parsing after aux arguments (#207237)
## Summary
- Fix `sandboxir::PassManager::setPassPipeline` to resume scanning pass
names after a pass aux argument when the next token is a delimiter.
- Add a unit test covering flat pipelines like `foo(aux1),bar`.
This fixes parsing of region pass pipelines such as
`bottom-up-vec(top-down),tr-accept` that will be used by the
SandboxVectorizer.
## Test plan
- [x] `ninja SandboxIRTests`
- [x] `./unittests/SandboxIR/SandboxIRTests
--gtest_filter=PassTest.SetPassPipeline`
Made with [Cursor](https://cursor.com)
Co-authored-by: Cursor <cursoragent at cursor.com>
Commit: 20e12152f9b218c42791151f0bca93a5a1763b64
https://github.com/llvm/llvm-project/commit/20e12152f9b218c42791151f0bca93a5a1763b64
Author: Jason Eckhardt <jeckhardt at nvidia.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64CallingConvention.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
M llvm/lib/Target/ARC/ARCISelLowering.cpp
M llvm/lib/Target/ARM/ARMCallingConv.cpp
M llvm/lib/Target/AVR/AVRISelLowering.cpp
M llvm/lib/Target/BPF/BPFISelLowering.cpp
M llvm/lib/Target/CSKY/CSKYISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Lanai/LanaiISelLowering.cpp
M llvm/lib/Target/M68k/M68kISelLowering.cpp
M llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCCallingConv.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/VE/VEISelLowering.cpp
M llvm/lib/Target/X86/X86CallingConv.cpp
M llvm/lib/Target/XCore/XCoreISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/utils/TableGen/CallingConvEmitter.cpp
Log Message:
-----------
[TableGen][CC][NFC] Emit idiomatic guards for CallingConv. (#207758)
Emit independent guards for the two existing sections rather than the
if-else done today. This is in preparation for adding other sections
that must be includable exclusive of the other sections.
This also eliminates the current asymmetry between the automatic
IfGuardEmitter for the "if" portion vs the manually emitted "else"
section.
Commit: 78bc590bbc89aa868bcee35982dd3cf70cebea64
https://github.com/llvm/llvm-project/commit/78bc590bbc89aa868bcee35982dd3cf70cebea64
Author: Stefan Mada <smada at nvidia.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/lib/IR/AsmWriter.cpp
A llvm/test/CodeGen/NVPTX/intrinsic-immarg-print-mismatched-signature.ll
Log Message:
-----------
[IR][NVVM] Fixed null pointer deference in AsmWriter pretty printer (#207223)
ASMWriter can deference a null pointer on intrinsics with pretty printed
args when those intrinsics are called with an invalid number of
arguments. This check avoids the null dereference and turns this into a
graceful failure.
Commit: 9c823964dd43645162d361b16d2ddedc381f5d2d
https://github.com/llvm/llvm-project/commit/9c823964dd43645162d361b16d2ddedc381f5d2d
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXLowerAlloca.cpp
M llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
M llvm/lib/Target/NVPTX/NVPTXLowerUnreachable.cpp
Log Message:
-----------
[NFC][LLVM][NVPTX] Initialize pass-ids to zero (#207547)
Initialize pass::ID values for various passes to canonical zero instead
of 1.
Commit: 2e75acd861aa78755c7a57ab8eca63fde916497a
https://github.com/llvm/llvm-project/commit/2e75acd861aa78755c7a57ab8eca63fde916497a
Author: Aditya Medhane <sherlockedaditya at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M libc/test/UnitTest/ErrnoSetterMatcher.h
Log Message:
-----------
[libc][test] Remove internal linkage from ErrnoSetterMatcher helpers (NFC) (#207707)
`Succeeds`, `Fails`, and `returns` are static function templates in a
header, so any test TU that includes it without using all of them trips
`-Wunused-template`. Dropping static also matches the neighboring EQ/NE
helpers, which are already non-static.
Part of #202945.
Commit: 42746081459775eb85879cc09361a316ac9e0ea2
https://github.com/llvm/llvm-project/commit/42746081459775eb85879cc09361a316ac9e0ea2
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp
M llvm/test/CodeGen/AMDGPU/opencl-printf.ll
Log Message:
-----------
[AMDGPU] Fix printf %s buffer slot oversized when strlen % 4 == 0 (#207772)
The metadata slot for a constant string %s used alignTo(strlen + 1, 4),
but the store loop only writes ceil(strlen / 4) dwords (no trailing
NUL), so every following argument was read from offset shifted by +4
Commit: 0f0b1c76a4d84594fef4de8ae5c49aa565d8bab0
https://github.com/llvm/llvm-project/commit/0f0b1c76a4d84594fef4de8ae5c49aa565d8bab0
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M .github/workflows/libcxx-run-benchmarks.yml
Log Message:
-----------
[libc++] Run the libcxx-run-benchmarks action on macOS in addition to Linux (#207780)
The libcxx-run-benchmarks action is triggered when a specially formatted
comment is posted on a PR, requesting benchmarks to be run against that
PR. This patch expands the Github action so it also runs benchmarks on
the macOS CI resources that were added recently.
Commit: 804a081a797c953b86503ead745dfde96f1c61c9
https://github.com/llvm/llvm-project/commit/804a081a797c953b86503ead745dfde96f1c61c9
Author: Ömer Sinan Ağacan <omeragacan at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
Log Message:
-----------
[GlobalISel][AArch64] Legalize PHIs with vectors smaller than 64-bits (#207356)
New legalization rule added as the last to not change legalization of
small vectors in existing tests.
Commit: 82d27f67b6aad3bf72e9db610ab5b6984cb02b76
https://github.com/llvm/llvm-project/commit/82d27f67b6aad3bf72e9db610ab5b6984cb02b76
Author: Nathan Corbyn <n_corbyn at apple.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
R clang/test/Interpreter/emulated-tls.cpp
M llvm/lib/ExecutionEngine/Orc/Layer.cpp
Log Message:
-----------
Revert "[ORC] Track __emutls_t definitions in IRMaterializationUnit" (#207775)
Commit: 96904e83cf69b0a02a5fb7dece9b258f562205e0
https://github.com/llvm/llvm-project/commit/96904e83cf69b0a02a5fb7dece9b258f562205e0
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M compiler-rt/lib/scudo/standalone/tests/chunk_test.cpp
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/lib/scudo/standalone/tests/flags_test.cpp
M compiler-rt/lib/scudo/standalone/tests/map_test.cpp
M compiler-rt/lib/scudo/standalone/tests/memtag_test.cpp
M compiler-rt/lib/scudo/standalone/tests/report_test.cpp
M compiler-rt/lib/scudo/standalone/tests/scudo_unit_test.h
M compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp
M compiler-rt/lib/scudo/standalone/tests/wrappers_c_test.cpp
M compiler-rt/lib/scudo/standalone/tests/wrappers_cpp_test.cpp
Log Message:
-----------
[scudo] Make death tests use SCUDO_XXX_DEATH_TEST. (#206196)
On Android, we want to disable the tombstone generation on expected
crashes to speed up running the tests. Also, this means that any
tombstone files will be real crashes and it's not necessary to search
for the right tombstone if one of the tests crashes unexpectedly.
In order to do the above, add SCUDO_EXPECT_DEATH_TEST and
SCUDO_ASSERT_DEATH_TEST that will disable tombstoned on Android but do
nothing on all other platforms.
Commit: 69ee64790ed69555264a200a3ae95d644a649e42
https://github.com/llvm/llvm-project/commit/69ee64790ed69555264a200a3ae95d644a649e42
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
A llvm/test/Transforms/InstCombine/frexp-implied-exponent-range-dominating-conditions.ll
Log Message:
-----------
InstCombine: Add baseline test for implied frexp exponent ranges (#206926)
Commit: d1eae28e79d33a4f85bf16a09cbb90aa9b6848e4
https://github.com/llvm/llvm-project/commit/d1eae28e79d33a4f85bf16a09cbb90aa9b6848e4
Author: Kamlesh Kumar <kamleshbhalui at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Analysis/InstructionSimplify.cpp
A llvm/test/Transforms/InstSimplify/vector-interleave-deinterleave.ll
Log Message:
-----------
[InstSimplify] fold the identity interleave (#206646)
If all the extracvalue of deinterleave used in interleave in same order
then it is an identity.
Commit: 5e265484030eb034a14f4e4fec5abb0209605787
https://github.com/llvm/llvm-project/commit/5e265484030eb034a14f4e4fec5abb0209605787
Author: Aliaksei Urbanski <aliaksei.urbanski at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M clang-tools-extra/docs/clang-tidy/checks/modernize/avoid-bind.rst
M clang/include/clang/Lex/MultipleIncludeOpt.h
M clang/lib/AST/DeclCXX.cpp
M clang/lib/CodeGen/README.txt
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Headers/avx2intrin.h
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/StaticAnalyzer/Checkers/GenericTaintChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/NullabilityChecker.cpp
M compiler-rt/lib/hwasan/hwasan_tag_mismatch_aarch64.S
M compiler-rt/lib/hwasan/hwasan_tag_mismatch_riscv64.S
M flang/docs/Semantics.md
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Optimizer/Transforms/LoopInvariantCodeMotion.cpp
M libc/src/string/memory_utils/arm/inline_memcpy.h
M libcxx/docs/DesignDocs/FeatureTestMacros.rst
M llvm/docs/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack.md
M llvm/docs/LangRef.rst
M llvm/docs/RISCVUsage.rst
M llvm/lib/Analysis/BlockFrequencyInfoImpl.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrNEON.td
M llvm/lib/Transforms/Instrumentation/NumericalStabilitySanitizer.cpp
M llvm/test/CodeGen/AArch64/regcoal-physreg.mir
M llvm/test/CodeGen/PowerPC/pgo-ref-directive.ll
M mlir/include/mlir/Dialect/Async/IR/AsyncOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.h
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPUOps.td
M polly/lib/External/isl/isl_union_map.c
Log Message:
-----------
[NFC] Fix "is is" typos (#206288)
These changes aim to fix common "is is" typos.
Commit: 03c62ca40d19ba03c7d2b69dbedc95e498d46071
https://github.com/llvm/llvm-project/commit/03c62ca40d19ba03c7d2b69dbedc95e498d46071
Author: Alex Strelnikov <strel at google.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M libc/docs/dev/printf_behavior.rst
M libc/src/__support/float_to_string.h
M libc/src/stdio/printf_core/converter_utils.h
M libc/src/stdio/printf_core/core_structs.h
M libc/src/stdio/printf_core/float_dec_converter.h
M libc/src/stdio/printf_core/float_dec_converter_limited.h
M libc/src/stdio/printf_core/float_hex_converter.h
M libc/src/stdio/printf_core/float_inf_nan_converter.h
M libc/src/stdio/printf_core/parser.h
M libc/src/stdio/printf_core/printf_config.h
M libc/src/stdio/printf_core/write_int_converter.h
M libc/test/UnitTest/CMakeLists.txt
M libc/test/UnitTest/PrintfMatcher.cpp
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/sprintf_test.cpp
Log Message:
-----------
[libc] Add Q length modifier to support float128 conversions in printf (#203077)
The spelling follows an existing pattern in e.g. libquadmath for format
printing `__float128` values.
A flag is added to disable float128 conversions and the "Q" length
modifier.
Commit: a4107d67f91946a97d0acd0a70e2ae16513858b9
https://github.com/llvm/llvm-project/commit/a4107d67f91946a97d0acd0a70e2ae16513858b9
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M .github/workflows/libcxx-run-benchmarks.yml
Log Message:
-----------
[libc++] Don't install custom Python on self-hosted macOS runners (#207794)
That shouldn't be necessary, since they already come with Python 3, and
it doesn't work anyway because it requires special setup that the macOS
runners don't currently perform.
Commit: 7b9a58e6cfa0dab49ef417f731ee7a8dc5e3aab5
https://github.com/llvm/llvm-project/commit/7b9a58e6cfa0dab49ef417f731ee7a8dc5e3aab5
Author: Michael Jones <michaelrj at google.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/hdr/CMakeLists.txt
A libc/hdr/dirent_overlay.h
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/DIR.h
A libc/hdr/types/struct_dirent.h
M libc/src/__support/File/dir.cpp
M libc/src/__support/File/dir.h
M libc/src/__support/File/linux/CMakeLists.txt
M libc/src/__support/File/linux/dir.cpp
M libc/src/__support/OSUtil/linux/stat/kernel_statx_types.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
A libc/src/__support/OSUtil/linux/syscall_wrappers/fcntl.h
M libc/src/dirent/CMakeLists.txt
A libc/src/dirent/fdopendir.cpp
A libc/src/dirent/fdopendir.h
M libc/test/src/dirent/CMakeLists.txt
A libc/test/src/dirent/fdopendir_test.cpp
Log Message:
-----------
[libc] Implement fdopendir (#206590)
The fdopendir function takes a file descriptor opened on a directory,
then opens a DIR* on it.
Needed for #191075
Assisted-by: Automated tooling, human reviewed.
Commit: 2590272e5674c300c9438ef5c10a65358b0636e9
https://github.com/llvm/llvm-project/commit/2590272e5674c300c9438ef5c10a65358b0636e9
Author: Alex Langford <alangford at apple.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M lldb/include/lldb/Core/EmulateInstruction.h
M lldb/include/lldb/Core/Value.h
M lldb/include/lldb/Expression/Materializer.h
M lldb/include/lldb/Host/common/NativeRegisterContext.h
M lldb/include/lldb/Symbol/UnwindPlan.h
M lldb/include/lldb/Target/DynamicRegisterInfo.h
M lldb/include/lldb/Target/RegisterContext.h
A lldb/include/lldb/Utility/RegisterInfo.h
M lldb/include/lldb/Utility/RegisterValue.h
M lldb/include/lldb/lldb-private-types.h
M lldb/source/Plugins/Process/Utility/RegisterFlagsDetector_arm64.h
M lldb/source/Plugins/Process/Utility/RegisterInfoInterface.h
Log Message:
-----------
[lldb] Move RegisterInfo and RegisterSet into their own header (#207286)
RegisterInfo holds onto a pointer to RegisterFlags which is in
lldbUtility. My understanding of lldb-private-types is that it contains
types used throughout LLDB but should generally stand on their own (i.e.
without dependencies on specific lldb types and headers). Thus I am
moving it to lldbUtility.
RegisterSet _does_ stand on its own but it is pretty strongly coupled to
RegisterInfo.
Commit: b74512899707cfcf962ebfa21f9209378372e78b
https://github.com/llvm/llvm-project/commit/b74512899707cfcf962ebfa21f9209378372e78b
Author: Andrei Elovikov <andrei.elovikov at sifive.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
Log Message:
-----------
[NFC][PatternMatch] Simplify m_Intrinsic impl using variadic templates (#207211)
Updates both IR/VPlan pattern matchers.
Commit: 76d253e2736c7da493a836c9c150772056dafd73
https://github.com/llvm/llvm-project/commit/76d253e2736c7da493a836c9c150772056dafd73
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
Log Message:
-----------
[docs][AMDGPU] Document amdgpu.buffer.oob.mode more, especially on fat pointers (#134734)
This commit expands the documentation of the amdgpu.buffer.oob.mode so
that fat buffer pointer users are more aware of its effects.
Commit: c8c20662e036099b00469bf26324b93151acb00c
https://github.com/llvm/llvm-project/commit/c8c20662e036099b00469bf26324b93151acb00c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/include/llvm/Support/KnownFPClass.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Support/KnownFPClass.cpp
M llvm/test/Transforms/Attributor/nofpclass-ldexp.ll
M llvm/test/Transforms/InstCombine/frexp-implied-exponent-range-dominating-conditions.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-ldexp.ll
Log Message:
-----------
ValueTracking: Improve frexp known range from dominating conditions (#206927)
Try to restrict the known range of the exponent result of llvm.frexp
based on dominating conditions. Identify comparisons that imply the
incoming value cannot introduce an overflow in a downstream ldexp
use. This pattern appears in the implementation of some complex math
functions and allows finite only math to prune out more edge case
paths.
One attributor test for ldexp regresses due to the switch from
computeKnownBits to computeConstantRange. computeConstantRange
does not try to handle non-splat vector constants for the binary
operators.
As a side effect, this also improves knowing that ldexp can't
introduce overflow for the 0 case.
Commit: dbd7511ad28819587fc9effc0086abf437279a84
https://github.com/llvm/llvm-project/commit/dbd7511ad28819587fc9effc0086abf437279a84
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-calls.ll
A llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization-alignment.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-mem-transfer.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-unoptimized-debug-data.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
Log Message:
-----------
[LowerBufferFatPointers] Correctly handle alignment modes (#134329)
Previously, AMDGPULowerBufferFatPointers would emit unaligned buffer
loads/stores, even when such unaligned accesses were disabled (that is,
on non-HSA platforms).
In addition, the lowering did not respect the newly-added
amdgpu.buffer.oob.mode module flag, which now must be enabled in order
to vectorize unaligned loads from buffers.
This commit fixes both issues and adds tests.
Commit: 000f6bf9cb7ec4223ef1de829158d09d4bfa2946
https://github.com/llvm/llvm-project/commit/000f6bf9cb7ec4223ef1de829158d09d4bfa2946
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFFunctionRewrite.cpp
M flang/test/Fir/CUDA/cuda-function-rewrite.mlir
Log Message:
-----------
[flang][cuda] Recognize on_device() by its Fortran leaf name in CUFFunctionRewrite (#207298)
CUFFunctionRewrite folds on_device() to a compile-time constant: true
inside a gpu.module (device), false on the host. Match on the callee's
Fortran leaf name, recovered independently of the external name-mangling
convention and of where the pass runs in the pipeline.
Commit: 3ae61eb220dc8f1fa0dd551a9575237b84dae61d
https://github.com/llvm/llvm-project/commit/3ae61eb220dc8f1fa0dd551a9575237b84dae61d
Author: Ken Matsui <26405363+ken-matsui at users.noreply.github.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/test/Transforms/InstCombine/add.ll
M llvm/test/Transforms/InstCombine/masked-merge-add.ll
M llvm/test/Transforms/InstCombine/pr53357.ll
M llvm/unittests/Analysis/ValueTrackingTest.cpp
Log Message:
-----------
[InstCombine] Turn Add into Or even when undef (#171556)
Since 03d4a9d94da30590ebfc444cf13a8763f47b7bb9, Add is turned into
DisjointOr, and since 5c3496ff33ce8e4cc6f8c18edd7ae5fc65d23fdf, Add
isn't turned into DisjointOr when undef. However, Add can still be
turned into Or even when undef.
This patch restores the transformation behavior we had in LLVM 17, while
continuing to generate DisjointOr when possible.
Alive2: https://alive2.llvm.org/ce/z/ZT0ZFj
Commit: 5e5490f2df9c9c329689929b62d51ee0fb95fb30
https://github.com/llvm/llvm-project/commit/5e5490f2df9c9c329689929b62d51ee0fb95fb30
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/haddsub-undef.ll
M llvm/test/CodeGen/X86/phaddsub-undef.ll
Log Message:
-----------
[X86] combineToHorizontalAddSub - use PostShuffleMask to determine undemanded subvectors (#207789)
For cases where the middle-end has created a 256-bit HADD/SUB pattern
with unused upper 128-bit subvectors, use the PostShuffleMask undefined
ranges to remove any unused 128-bit HADD/SUB ops.
Commit: 3df6ca69c9e2b22687315a3074857383eefa93b8
https://github.com/llvm/llvm-project/commit/3df6ca69c9e2b22687315a3074857383eefa93b8
Author: Quentin Colombet <quentin.colombet at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
R llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll
A llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.mir
Log Message:
-----------
[AMDGPU][test] Use mir test for regalloc issue (#197363)
Use the newly introduced split-from flag to produce a more robust test
case for the hoistSpillInsideBB live-range update issue.
NFC
Commit: 2e0c6a254c4a159726f0477bbe3723eafe33382c
https://github.com/llvm/llvm-project/commit/2e0c6a254c4a159726f0477bbe3723eafe33382c
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M lldb/test/API/functionalities/scripted_frame_provider/circular_dependency/TestFrameProviderCircularDependency.py
Log Message:
-----------
[lldb] Fix TestFrameProviderCircularDependency.py on Arm (#207804)
After #206987 this test started passing on Windows and 32-bit Linux on
Arm. Remove the expected failure annotation to fix lldb-arm-ubuntu
buildbot.
Commit: 396354a3f7f627aaa5cbfffa2033e1ea8bc00e69
https://github.com/llvm/llvm-project/commit/396354a3f7f627aaa5cbfffa2033e1ea8bc00e69
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M .github/workflows/libcxx-run-benchmarks.yml
Log Message:
-----------
[libc++] Install missing dependencies for running benchmarks on macOS (#207810)
The macOS self-hosted runners don't come with Ninja and CMake installed
out of the box, so we need to install them with Homebrew.
Commit: d2b6f83980ed0428d8342b378f01317acf4510de
https://github.com/llvm/llvm-project/commit/d2b6f83980ed0428d8342b378f01317acf4510de
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M clang/include/clang/Basic/TargetInfo.h
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/ARM.h
M clang/lib/Basic/Targets/DirectX.h
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Basic/Targets/NVPTX.h
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Basic/Targets/SystemZ.h
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/Basic/Targets/X86.h
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CodeGen/CGExprConstant.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CodeGenTypes.cpp
M clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaExpr.cpp
A clang/test/CIR/CodeGen/fp16-native-args.c
A clang/test/CIR/CodeGen/fp16.c
M clang/test/CodeGen/builtin_float.c
M clang/test/CodeGen/builtin_float_strictfp.c
M clang/test/CodeGen/wasm-fp16.c
Log Message:
-----------
clang: Remove useFP16ConversionIntrinsics target option (#207212)
Follow up to #174494. Remove the remnants of the control to
use llvm.convert.to.fp16/llvm.convert.from.fp16. Prefer
directly using the IR half type.
I did the first 80% of this a long time ago, and AI finished
the last bit and handled the recent rebases and test updates.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: 4868f2c1edfede611994a621e8eb0adac46bca1a
https://github.com/llvm/llvm-project/commit/4868f2c1edfede611994a621e8eb0adac46bca1a
Author: Alex Langford <alangford at apple.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbtest.py
Log Message:
-----------
[lldb] Modify test binaries that link against LLDB to use LLVM dylib (#207290)
When LLVM_LINK_LLVM_DYLIB is enabled and we build LLDB.framework, tests
that link against LLDB.framework will fail to load the LLVM dylib
because of a missing rpath.
Commit: 2d0f294d1b272b8976ebd2d90a5252af1af8ca89
https://github.com/llvm/llvm-project/commit/2d0f294d1b272b8976ebd2d90a5252af1af8ca89
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.offset-split.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load-exported.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
Log Message:
-----------
[AMDGPU] Precommit for pulling NUW large buffer offsets into SOFFSET (#207795)
This commit adds tests with larger constant offsets [being added to
VGPRs] in raw.buffer.* instructions to show the movement of such offsets
to SOFFSET after rounding in a future commit if this won't cause errors
because of overflow.
This also necessitated adding gfx1250 tests (to show the different
offset sizes) and moving tests that ctalled "export" into a new file so
that the gfx1250 (which doesn't support that instruction) doesn't trip
ot those tests.
This also adds a few global-isel specific tests for handling `or
disjoint` like an add we can't just stick -global-isel in the normal
buffer intrinsic tests.
AI usage disclosure: AI wrote these, I skimmed them.
---------
Co-authored-by: Codex <codex at openai.com>
Commit: 5dfc35a50514aaa62a34cb17f5be5c6396caf4fb
https://github.com/llvm/llvm-project/commit/5dfc35a50514aaa62a34cb17f5be5c6396caf4fb
Author: Scott Linder <scott.linder at amd.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/docs/VectorizationPlan.rst
M llvm/docs/conf.py
M utils/docs/llvm_sphinx/__init__.py
Log Message:
-----------
[docs] Disable sphinx's numfig option (#207817)
Benchmarking shows a speedup of about 1.6x for a single file edit:
```bash
source .venv/bin/activate
hyperfine \
--ignore-failure \
--warmup 1 \
--setup 'rm -rf /dev/shm/sphinx-build && cm c -b /dev/shm/sphinx-build' \
--prepare 'touch llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst' \
'cm b -b /dev/shm/sphinx-build docs-llvm-html'
# main:
# Benchmark 1: cm b -b /dev/shm/sphinx-build docs-llvm-html
# Time (mean ± σ): 41.424 s ± 1.652 s [User: 39.534 s, System: 1.876 s]
# Range (min … max): 40.696 s … 46.110 s 10 runs
# no-numfig:
# Benchmark 1: cm b -b /dev/shm/sphinx-build docs-llvm-html
# Time (mean ± σ): 25.808 s ± 2.051 s [User: 24.106 s, System: 1.692 s]
# Range (min … max): 24.287 s … 30.132 s 10 runs
```
There are only two uses of the feature, both in VectorizationPlan, and
the net result of disabling it just changes them from looking like this:
Refer to [Fig. 1] for an overview of the current transformation
pipeline.
To looking like this:
Refer to [VPlan Transformation Pipeline in 2024] for an overview of the
current transformation pipeline.
Where "[...]" denotes the hyperlink to the figure.
See
https://github.com/zephyrproject-rtos/zephyr/pull/37572#discussion_r1102411281
for another project's discussion of the same issue.
Commit: 2ef9c9d02409b02dc2289b4125397cbc40030c74
https://github.com/llvm/llvm-project/commit/2ef9c9d02409b02dc2289b4125397cbc40030c74
Author: Jackson Stogel <jtstogel at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/stdio/BUILD.bazel
Log Message:
-----------
[bazel][libc] Port 03c62ca40d (#207820)
Commit: 642c9f69772dea930c8c035813430d325c96697c
https://github.com/llvm/llvm-project/commit/642c9f69772dea930c8c035813430d325c96697c
Author: Scott Linder <scott.linder at amd.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M utils/docs/llvm_sphinx/__init__.py
Log Message:
-----------
[docs][NFC] Some small cleanup in llvm_sphinx (#207818)
Format the doc-comment suggested import to match what `black` prefers,
and isolate the `import` as the only statement in the `try` for
`myst_parser`.
Commit: ddebfb9d1cbdf2988d118eae889b868024290856
https://github.com/llvm/llvm-project/commit/ddebfb9d1cbdf2988d118eae889b868024290856
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
Log Message:
-----------
[VPlan] Add intrinsic constant folding test for replicate recipes. (NFC) (#207792)
Commit: f348d964af441ec454e5fc12ab1b599cfc1e7d14
https://github.com/llvm/llvm-project/commit/f348d964af441ec454e5fc12ab1b599cfc1e7d14
Author: Aditya Medhane <sherlockedaditya at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/test/Misc/warning-wall.c
M clang/test/SemaCXX/warn-func-not-needed.cpp
M clang/test/SemaCXX/warn-variable-not-needed.cpp
Log Message:
-----------
[Clang] Enable -Wunused-template under -Wall (#206123)
Uncomment `UnusedTemplate` in the `Unused` diagnostic group so
`-Wunused-template` becomes part of `-Wall`.
`-Wunused-template` flags unused function and variable templates with
internal linkage. In a header, such a template gives every translation
unit its own internal-linkage copy, which is a latent ODR violation
(ill-formed, no diagnostic required), so enabling this surfaces a real
class of bugs and keeps the pattern from reappearing.
### Depends on
The in-tree occurrences were cleaned up first in a series of NFC PRs
tracked by #202945. This change only builds clean once those land, so CI
will be red on any area whose cleanup is not yet merged. Remaining
prerequisites:
Approved
- #202969
- #202971
- #202973
- #202974
- #206309
- #206312
Needs to be reviewed
- #202988
- #206308
Closes #202945
cc @AaronBallman @vgvassilev
Commit: 2e1f347c38114f5e2e4fc4355fad9cdc0e1bb205
https://github.com/llvm/llvm-project/commit/2e1f347c38114f5e2e4fc4355fad9cdc0e1bb205
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M libcxx/include/__ranges/zip_transform_view.h
A libcxx/test/libcxx/ranges/range.adaptors/range.zip.transform/nodiscard.verify.cpp
M libcxx/test/std/ranges/range.adaptors/range_adaptor_types.h
M libcxx/test/support/test_iterators.h
Log Message:
-----------
[libc++][ranges] Applied `[[nodiscard]]` to `views::zip_transform` (#207120)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html
- https://wg21.link/range.zip.transform
Towards #172124
---------
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Commit: 5a74b398d27ecba94fa0acf800af86039bf6a0f5
https://github.com/llvm/llvm-project/commit/5a74b398d27ecba94fa0acf800af86039bf6a0f5
Author: Alex Langford <alangford at apple.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M lldb/include/lldb/Core/Section.h
M lldb/source/API/SBModule.cpp
M lldb/source/API/SBSection.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Core/Section.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOSXDYLD.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntime.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Platform/Android/PlatformAndroid.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp
M lldb/unittests/Core/ModuleTest.cpp
M lldb/unittests/ObjectFile/ELF/TestObjectFileELF.cpp
M lldb/unittests/Symbol/LineTableTest.cpp
Log Message:
-----------
[lldb] Remove ConstString from SectionList::FindSectionByName (#207296)
By having ConstString in this interface, we are forcing callers to
create a ConstString in order to perform a lookup. In many cases,
`FindSectionByName` is a best-effort interface, meaning we're creating
ConstStrings speculatively. In other cases, we were creating a
ConstString at the call-site instead of computing it once and re-using
it.
I audited all the callsites and changed all the callsites that created a
ConstString for the purpose of calling `FindSectionByName`. Other
callsites will take more time to change.
Commit: 09f2062da3b34b7db167268b05c9a9a5bd3c7e17
https://github.com/llvm/llvm-project/commit/09f2062da3b34b7db167268b05c9a9a5bd3c7e17
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CodeGenTypes.cpp
Log Message:
-----------
clang: Use getFloatingPointType instead of reinventing it (#207213)
Commit: e64a71f09b016edb834eb45e5c172d1337555803
https://github.com/llvm/llvm-project/commit/e64a71f09b016edb834eb45e5c172d1337555803
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/test/Transforms/LoopVectorize/early_exit_with_outer_loop.ll
Log Message:
-----------
[VPlan] Refine hasEarlyExit check. (#207791)
Currently hasEarlyExit misses cases where we have things like dead exit
blocks or simplified the middle block.
Update to check by counting the predecessors.
This fixes a case where we missed properly updating LoopInfo due to
incorrect results.
Fixes https://github.com/llvm/llvm-project/issues/206007.
Commit: b69ec1023d6604106cb64f9a6a6b04e9c3e5d533
https://github.com/llvm/llvm-project/commit/b69ec1023d6604106cb64f9a6a6b04e9c3e5d533
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/test/Transforms/LoopVectorize/early_exit_with_outer_loop.ll
Log Message:
-----------
Revert "[VPlan] Refine hasEarlyExit check." (#207838)
Reverts llvm/llvm-project#207791
This appears to break multiple build-bots
Commit: f147395634dd21f9f2dfbdcc8c1a2f96c3228a24
https://github.com/llvm/llvm-project/commit/f147395634dd21f9f2dfbdcc8c1a2f96c3228a24
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ObjectYAML/BUILD.gn
Log Message:
-----------
[gn build] Port commits (#207839)
1b2efd2e079a
9b2d44a51252
Commit: 23a01e949a55d4034dbbcad08c875a1d458464b1
https://github.com/llvm/llvm-project/commit/23a01e949a55d4034dbbcad08c875a1d458464b1
Author: Eli Friedman <efriedma at qti.qualcomm.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/test/CodeGen/AArch64/stack-guard-width.ll
Log Message:
-----------
[AArch64] Support 4-byte stack protector with large code model. (#205956)
This is a simple extension to existing code. We might need this in the
future.
Commit: 61d766817b9ebe9804c84d71aa7a620962436dff
https://github.com/llvm/llvm-project/commit/61d766817b9ebe9804c84d71aa7a620962436dff
Author: Bill Wendling <morbo at google.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
A clang/test/CodeGen/attr-counted-by-nested-structs.c
Log Message:
-----------
[Clang][counted_by] Use the expr's RecordDecl that transitively contains the counter field (#205903)
The counted field could be in nested structs. This can happen when the
Expr is pointing to a field that has a struct type. The original code
didn't do a good job at finding the best RecordDecl to build the GEP off
of. It made too many assumptions about how structs' layouts.
This rewrite finds the RecordDecl that transitively contains the
__counted_by__'s counter field.
Fixes: #205652
Commit: c9c7fdde03d04ab10960db156f832a276411e3b5
https://github.com/llvm/llvm-project/commit/c9c7fdde03d04ab10960db156f832a276411e3b5
Author: yebinchon <86588366+yebinchon at users.noreply.github.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/SeparateAllocatableAssign.cpp
M flang/test/HLFIR/separate-allocatable-assign.fir
Log Message:
-----------
[flang] keep runtime allocator for pinned allocations (#207822)
If an allocatable is pinned, use the flang runtime instead of lowering
to normal memcpy/free.
---------
Co-authored-by: Yebin Chon <ychon at nvidia.com>
Commit: 8014a1d208f0f9e58cfeaf022517cf3d69257bff
https://github.com/llvm/llvm-project/commit/8014a1d208f0f9e58cfeaf022517cf3d69257bff
Author: Yao Qi <yao_qi at apple.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/include/llvm/Support/LEB128.h
M llvm/unittests/Support/LEB128Test.cpp
Log Message:
-----------
[Support] Fix undefined shift in decodeULEB128/decodeSLEB128 for overlong encodings (#205907)
When a (signed or unsigned) LEB128 value is encoded with extra trailing
bytes that only carry zero- or sign-extension, the decode loop could
keep
running with the shift amount at 64 or beyond and then evaluate
`Slice << Shift`, which is undefined behavior for a 64-bit type.
The DWARF expression parser feeds attacker-controlled LEB128 operands
(such as `DW_OP_bregN` / `DW_OP_constu`) through
`DataExtractor::getULEB128` / `getSLEB128`, so the
`lldb-dwarf-expression-fuzzer` reaches this under UBSan. The unsigned
case:
```
LEB128.h:152:20: runtime error: shift exponent 70 is too large for
64-bit type 'uint64_t' (aka 'unsigned long long')
#0 llvm::decodeULEB128(...) LEB128.h:152
#1 getLEB128<unsigned long long>(...) DataExtractor.cpp:227
#2 llvm::DataExtractor::getULEB128(...) DataExtractor.cpp:241
#3 llvm::DWARFExpression::Operation::extract(...) DWARFExpression.cpp:218
#7 lldb_private::DWARFExpression::Evaluate(...) DWARFExpression.cpp:1333
#9 LLVMFuzzerTestOneInput lldb-dwarf-expression-fuzzer.cpp:83
SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior LEB128.h:152:20
```
and the signed case, reached the same way:
```
LEB128.h:190:20: runtime error: shift exponent 70 is too large for
64-bit type 'uint64_t' (aka 'unsigned long long')
#0 llvm::decodeSLEB128(...) LEB128.h:190
#1 getLEB128<long long>(...) DataExtractor.cpp:227
#2 llvm::DataExtractor::getSLEB128(...) DataExtractor.cpp:245
#3 llvm::DWARFExpression::Operation::extract(...) DWARFExpression.cpp:216
#7 lldb_private::DWARFExpression::Evaluate(...) DWARFExpression.cpp:1333
```
The existing range checks already guarantee that once `Shift` reaches 64
the remaining bytes are pure extension and contribute nothing to the
result, so skip the accumulating shift in that case. Decoded values are
unchanged for all well-formed inputs.
Adds overlong-encoding regression cases to `LEB128Test`. Without the fix
the signed case is the UBSan diagnostic above in a sanitizer build, and
in a normal build the unsigned case also decodes to the wrong value (the
overlong `1` decodes as `11`).
Commit: 3df648c5678f6add2a813cd5be3dffb4f074115e
https://github.com/llvm/llvm-project/commit/3df648c5678f6add2a813cd5be3dffb4f074115e
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
A llvm/test/Transforms/InstCombine/select-abs-positive-mul.ll
Log Message:
-----------
[InstCombine] Add tests for select-abs through multiply (NFC) (#207833)
Add tests from approved https://github.com/llvm/llvm-project/pull/207539
Commit: 1b6f1528bbb95d47bb2e3fc394b3a4943b1e9708
https://github.com/llvm/llvm-project/commit/1b6f1528bbb95d47bb2e3fc394b3a4943b1e9708
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/include/llvm/DebugInfo/DWARF/DWARFDie.h
M llvm/lib/DebugInfo/DWARF/DWARFDie.cpp
A llvm/test/tools/llvm-dwarfdump/X86/array-type-lower-bound-dwarf6.s
M llvm/unittests/DebugInfo/DWARF/DWARFDieTest.cpp
Log Message:
-----------
[llvm][DebugInfo] Add DW_LNAME_ support to DWARFDie::getLanguage (#207151)
Currently `DWARFDie::getLanguage` only looks at `DW_AT_language`.
However, with DWARFv6 we may not have such attribute, and instead have a
`DW_AT_language_name` (and optional `DW_AT_language_version`).
This patch adjusts the implementation to also consider the DWARFv6
language name/version codes. In this patch I just convert it back to
`DW_LANG_` (similar to what we do for the `AsmPrinter`'s
`DwarfUnit::getSourceLanguage`). Added a FIXME to investigate whether we
want to return a variant-like type that can be either an DW_LANG vs.
DW_LNAME code.
The way I initially observed this was looking at a DWARFv6 dwarfdump for
a `const char[]` type. It displayed as follows:
```
DW_AT_type (0x... "const char[[?, ? + 3)]")
```
which is our representation for when we [can't derive the default lower
bound for the
language](https://github.com/llvm/llvm-project/blob/ce787718c3c82255825ebe5f95740c24df55f7d0/llvm/include/llvm/DebugInfo/DWARF/DWARFTypePrinter.h#L122-L135).
With this patch, we'd display it as expected:
```
DW_AT_type (0x... "const char[3]")
```
Added unit-tests for the new API and a dwarfdump test.
AI usage:
- Claude wrote the dwarfdump and unit-tests. Manually reviewed and
cleaned them up.
Commit: 94b325469b20255d31879c80204800510ac4fd66
https://github.com/llvm/llvm-project/commit/94b325469b20255d31879c80204800510ac4fd66
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaChecking.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/Analysis/bstring.c
M clang/test/Analysis/malloc.c
M clang/test/Analysis/pr22954.c
M clang/test/Sema/builtin-memcpy.c
M clang/test/Sema/builtin-object-size.c
M clang/test/Sema/warn-fortify-source.c
R clang/test/Sema/warn-stringop-overread.c
M clang/test/SemaCXX/warn-memset-bad-sizeof.cpp
M compiler-rt/test/asan/TestCases/Windows/issue64990.cpp
Log Message:
-----------
Revert "[Clang][Sema] Add -Wstringop-overread warning for source buffer overreads (#183004)" (#207840)
This reverts commit 86f2e71cb8d165b59ad31a442b2391e23826133e.
And revert followup ab1ef459069d1dbf4ee9e5a802537ababe294b25 (#205201).
Causes crashes:
https://github.com/llvm/llvm-project/pull/183004#issuecomment-4897195939
Commit: ff11bbce9e87ab4ef59a789cff1c9b9d771adc1e
https://github.com/llvm/llvm-project/commit/ff11bbce9e87ab4ef59a789cff1c9b9d771adc1e
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M clang-tools-extra/clang-tidy/misc/DefinitionsInHeadersCheck.cpp
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/refactor/tweaks/DefineInline.cpp
M clang/docs/LibASTMatchersReference.html
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/JSONNodeDumper.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/ASTMatchers/ASTMatchersInternal.h
M clang/include/clang/Basic/Specifiers.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTDumper.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/Comment.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/ASTMatchers/Dynamic/Registry.cpp
M clang/lib/Analysis/ExprMutationAnalyzer.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
M clang/lib/CodeGen/CGVTables.cpp
M clang/lib/Index/IndexingContext.cpp
M clang/lib/InstallAPI/Visitor.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/StaticAnalyzer/Core/BugSuppression.cpp
M clang/lib/Tooling/Syntax/BuildTree.cpp
M clang/test/AST/ast-dump-templates-pattern.cpp
M clang/test/CXX/basic/basic.link/p11.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg7xx.cpp
M clang/test/CXX/temp/temp.arg/temp.arg.template/p3-2a.cpp
M clang/test/CXX/temp/temp.constr/temp.constr.decl/p4.cpp
M clang/test/CXX/temp/temp.decls/temp.spec.partial/temp.spec.partial.member/p2.cpp
M clang/test/CXX/temp/temp.spec/temp.expl.spec/p7.cpp
M clang/test/CodeGenCXX/default-arguments.cpp
M clang/test/CodeGenCXX/explicit-instantiation.cpp
M clang/test/SemaCXX/GH195416.cpp
M clang/test/SemaCXX/constant-expression-cxx14.cpp
M clang/test/SemaCXX/deduced-return-type-cxx14.cpp
M clang/test/SemaCXX/member-class-11.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/test/SemaTemplate/friend-template.cpp
M clang/test/SemaTemplate/instantiate-scope.cpp
M clang/test/Templight/templight-default-func-arg.cpp
M clang/test/Templight/templight-empty-entries-fix.cpp
M clang/tools/libclang/CIndex.cpp
M clang/unittests/AST/ASTImporterTest.cpp
M clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
Log Message:
-----------
[clang] Reland: fix getTemplateInstantiationArgs (#207825)
Relands https://github.com/llvm/llvm-project/pull/199528
Previous: https://github.com/llvm/llvm-project/pull/202088
This implements a new strategy for collecting the template arguments, by
relying on the qualifiers and template parameter lists to navigate the
template
context of out-of-line definitions.
This greatly simplifies the signature of that function, by removing a
bunch
of workarounds, and simpliffying a couple that weren't removed yet.
Since this now relies on qualifiers and template parameter lists,
this patch expends most of its effort making sure these are placed,
transformed and propagated to template instantiations.
Also makes the explicit specialization AST nodes stop abusing the
template
parameter lists by storing it's own template parameter list, creating a
dedicated field for them, similar to partial specializations.
Fixes #202106
Fixes #202109
Commit: c63adb28aa78ecb300bf06c1d0893ae6259765dd
https://github.com/llvm/llvm-project/commit/c63adb28aa78ecb300bf06c1d0893ae6259765dd
Author: mzukovec <martin.zukovec at xlab.si>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/AST/MicrosoftMangle.cpp
M clang/test/CodeGenCXX/mangle-ms-md5.cpp
Log Message:
-----------
[clang] Cap MS RTTI TypeDescriptor name strings like MSVC does (#206317)
On the Microsoft ABI, an RTTI TypeDescriptor stores the type's decorated
name as an inline string. Unlike symbol names, this string was never run
through the MD5 shortening that MSVC applies to over-long decorated
names. Deeply nested template types therefore produced unbounded
writable .data COMDATs: for example a type whose template arguments
contain a local lambda, whose mangled name re-spells the enclosing
template context at every level of nesting, grows exponentially with
depth. A five-level repro emitted an 82 MB object file.
Wrap the TypeDescriptor name string in the same msvc_hashing_ostream
already used for the RTTI symbol. When the name reaches the length limit
it is replaced by ??@<md5>@, mimicking MSVC. MSVC counts the leading .
of the name string toward the 4096-character limit but excludes it from
the hashed input, so the threshold here is one lower than for symbols.
Fixes #206313
Commit: e27218ee24231abd4f4d3231fc682745a71a0657
https://github.com/llvm/llvm-project/commit/e27218ee24231abd4f4d3231fc682745a71a0657
Author: David Blaikie <dblaikie at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/lib/DebugInfo/DWARF/DWARFDebugAbbrev.cpp
M llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
M llvm/lib/DebugInfo/DWARF/DWARFUnit.cpp
M llvm/lib/DebugInfo/GSYM/DwarfTransformer.cpp
Log Message:
-----------
Reapply "DebugInfo: Shrink-to-fit some containers to reduce peak memory usage" (#199145) (#201160)
Starting with posting this as a draft PR to run presubmit checks to
understand what failed.
This reverts commit #199145,
effectively reapplying #198935.
Commit: 1fd46543f6b8aa0017d814301e0b019aa7144468
https://github.com/llvm/llvm-project/commit/1fd46543f6b8aa0017d814301e0b019aa7144468
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
M lldb/test/API/tools/lldb-dap/exception/TestDAP_exception.py
M lldb/test/API/tools/lldb-dap/exception/asan/TestDAP_asan.py
M lldb/test/API/tools/lldb-dap/exception/cpp/TestDAP_exception_cpp.py
M lldb/test/API/tools/lldb-dap/exception/cpp/main.cpp
M lldb/test/API/tools/lldb-dap/exception/objc/TestDAP_exception_objc.py
M lldb/test/API/tools/lldb-dap/exception/ubsan/TestDAP_ubsan.py
Log Message:
-----------
[lldb-dap] Migrate DAP exceptions test. (#207029)
Migrate all the tests in the `lldb-dap/exception` folder.
Commit: 5275ff2efaa9b729aebdfbfc4219f0d109cf03e5
https://github.com/llvm/llvm-project/commit/5275ff2efaa9b729aebdfbfc4219f0d109cf03e5
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Frontend/InitPreprocessor.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/__clang_gpu_builtin_vars.h
A clang/lib/Headers/__clang_gpu_device_functions.h
A clang/lib/Headers/__clang_gpu_intrinsics.h
M clang/test/Driver/hip-device-libs-llvm-env.hip
A clang/test/Headers/gpu-device-functions.cpp
M clang/test/Preprocessor/predefined-macros.c
Log Message:
-----------
[Clang][HIP] Add LLVM vendored device headers for `*-llvm` triple (#203980)
Summary:
We already have the `*-llvm` vendor triple to imply a hermetic LLVM
toolchain for HIP. This adds the device portion of the headers that can
be used without a ROCm installation. These are vendored just like the
CUDA ones. Despite being HIP, these are actually generic because it onyl
uses clang builtins and the `gpuintrin` shims.
Commit: 6f47c92a82cc142fe5b728a4d90987e15876b372
https://github.com/llvm/llvm-project/commit/6f47c92a82cc142fe5b728a4d90987e15876b372
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/test/Misc/warning-wall.c
M clang/test/SemaCXX/warn-func-not-needed.cpp
M clang/test/SemaCXX/warn-variable-not-needed.cpp
Log Message:
-----------
Revert "[Clang] Enable -Wunused-template under -Wall" (#207848)
Reverts llvm/llvm-project#206123
See the Flang Runtime unit test failures, we probably should fix those
before merging this to keep buildbots green.
Commit: 1e7e166e39f4515a4cea1dcd07d016b4e2315e31
https://github.com/llvm/llvm-project/commit/1e7e166e39f4515a4cea1dcd07d016b4e2315e31
Author: Kyungtak Woo <kevinwkt at google.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/Transforms/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
Log Message:
-----------
[bazel][libc] Port 03c62ca40d pt2 (#207846)
This was missed in https://github.com/llvm/llvm-project/pull/207820 adding dep. Along with flang deps.
Commit: 8475e376043ddacc53b7062c71438ea4e2a082e0
https://github.com/llvm/llvm-project/commit/8475e376043ddacc53b7062c71438ea4e2a082e0
Author: tedwoodward <56049650+tedwoodward at users.noreply.github.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M lldb/bindings/python/get-python-config.py
Log Message:
-----------
[lldb] Change Python site-packages path (#207771)
On POSIX systems, traditionally the lldb Python module is in
lib/pythonx.x/site-packages. We only ever have 1 Python in a given
build, so we don't need to specify the version.
On Windows, we've always had the Python module in lib\site-packages.
Change the behavior on POSIX to match the Windows behavior, and put the
lldb Python module in lib/site-packages.
---------
Co-authored-by: Ted Woodward <tedwood at quicinc.com>
Commit: 6e0311f077601350d5cc70e59c49432d985ca631
https://github.com/llvm/llvm-project/commit/6e0311f077601350d5cc70e59c49432d985ca631
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/include/llvm/Object/COFF.h
M llvm/lib/Object/ArchiveWriter.cpp
M llvm/lib/Object/COFFObjectFile.cpp
A llvm/test/tools/llvm-ar/arm64x-hybridobj.yaml
A llvm/test/tools/llvm-ar/arm64x-split.yaml
A llvm/test/tools/llvm-lib/arm64x-hybridobj.yaml
Log Message:
-----------
[Archive][COFF] Split hybrid COFF files when adding them to an archive (#205160)
Create a separate member for the embedded hybrid object so that it's
properly reflected in the archive's symbol map and can be correctly
processed by tools unaware of multi-arch object files. Prefix the
embedded member name with 'obj.arm64x/' to avoid name collisions.
The split is performed only when targeting COFF archive format.
Commit: 6da965ce85fc9c14ecad4d6d15cb6bb57776d979
https://github.com/llvm/llvm-project/commit/6da965ce85fc9c14ecad4d6d15cb6bb57776d979
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M mlir/examples/standalone/pyproject.toml
Log Message:
-----------
[mlir][python] Set a static version in the standalone example pyproject.toml (#207860)
The standalone example's pyproject.toml declares `dynamic = ["version"]` but does not configure a `tool.scikit-build metadata.version.provider`. Newer versions of scikit-build-core reject this combination with:
```
AssertionError: project.version is not specified, must be statically present or tool.scikit-build metadata.version.provider configured when dynamic
```
Just pin a static placeholder version instead of adding a "provider".
Assisted by: Claude
Commit: 3d517ee6486553b3ecbabdb46c0496abcf9ad20a
https://github.com/llvm/llvm-project/commit/3d517ee6486553b3ecbabdb46c0496abcf9ad20a
Author: Damyan Pepper <damyanp at microsoft.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/test/tools/dxil-dis/waveactiveballot.ll
Log Message:
-----------
[NFC] Fix dxil-dis/waveactiveballot.ll test (#207446)
It looks like #204478 introduced new intrinsic signature verification,
but since it didn't touch any of the HLSL/DXIL related paths the tests
were never run on a runner that has dxil-dis installed on it.
Assisted-by: copilot
Commit: f7f06613d4fc68620076a48341acf22dc05fbd82
https://github.com/llvm/llvm-project/commit/f7f06613d4fc68620076a48341acf22dc05fbd82
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M clang/lib/CodeGen/Targets/RISCV.cpp
A clang/test/CodeGen/RISCV/attr-rvv-vector-bits-struct-call.c
A clang/test/CodeGenCXX/riscv-rvv-fixed-length-struct-call.cpp
Log Message:
-----------
[RISCV] Pass structs containing riscv_rvv_vector_bits types using vector registers. (#203601)
The ABI for this isn't documented. The riscv_rvv_vector_bits feature was
copied from aarch_sve_vector_bits which passes the types in vector
registers. At the time I implemented RISC-V I didn't think about struct
arguments so no ABI support was added.
I think it makes sense to pass structs of these types in vector
registers similar to the vls_cc ABI. We already do use vector registers
for these types when the vls_cc ABI is enabled for a function(unclear if
that was intentional), but we should do it unconditionally.
I will work with gcc maintainers to see if they can do the same. In
practice, there probably isn't much compiler mixing with these types.
This patch was heavily assisted by AI, but I've reviewed it and the
changes seem reasonable to me.
Commit: 81200d780eb6f9d8c9cf319d04ca5d7039dff944
https://github.com/llvm/llvm-project/commit/81200d780eb6f9d8c9cf319d04ca5d7039dff944
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/NVPTX/NVVMProperties.cpp
Log Message:
-----------
[NFC][LLVM][NVPTX] Use namespace qualifiers to define functions (#207546)
Use namespace qualifiers to define functions in `llvm` namespace, per
https://llvm.org/docs/CodingStandards.html#use-namespace-qualifiers-to-define-previously-declared-symbols.
Commit: 06f4b027b2df1febf3cd496573b8739074e8aa29
https://github.com/llvm/llvm-project/commit/06f4b027b2df1febf3cd496573b8739074e8aa29
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVVMReflect.cpp
Log Message:
-----------
[NFC][LLVM][NVPTX] Minor code cleanup in NVVMReflect (#207549)
Use explicit types instead of auto when the type is not obvious. Use
`StringRef` type in the range for loop over `ReflectList`, allowing
additional code cleanups.
Commit: 8f3e6197f676831794bfa7a7b4619c59c7915c42
https://github.com/llvm/llvm-project/commit/8f3e6197f676831794bfa7a7b4619c59c7915c42
Author: Michael Jones <michaelrj at google.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M libc/config/linux/riscv/entrypoints.txt
Log Message:
-----------
[libc][RISC-V] Temporarily disable dirent (#207867)
The RISC-V 32 QEMU buildbot is failing due to missing SYS_fcntl, which
is needed for fdopendir. Since that syscall is referenced in the shared
dir code it's easiest to just disable all the dirent functions for now.
Commit: cc048e80b670a5262500612069d1c2d065b53f15
https://github.com/llvm/llvm-project/commit/cc048e80b670a5262500612069d1c2d065b53f15
Author: Neil Nair <neilnair4 at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M clang-tools-extra/clang-doc/CMakeLists.txt
A clang-tools-extra/clang-doc/markdown/CMakeLists.txt
A clang-tools-extra/clang-doc/markdown/Markdown.cpp
A clang-tools-extra/clang-doc/markdown/Markdown.h
M clang-tools-extra/clang-doc/support/CMakeLists.txt
R clang-tools-extra/clang-doc/support/Markdown.cpp
R clang-tools-extra/clang-doc/support/Markdown.h
M clang-tools-extra/unittests/clang-doc/MarkdownParserTest.cpp
Log Message:
-----------
[clang-doc] Move Markdown into its own subdirectory (#207856)
Removes the need for PARTIAL_SOURCES_INTENDED by giving clangDocMarkdown
its own directory. Addresses post-merge feedback on #205609.
Commit: a2dbd23cdc562f5307e81789e770a290e863a91f
https://github.com/llvm/llvm-project/commit/a2dbd23cdc562f5307e81789e770a290e863a91f
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/clang-tools-extra/clang-doc/BUILD.bazel
M utils/bazel/llvm-project-overlay/clang-tools-extra/unittests/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes cc048e8 (#207873)
This fixes cc048e80b670a5262500612069d1c2d065b53f15.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: a37bb291fd9ca6c19a809196d074eaddae041353
https://github.com/llvm/llvm-project/commit/a37bb291fd9ca6c19a809196d074eaddae041353
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
A llvm/test/CodeGen/NVPTX/lower-byval-args-mem-attrs.ll
Log Message:
-----------
[NVPTX] Assign correct memory attrs to args in NVPTXLowerArgs (#207461)
Commit: 52f1b754dddb740a553166acb9a5d40c38cc74e5
https://github.com/llvm/llvm-project/commit/52f1b754dddb740a553166acb9a5d40c38cc74e5
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/bindings/python/tests/cindex/test_source_range.py
M clang/bindings/python/tests/cindex/test_translation_unit.py
Log Message:
-----------
[clang] workaround libclang-python windows CI failures (#207875)
Commit: a42a1c84c1305d785ca58d271d5f2f87f1daeeb0
https://github.com/llvm/llvm-project/commit/a42a1c84c1305d785ca58d271d5f2f87f1daeeb0
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/unittests/ExecutionEngine/Orc/InProcessEPCTest.cpp
Log Message:
-----------
[ORC] Fix reinterpret_cast warning. (#207874)
https://github.com/llvm/llvm-project/pull/206725#issuecomment-4896222897
reported warnings on windows builds due to reinterpret_cast:
warning C4312: 'reinterpret_cast': conversion from 'unsigned int' to
'void *' of greater size
This commit fixes the issue by using ExecutorAddr::toPtr for conversion
instead of reinterpret_cast.
Commit: 5cd8f2f847101effad54a88936abe5e3bcb7e884
https://github.com/llvm/llvm-project/commit/5cd8f2f847101effad54a88936abe5e3bcb7e884
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M flang/test/Driver/fsave-optimization-record.f90
M lld/test/ELF/lto/stats-file-option.ll
M llvm/docs/Remarks.rst
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/test/CodeGen/AArch64/aarch64-large-stack-spbump.mir
M llvm/test/CodeGen/AArch64/aarch64-vector-pcs.mir
M llvm/test/CodeGen/AArch64/addg_subg.mir
M llvm/test/CodeGen/AArch64/cfi_restore.mir
M llvm/test/CodeGen/AArch64/chkstk.ll
M llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
M llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir
M llvm/test/CodeGen/AArch64/emit-prologue-clobber-verification.mir
M llvm/test/CodeGen/AArch64/extra-callee-save.mir
M llvm/test/CodeGen/AArch64/framelayout-fpr128-spill.mir
M llvm/test/CodeGen/AArch64/framelayout-frame-record.mir
M llvm/test/CodeGen/AArch64/framelayout-offset-immediate-change.mir
M llvm/test/CodeGen/AArch64/framelayout-scavengingslot-stack-hazard.mir
M llvm/test/CodeGen/AArch64/framelayout-scavengingslot.mir
M llvm/test/CodeGen/AArch64/framelayout-split-sve.mir
M llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir
M llvm/test/CodeGen/AArch64/framelayout-sve-calleesaves-fix.mir
M llvm/test/CodeGen/AArch64/framelayout-sve-fixed-width-access.mir
M llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir
M llvm/test/CodeGen/AArch64/framelayout-sve-win.mir
M llvm/test/CodeGen/AArch64/framelayout-sve.mir
M llvm/test/CodeGen/AArch64/large-stack-offset-calcs.mir
M llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
M llvm/test/CodeGen/AArch64/lr-reserved-for-ra-live-in.ll
M llvm/test/CodeGen/AArch64/machine-outliner-bti.mir
M llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
M llvm/test/CodeGen/AArch64/machine-outliner-no-noreturn-no-stack.mir
M llvm/test/CodeGen/AArch64/machine-outliner-noreturn-no-stack.mir
M llvm/test/CodeGen/AArch64/machine-outliner-regsave.mir
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir
M llvm/test/CodeGen/AArch64/machine-outliner-size-info.mir
M llvm/test/CodeGen/AArch64/machine-outliner.mir
M llvm/test/CodeGen/AArch64/memtag-stg-loop-reg-pressure.mir
M llvm/test/CodeGen/AArch64/no-xzr-liveins.mir
M llvm/test/CodeGen/AArch64/pr157252.mir
M llvm/test/CodeGen/AArch64/preserve.ll
M llvm/test/CodeGen/AArch64/prologue-epilogue-remarks.mir
M llvm/test/CodeGen/AArch64/reg-scavenge-frame.mir
M llvm/test/CodeGen/AArch64/reloc-specifiers.mir
M llvm/test/CodeGen/AArch64/settag-merge.mir
M llvm/test/CodeGen/AArch64/spill-stack-realignment.mir
M llvm/test/CodeGen/AArch64/stack-guard-reassign-sve.mir
M llvm/test/CodeGen/AArch64/stack-guard-reassign.mir
M llvm/test/CodeGen/AArch64/stack-id-pei-alloc.mir
M llvm/test/CodeGen/AArch64/stack-id-stackslot-scavenging.mir
M llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir
M llvm/test/CodeGen/AArch64/stack-probing-no-scratch-reg.mir
M llvm/test/CodeGen/AArch64/stack-probing-shrink-wrap.mir
M llvm/test/CodeGen/AArch64/stack-tagging-epilogue-fold.mir
M llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir
M llvm/test/CodeGen/AArch64/statepoint-call-lowering-lr.ll
M llvm/test/CodeGen/AArch64/statepoint-call-lowering-sp.ll
M llvm/test/CodeGen/AArch64/sve-calling-convention.ll
M llvm/test/CodeGen/AArch64/sve-ld1r.mir
M llvm/test/CodeGen/AArch64/sve-ldN.mir
M llvm/test/CodeGen/AArch64/sve-ldnf1.mir
M llvm/test/CodeGen/AArch64/sve-ldst-multi-vec.mir
M llvm/test/CodeGen/AArch64/sve-ldstnt1.mir
M llvm/test/CodeGen/AArch64/sve-stN.mir
M llvm/test/CodeGen/AArch64/unreachable-emergency-spill-slot.mir
M llvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
M llvm/test/CodeGen/AArch64/wineh-frame-predecrement.mir
M llvm/test/CodeGen/AArch64/wineh-frame-scavenge.mir
M llvm/test/CodeGen/AArch64/wineh-frame0.mir
M llvm/test/CodeGen/AArch64/wineh-frame1.mir
M llvm/test/CodeGen/AArch64/wineh-frame2.mir
M llvm/test/CodeGen/AArch64/wineh-frame3.mir
M llvm/test/CodeGen/AArch64/wineh-frame4.mir
M llvm/test/CodeGen/AArch64/wineh-frame5.mir
M llvm/test/CodeGen/AArch64/wineh-frame6.mir
M llvm/test/CodeGen/AArch64/wineh-frame7.mir
M llvm/test/CodeGen/AArch64/wineh-frame8.mir
M llvm/test/CodeGen/AArch64/wineh-save-lrpair1.mir
M llvm/test/CodeGen/AArch64/wineh-save-lrpair2.mir
M llvm/test/CodeGen/AArch64/wineh-save-lrpair3.mir
M llvm/test/CodeGen/AArch64/wineh1.mir
M llvm/test/CodeGen/AArch64/wineh2.mir
M llvm/test/CodeGen/AArch64/wineh3.mir
M llvm/test/CodeGen/AArch64/wineh4.mir
M llvm/test/CodeGen/AArch64/wineh5.mir
M llvm/test/CodeGen/AArch64/wineh6.mir
M llvm/test/CodeGen/AArch64/wineh7.mir
M llvm/test/CodeGen/AArch64/wineh8.mir
M llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir
M llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
M llvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir
M llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
M llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
M llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir
M llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir
M llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
M llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir
M llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir
M llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-u32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-scc-clobber.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
M llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir
M llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi-gfx1250.mir
M llvm/test/CodeGen/AMDGPU/frame-index-elimination-tied-operand.mir
M llvm/test/CodeGen/AMDGPU/frame-index.mir
M llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir
M llvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir
M llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
M llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir
M llvm/test/CodeGen/AMDGPU/machine-function-info-cwsr.ll
M llvm/test/CodeGen/AMDGPU/mcinstlower-external-symbol-reloc.mir
M llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir
M llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
M llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir
M llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
M llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
M llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
M llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
M llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir
M llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
M llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
M llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir
M llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir
M llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
M llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir
M llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir
M llvm/test/CodeGen/AMDGPU/spillv16.mir
M llvm/test/CodeGen/AMDGPU/spillv16Kernel.mir
M llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir
M llvm/test/CodeGen/AMDGPU/track-spilled-vgpr-liveness.mir
M llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir
M llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir
M llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill-dead-frame-in-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir
M llvm/test/CodeGen/AMDGPU/wwm-reg-shift-down-gfx11plus.mir
M llvm/test/CodeGen/ARM/execute-only-save-cpsr.mir
M llvm/test/CodeGen/ARM/fpoffset_overflow.mir
M llvm/test/CodeGen/ARM/interrupt-save-fp-attr-status-regs.mir
M llvm/test/CodeGen/ARM/machine-outliner-calls.mir
M llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-arm.mir
M llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir
M llvm/test/CodeGen/ARM/nonreserved-callframe-with-basereg.mir
M llvm/test/CodeGen/ARM/noreturn-csr-skip.mir
M llvm/test/CodeGen/ARM/pei-swiftself.mir
M llvm/test/CodeGen/ARM/register-scavenger-exceptions.mir
M llvm/test/CodeGen/ARM/stack_frame_offset.mir
M llvm/test/CodeGen/ARM/tldrlit_ga_size.mir
M llvm/test/CodeGen/BPF/BTF/func-nocall-undef-dead-arg.ll
M llvm/test/CodeGen/Hexagon/aligna-prologue-expansion.mir
M llvm/test/CodeGen/Hexagon/livephysregs-regmask-clobber.mir
M llvm/test/CodeGen/Hexagon/spill-vector-alignment.mir
M llvm/test/CodeGen/LoongArch/stack-probing-frame-setup.mir
M llvm/test/CodeGen/LoongArch/statepoint-call-lowering-r1.ll
M llvm/test/CodeGen/M68k/CollapseMOVEM.mir
M llvm/test/CodeGen/M68k/is-pcrel-register-operand-legal.mir
M llvm/test/CodeGen/MIR/AArch64/hasstackframe.mir
M llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
M llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
M llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
M llvm/test/CodeGen/MIR/X86/diexpr-win32.mir
M llvm/test/CodeGen/Mips/copy-fp64.ll
M llvm/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir
M llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
M llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
M llvm/test/CodeGen/PowerPC/aix-csr.ll
M llvm/test/CodeGen/PowerPC/aix32-crsave.mir
M llvm/test/CodeGen/PowerPC/aix32-vector-pair-cc-spills.ll
M llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll
M llvm/test/CodeGen/PowerPC/alloca-crspill.ll
M llvm/test/CodeGen/PowerPC/byval-agg-info.ll
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M llvm/test/CodeGen/PowerPC/mflr-store.mir
M llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
M llvm/test/CodeGen/PowerPC/prolog_vec_spills.mir
M llvm/test/CodeGen/PowerPC/stack_pointer_vec_spills.mir
M llvm/test/CodeGen/RISCV/determine-callee-saves-gpr.mir
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M llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
M llvm/test/CodeGen/RISCV/pr53662.mir
M llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir
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M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll
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M llvm/test/CodeGen/Thumb2/mve-stacksplot.mir
M llvm/test/CodeGen/Thumb2/scavenge-lr.mir
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M llvm/test/CodeGen/X86/ipra-reg-usage.ll
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M llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic3.macho.remarks.arm64.opt.yaml
M llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/fat.macho.remarks.x86_64.opt.yaml
M llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/fat.macho.remarks.x86_64h.opt.yaml
M llvm/test/tools/llvm-remarkutil/Inputs/two-remarks.bitstream
M llvm/test/tools/llvm-remarkutil/Inputs/two-remarks.yaml
M llvm/test/tools/llvm-remarkutil/convert.test
M llvm/test/tools/llvm-remarkutil/size-diff/Inputs/1-func-1-instr-1-stack.yaml
M llvm/test/tools/llvm-remarkutil/size-diff/Inputs/1-func-2-instr-2-stack.yaml
M llvm/test/tools/llvm-remarkutil/size-diff/Inputs/2-identical-func-1-instr-1-stack.yaml
M llvm/test/tools/llvm-remarkutil/size-diff/Inputs/inconvertible-integer.yaml
M llvm/test/tools/llvm-remarkutil/size-diff/Inputs/no-instruction-count-remarks.yaml
M llvm/test/tools/llvm-remarkutil/size-diff/Inputs/unexpected-key.yaml
M llvm/tools/llvm-exegesis/lib/Assembler.cpp
M llvm/tools/llvm-remarkutil/RemarkSizeDiff.cpp
Log Message:
-----------
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
This is primarily to ensure consistenct with the new pass manager where
the name of the pass is already prolog-epilog, which is more consistent
with our existing naming scheme. This is necessary to be able to run
existing llc invocations that explicitly specify prolog-epilog under the
NewPM automatically.
Assisted by Gemini.
Commit: 0ad19f403165d8fc1596fb2fef9c940e941c54df
https://github.com/llvm/llvm-project/commit/0ad19f403165d8fc1596fb2fef9c940e941c54df
Author: hulxv <hulxxv at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libc/shared/builtins.h
A libc/shared/builtins/subsf3.h
M libc/src/__support/builtins/CMakeLists.txt
A libc/src/__support/builtins/subsf3.h
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_builtins_test.cpp
Log Message:
-----------
[libc] add shared subsf3 builtin (#205677)
Re-exposes LLVM-libc's `__subsf3` as `shared::subsf3` for reuse by
compiler-rt's builtins.
Stacked change - merge these first:
- #200094
- #205669
- #205670
- #205671
- #205672
- #205673
- #205674
- #205675
- #205676
Part of #197824
Commit: d49c6da56c60e3859b686ed2434fed7cab92bff9
https://github.com/llvm/llvm-project/commit/d49c6da56c60e3859b686ed2434fed7cab92bff9
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M .ci/compute_projects.py
M .ci/compute_projects_test.py
R .github/workflows/libclang-python-tests.yml
Log Message:
-----------
CI: move libclang python bindings tests to main CI (#201677)
This removes the separate python bindings CI, which run on the GitHub
free runners and take more than one hour to build libclang.
The tests are executed instead in the monolithic pipelines, whenever
clang would be tested.
That only tests whatever python version we set up for that pipeline.
This is fine in terms of resources because all the dependencies are
built anyway, and the tests themselves take less than one second to run
on the free runners.
Commit: 1b9723b3cd661b53f8ea891204efdb95a9c1c678
https://github.com/llvm/llvm-project/commit/1b9723b3cd661b53f8ea891204efdb95a9c1c678
Author: Yi Zhang <cathyzhyi at google.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/include/llvm/ADT/APInt.h
M llvm/unittests/ADT/APIntTest.cpp
Log Message:
-----------
Fix APInt::concat for zero-width operands (#207475)
APInt::concat triggered undefined behavior (invalid shift exponent) when
concatenating a zero-width operand with a 64-bit operand on the fast
path (combined width <= 64). For example, `I0.concat(I64)` resulted in
`U.VAL << 64`, which is UB.
Fix by checking for zero-width operands early and returning the other
operand. Added regression tests to `APIntTest.cpp`.
Commit: 5c715d56884364a3b05acb4d3e6b52a911f14667
https://github.com/llvm/llvm-project/commit/5c715d56884364a3b05acb4d3e6b52a911f14667
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang-tools-extra/docs/ReleaseNotes.rst
M clang/lib/Tooling/Tooling.cpp
M clang/unittests/Tooling/ToolingTest.cpp
Log Message:
-----------
[Tooling] Preserve backslashes in POSIX source paths (#207499)
On POSIX, backslashes are valid filename characters. Avoid converting
them to slashes when computing absolute source paths in LibTooling,
since doing so changes paths such as `a\b.cc` into `a/b.cc`.
Closes #207396
Commit: 664e704bd5da24971bfdedee410415537e8d2e45
https://github.com/llvm/llvm-project/commit/664e704bd5da24971bfdedee410415537e8d2e45
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M flang/include/flang/Semantics/semantics.h
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Driver/bbc-implicit-use-module.f90
M flang/tools/bbc/bbc.cpp
Log Message:
-----------
[flang] Add ability to implicitly use a module (#207824)
Add parser and semantics plumbing for configured implicit USE modules,
reusing
the normal USE-association path so public symbols and common blocks are
imported
consistently.
Commit: c45ff74fbe38151a21e1877b7e0c703b1590f101
https://github.com/llvm/llvm-project/commit/c45ff74fbe38151a21e1877b7e0c703b1590f101
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
Log Message:
-----------
[RISCV] Sync RISCVSystemOperands.td order/sections with priv-csrs.adoc from riscv-isa-manual. NFC (#207803)
Commit: c392657d4992148cb7cd5ebd94f12d2ffab949b4
https://github.com/llvm/llvm-project/commit/c392657d4992148cb7cd5ebd94f12d2ffab949b4
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
A llvm/test/CodeGen/SPIRV/pointers/array-stride-subbyte.ll
Log Message:
-----------
[SPIR-V] Fix ArrayStride truncation to 0 for sub-byte element types (#207140)
addArrayStrideDecorations computed the stride as `getTypeSizeInBits/8`
which truncates to 0 for sub-byte element types such as i1
0 strides are disallowed in spec
---------
Co-authored-by: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Commit: 2ef13ce61b9625080e20df1e13763aa4d4fb5964
https://github.com/llvm/llvm-project/commit/2ef13ce61b9625080e20df1e13763aa4d4fb5964
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
Log Message:
-----------
[AMDGPU] Fix whole-wave function prologue to set EXEC to -1 (#207781)
A whole-wave function body must run with all lanes on. With no WWM
spills the prologue emitted `S_XOR_SAVEEXEC`, giving `EXEC` =
`~entryEXEC`
Commit: b068ae9e376b1e3d721064e140e638cad076d0bc
https://github.com/llvm/llvm-project/commit/b068ae9e376b1e3d721064e140e638cad076d0bc
Author: Zachary Yedidia <zyedidia at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M clang/lib/Basic/Targets/X86.cpp
M llvm/docs/LFI.rst
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/MC/MCLFI.cpp
M llvm/lib/Target/X86/MCTargetDesc/CMakeLists.txt
A llvm/lib/Target/X86/MCTargetDesc/X86MCLFIRewriter.cpp
A llvm/lib/Target/X86/MCTargetDesc/X86MCLFIRewriter.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86Subtarget.h
M llvm/lib/TargetParser/Triple.cpp
A llvm/test/CodeGen/X86/lfi-sibcall.ll
A llvm/test/MC/X86/LFI/abi-note.s
A llvm/test/MC/X86/LFI/syscall.s
A llvm/test/MC/X86/LFI/thread-pointer-errors.s
A llvm/test/MC/X86/LFI/thread-pointer.s
Log Message:
-----------
[LFI][X86] Add X86 LFI target and system instruction rewrites (#189569)
This PR introduces an x86-64 backend for Lightweight Fault Isolation
(LFI), similar to the one being developed for AArch64. LFI is a
compiler-based mechanism that enables efficient in-process sandboxing.
See the RFC from last fall for details.
This PR adds the `x86_64_lfi` target (similar to `aarch64_lfi`), sets up
reserved registers, and implements some initial rewrites for system
instructions (system calls and TLS accesses). The rewrites are done at
the MC level, using the `MCLFIRewriter` infrastructure. I have updated
the documentation to describe the x86-64 sandboxing scheme and to list
rewrites that will be implemented in future PRs (to keep each individual
PR small).
For performance and compatibility reasons, the plan is currently to use
bundling for maintaining control-flow integrity in the sandbox, which
is not yet supported. For now we are setting up the rewrites without using
bundling, but we can also use a CFI mechanism based on shadow
stack+endbr in order to have something usable while bundling is
in progress.
Commit: a849f52b7930ead34ce6337763cff9977f5f61aa
https://github.com/llvm/llvm-project/commit/a849f52b7930ead34ce6337763cff9977f5f61aa
Author: rdevshp <rdevshp at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
M llvm/test/Transforms/InstCombine/conditional-variable-length-signext-after-high-bit-extract.ll
Log Message:
-----------
[InstCombine] Fix assertion failure in `foldVariableSignZeroExtensionOfVariableHighBitExtract` (#205148)
This PR fixes crash for the following program:
```
define i16 @d(i16 %x, i4 %n) {
entry:
%highbits = lshr i16 %x, 1
%sub1 = sub i4 0, %n
%z1 = zext i4 %sub1 to i16
%shl = shl i16 %highbits, %z1
%sub2 = sub i4 0, %n
%z2 = zext i4 %sub2 to i16
%ashr = ashr i16 %shl, %z2
ret i16 %ashr
}
```
when running `opt -passes=instcombine prog.ll -S`.
Assisted-by: Codex
Commit: fa9fac7ae909053993e96a1c2aecc981b08f70cb
https://github.com/llvm/llvm-project/commit/fa9fac7ae909053993e96a1c2aecc981b08f70cb
Author: Zachary Yedidia <zyedidia at gmail.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M clang/lib/Basic/Targets/X86.cpp
M llvm/docs/LFI.rst
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/MC/MCLFI.cpp
M llvm/lib/Target/X86/MCTargetDesc/CMakeLists.txt
R llvm/lib/Target/X86/MCTargetDesc/X86MCLFIRewriter.cpp
R llvm/lib/Target/X86/MCTargetDesc/X86MCLFIRewriter.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86Subtarget.h
M llvm/lib/TargetParser/Triple.cpp
R llvm/test/CodeGen/X86/lfi-sibcall.ll
R llvm/test/MC/X86/LFI/abi-note.s
R llvm/test/MC/X86/LFI/syscall.s
R llvm/test/MC/X86/LFI/thread-pointer-errors.s
R llvm/test/MC/X86/LFI/thread-pointer.s
Log Message:
-----------
Revert "[LFI][X86] Add X86 LFI target and system instruction rewrites" (#207891)
Reverts llvm/llvm-project#189569
Commit: 025e2adf1c774d17415b72244722aa740fe4d712
https://github.com/llvm/llvm-project/commit/025e2adf1c774d17415b72244722aa740fe4d712
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M lldb/source/Host/freebsd/Host.cpp
Log Message:
-----------
[LLDB][FreeBSD] Fix build from FileSpec change (#207819)
FileSpec now returns llvm::StringRef instead of ConstString. As a
result, we don't need to use GetCString to get the raw string. Remove it
to fix build failure.
Fixes: f9b5264523b1 (#206802)
Commit: b838b0cc1c76c34e57d70d5d259382ac0d764cca
https://github.com/llvm/llvm-project/commit/b838b0cc1c76c34e57d70d5d259382ac0d764cca
Author: Ying Chen <chenying at inchitech.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td
M llvm/test/MC/RISCV/rv32zclsd-invalid.s
Log Message:
-----------
[RISCV][MC] Improve diagnostics for Zclsd RV32 GPR pair operands (#207639)
Add dedicated assembler diagnostics for the RV32 GPR pair operands used
by
Zclsd compressed load/store pair instructions.
After the RISC-V asm parser started reporting multiple near-miss
reasons, these
operands still fell back to the generic "invalid operand for
instruction" note.
Give them explicit diagnostic types and messages so invalid register
pairs report
the expected pair constraints.
Commit: 26fbd61932b41a36a1fee3bcdfbb6800ca5c09b3
https://github.com/llvm/llvm-project/commit/26fbd61932b41a36a1fee3bcdfbb6800ca5c09b3
Author: Ying Chen <chenying at inchitech.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M lld/test/ELF/gc-sections-keep-shared-start.s
Log Message:
-----------
[ELF,test] Fix FileCheck RUN line in gc-sections-keep-shared-start.s (#207678)
Fix a malformed multiline RUN line.
---------
Co-authored-by: Fangrui Song <i at maskray.me>
Commit: 25b205eb9413e418732d0d5b526511c3ce37c6d9
https://github.com/llvm/llvm-project/commit/25b205eb9413e418732d0d5b526511c3ce37c6d9
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/FIRToMemRef.cpp
Log Message:
-----------
[FIRToMemRef] Doc collectSliceInfoFrom, getMemrefIndices, canonicalizeIndex (#207699)
Also drops the unused `converted` parameter from getMemrefIndices. The
internal workings of these functions were not easy to understand for me
so I worked with Claude to document with examples. Hopefully, that makes
the code easier to read. I reviewed the docs and corrected some obvious
hallucinations produced by the agent.
Co-Authored-By: Claude Sonnet 4.6 noreply at anthropic.com
Commit: 51a378885ae5f48c2b1521700fd5732a5aae00aa
https://github.com/llvm/llvm-project/commit/51a378885ae5f48c2b1521700fd5732a5aae00aa
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/TableGen/StringToOffsetTable.cpp
Log Message:
-----------
[TableGen] Separate string when digit follows octal escape (#207807)
Silence MSVC warning C4125 by separating the string literals when an
octal escape sequence is followed by a decimal char.
Commit: cb19f2b288a94e62c93f3e862cb697c14a7326fb
https://github.com/llvm/llvm-project/commit/cb19f2b288a94e62c93f3e862cb697c14a7326fb
Author: Ian Anderson <iana at apple.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M clang/test/OffloadTools/clang-offload-bundler/zstd.c
Log Message:
-----------
[clang][test][darwin] Driver/clang-offload-bundler-zstd.c fails on macOS (#207876)
Driver/clang-offload-bundler-zstd.c isn't supported on Darwin, but
neglected to list the macosx target.
Commit: cbf8048aa1427166045a602e0bc29127c1d8274c
https://github.com/llvm/llvm-project/commit/cbf8048aa1427166045a602e0bc29127c1d8274c
Author: SiHuaN <liyongtai at iscas.ac.cn>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
Log Message:
-----------
[RISCV][P-ext] Add codegen for packed absolute difference sum (#207314)
The pabdsumu/pabdsumau instructions compute the sum of absolute differences
of packed unsigned bytes; pabdsumau also accumulates into rd.
Add the llvm.riscv.pabdsumu and pabdsumau intrinsics. A single-GPR source is
selected directly to pabdsumu.b/pabdsumau.b with isel patterns. A 64-bit
GPRPair source on RV32 has no paired instruction, so it is split during
lowering into two v4i8 halves: reduce the low half (folding in rd when
accumulating), then accumulate the high half into that partial sum.
Cases with a target-illegal result are handled in ReplaceNodeResults:
RV64, i32 result: reduce at i64 and truncate (a 32-bit source is
zero-extended first).
RV32, i64 result: reduce each half with pabdsumu.b and combine the
partial sums with a widening add (waddu/waddau).
Commit: 0fc9beeadf2a415553047989154a8df7f89fd8dc
https://github.com/llvm/llvm-project/commit/0fc9beeadf2a415553047989154a8df7f89fd8dc
Author: Lucas Mellone <github.snugness349 at passinbox.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libcxx/include/__ranges/adjacent_transform_view.h
A libcxx/test/libcxx/ranges/range.adaptors/range.adjacent.transform/nodiscard.verify.cpp
Log Message:
-----------
[libc++][ranges] Applied [[nodiscard]] to `adjacent_transform_view` (#205900)
[[nodiscard]] should be applied to functions where discarding the return
value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html
- https://wg21.link/range.adjacent.transform
Towards https://github.com/llvm/llvm-project/issues/172124
---------
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Commit: 8992cdf458f78c5ef9b018c92234658fc78cfd80
https://github.com/llvm/llvm-project/commit/8992cdf458f78c5ef9b018c92234658fc78cfd80
Author: Lucas Mellone <github.snugness349 at passinbox.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libcxx/include/__ranges/join_view.h
A libcxx/test/libcxx/ranges/range.adaptors/range.join/nodiscard.verify.cpp
Log Message:
-----------
[libc++][ranges] Applied [[nodiscard]] to `join_view` (#206838)
[[nodiscard]] should be applied to functions where discarding the return
value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html
- https://wg21.link/range.join
Towards https://github.com/llvm/llvm-project/issues/172124
Commit: 347e97f815e2b866aa07b8e0f6364a79280ad2fb
https://github.com/llvm/llvm-project/commit/347e97f815e2b866aa07b8e0f6364a79280ad2fb
Author: quic-k <kushpal at qti.qualcomm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/test/Driver/hexagon-toolchain-picolibc.c
Log Message:
-----------
[Clang][Hexagon] Use flat library directory layout for Picolibc (#201326)
Signed-off-by: Kushal Pal <kushpal at qti.qualcomm.com>
Commit: a6575e8ea5a638259d4051ebfb1430bf1cc2795b
https://github.com/llvm/llvm-project/commit/a6575e8ea5a638259d4051ebfb1430bf1cc2795b
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
Log Message:
-----------
[clang][bytecode] Use `PtrView` in `CheckActive()` (#207756)
Commit: bc2b50fbca41852434db4c3f066989e036b9b962
https://github.com/llvm/llvm-project/commit/bc2b50fbca41852434db4c3f066989e036b9b962
Author: David Green <david.green at arm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/arith-overflow.ll
M llvm/test/Analysis/CostModel/AArch64/arith.ll
M llvm/test/Analysis/CostModel/AArch64/div.ll
M llvm/test/Analysis/CostModel/AArch64/mul.ll
M llvm/test/Analysis/CostModel/AArch64/rem.ll
Log Message:
-----------
[AArch64] Add a basic i128 mul cost. (#203271)
This adds a basic cost for i128 multiply instructions, which has a basic
cost of 4 and scales n^2 with bitsize.
Commit: 08ed6acb7e0d328ee02d4c15b7b6bcdd943323e3
https://github.com/llvm/llvm-project/commit/08ed6acb7e0d328ee02d4c15b7b6bcdd943323e3
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libc/src/__support/File/CMakeLists.txt
M libc/src/__support/File/dir.cpp
M libc/src/__support/File/dir.h
M libc/src/__support/File/linux/dir.cpp
Log Message:
-----------
[libc] Improve Dir class safety, performance, and style (#207214)
Addressed issues in the Dir class identified during review:
* Safety: Added bounds and validation checks in Dir::read to prevent
out-of-bounds reads on corrupted input.
* Performance: Aligned the internal buffer to struct dirent to prevent
unaligned memory access, and increased the buffer size to 4096 to reduce
syscall overhead.
* Style: Replaced the system <dirent.h> include with a new proxy header
(struct_dirent.h) to avoid system dependencies, and fixed relative
includes.
* Refactoring: Moved platform-specific record length access to a
platform helper (platform_dir_reclen).
* CMake: Updated dependencies for the dir target.
Assisted-by: Automated tooling, human reviewed.
Commit: a2031641ed0db092d7f7a5371f4710b9e260ec4a
https://github.com/llvm/llvm-project/commit/a2031641ed0db092d7f7a5371f4710b9e260ec4a
Author: David Green <david.green at arm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
R llvm/test/CodeGen/AArch64/arm64-2013-02-12-shufv8i8.ll
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/bf16-shuffle.ll
M llvm/test/CodeGen/AArch64/build-vector-two-dup.ll
M llvm/test/CodeGen/AArch64/implicitly-set-zero-high-64-bits.ll
M llvm/test/CodeGen/AArch64/insert-subvector.ll
M llvm/test/CodeGen/AArch64/insertshuffleload.ll
M llvm/test/CodeGen/AArch64/neon-extracttruncate.ll
M llvm/test/CodeGen/AArch64/neon-shuffle-vector-tbl.ll
M llvm/test/CodeGen/AArch64/neon-wide-splat.ll
M llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
M llvm/test/CodeGen/AArch64/shuffle-extend.ll
M llvm/test/CodeGen/AArch64/shuffle-slide-to-shift.ll
M llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
M llvm/test/CodeGen/AArch64/shuffles.ll
Log Message:
-----------
[AArch64][GlobalISel] Add more shuffle test coverage. NFC (#207907)
Commit: 39f64b9045441225f6229d3ea5502ae5a03307f8
https://github.com/llvm/llvm-project/commit/39f64b9045441225f6229d3ea5502ae5a03307f8
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
M llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_eq.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ne.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_sge.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_slt.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_uge.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ult.ll
Log Message:
-----------
[RISCV] Fix Predicates in SFB to MVccI (#207806)
Commit: 93509a564b4dda593766f4395873175ede1a30ed
https://github.com/llvm/llvm-project/commit/93509a564b4dda593766f4395873175ede1a30ed
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
A llvm/test/CodeGen/LoongArch/get-rounding.ll
M llvm/test/CodeGen/LoongArch/set-rounding.ll
Log Message:
-----------
[LoongArch] Support ISD::GET_ROUNDING (llvm.get.rounding) (#207319)
Commit: c6cadf901add7de1751cb27856aec90e47849cf4
https://github.com/llvm/llvm-project/commit/c6cadf901add7de1751cb27856aec90e47849cf4
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M flang-rt/lib/runtime/CMakeLists.txt
M runtimes/cmake/config-Fortran.cmake
Log Message:
-----------
[Fortran] Use INTERFACE targets for options and dependencies (#193469)
Use CMake INTERFACE libraries to express dependencies and common build
options.
Using INTERFACE libraries was proposed here:
https://github.com/llvm/llvm-project/pull/171610#discussion_r3122187957
Since such libraries can also propagate build options use this instead
of `target_compile_options`. Unfortunately this does not mean we can get
rid of `flang_module_target` because it also needs to set the module
output directory.
---------
Co-authored-by: Tarun Prabhu <tarunprabhu at gmail.com>
Commit: 1a5376e062e3f3b99ffce25e24e53182202e06b9
https://github.com/llvm/llvm-project/commit/1a5376e062e3f3b99ffce25e24e53182202e06b9
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AVR/AVRISelLowering.cpp
A llvm/test/CodeGen/AVR/cmp-sgt-i128.ll
Log Message:
-----------
[AVR] Fix overflow in SETGT lowering (#207737)
https://github.com/llvm/llvm-project/pull/182690 fixed this for the
SETUGT case, but the same issue exists for SETGT, so fix it in the same
way.
Similar to the SETUGT case this needs a i128 comparison to reproduce,
otherwise the comparison gets folded away too early.
Commit: 47b819b866636fb1770f78da3f45ebd64d5f9875
https://github.com/llvm/llvm-project/commit/47b819b866636fb1770f78da3f45ebd64d5f9875
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpermi.ll
Log Message:
-----------
[LoongArch] Fix vpermi.w legalization with undef elements (#207751)
For the MaskSize==8 case, the code was comparing mask elements that
could be undef (-1). This could result in a miscompile (where -1 + 4 ==
3, which crosses from the high half to the low half) or the pattern not
matching (because -1 doesn't match the other mask element).
Fix this by explicitly handling undef elements in the code. If the high
half is undef, we can just ignore. If the low half is undef, we need to
use the value from the high half shifted down by 4. If neither are
undef, use the original check.
Commit: 5bca42d7d7cd55642e9e63fa3b4da11245d025c3
https://github.com/llvm/llvm-project/commit/5bca42d7d7cd55642e9e63fa3b4da11245d025c3
Author: Jaydeep Chauhan <chauhan.jaydeep.ashwinbhai at intel.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/BuiltinsX86_64.td
M clang/include/clang/Options/Options.td
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Headers/CMakeLists.txt
R clang/lib/Headers/amxtf32intrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaX86.cpp
R clang/test/CodeGen/X86/amx_tf32.c
R clang/test/CodeGen/X86/amx_tf32_api.c
R clang/test/CodeGen/X86/amx_tf32_errors.c
R clang/test/CodeGen/X86/amx_tf32_inline_asm.c
M clang/test/Driver/x86-target-features.c
M clang/test/Preprocessor/predefined-arch-macros.c
M clang/test/Preprocessor/x86_target_features.c
M compiler-rt/lib/builtins/cpu_model/x86.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
R llvm/test/CodeGen/X86/amx-tf32-internal.ll
R llvm/test/CodeGen/X86/amx-tf32-intrinsics.ll
R llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-tf32.txt
R llvm/test/MC/X86/AMX/x86-64-amx-tf32-att.s
R llvm/test/MC/X86/AMX/x86-64-amx-tf32-intel.s
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[X86] Remove AMX-TF32 (#207673)
Per Intel Architecture Instruction Set Extensions Programming Reference
rev. 62 https://cdrdv2.intel.com/v1/dl/getContent/922690 Revision
History entry for revision -062
Commit: 5c01d66e97208cd8acf6d7db72d9cfcbb4cd883f
https://github.com/llvm/llvm-project/commit/5c01d66e97208cd8acf6d7db72d9cfcbb4cd883f
Author: Folkert de Vries <folkert at folkertdev.nl>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/test/CodeGen/win64-i128.c
Log Message:
-----------
[AArch64][msvc] allow higher align than slot size in va_arg (#207591)
Fixes https://github.com/llvm/llvm-project/issues/207584
On aarch64 windows, an `__int128` argument is passed with alignment 16,
but was read with an alignment of 8. Based on the MSVC assembly and how
e.g. aarch64 darwin handles this, I think it's correct to set
`AllowHigherAlign = true`.
Commit: 57a7e7538cfc73184b8280160e8d89cedab04c5d
https://github.com/llvm/llvm-project/commit/57a7e7538cfc73184b8280160e8d89cedab04c5d
Author: Folkert de Vries <folkert at folkertdev.nl>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/fp128-cast.ll
Log Message:
-----------
[X86][Windows] use `LowerWin64_INT128_TO_FP` for `u128` to `f128` conversion (#207285)
This change fixes an ABI issue where the signed conversion passes a
`i128` different from a `u128`, and crucially different from GCC.
https://godbolt.org/z/x3daY3rej
```diff
--- <unnamed>
+++ <unnamed>
@@ -1,15 +1,15 @@
-conv_from_i128:
+conv_from_u128:
push rsi
- sub rsp, 64
+ sub rsp, 48
mov rsi, rcx
- movaps xmm0, xmmword ptr [rdx]
- movaps xmmword ptr [rsp + 48], xmm0
+ mov rax, qword ptr [rdx]
+ mov r8, qword ptr [rdx + 8]
lea rcx, [rsp + 32]
- lea rdx, [rsp + 48]
- call __floattitf
+ mov rdx, rax
+ call __floatuntitf
movaps xmm0, xmmword ptr [rsp + 32]
movaps xmmword ptr [rsi], xmm0
mov rax, rsi
- add rsp, 64
+ add rsp, 48
pop rsi
ret
```
The signed case being correct is apparently due to a special
windows-specific path being chosen. The unsigned version bailed out too
early. So, I've changed `LowerUINT_TO_FP` to be more like
`LowerSINT_TO_FP`. In particular this moves the "Bail out when we don't
have native conversion instructions." down a bit, so that
`LowerWin64_INT128_TO_FP` is actually used.
I've then also added some testing for win64 SSE. I'm not sure if the
other target features are as relevant but I can add those too if
helpful.
This was found by running the `rust-lang/compiler-builtins` tests with a
build that includes https://github.com/llvm/llvm-project/pull/204887.
Commit: c5026e4e3332acf88bb304c37137bd247fa12b25
https://github.com/llvm/llvm-project/commit/c5026e4e3332acf88bb304c37137bd247fa12b25
Author: Sudharsan Veeravalli <svs at qti.qualcomm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M lldb/source/Plugins/Architecture/CMakeLists.txt
A lldb/source/Plugins/Architecture/RISCV/ArchitectureRISCV.cpp
A lldb/source/Plugins/Architecture/RISCV/ArchitectureRISCV.h
A lldb/source/Plugins/Architecture/RISCV/CMakeLists.txt
A lldb/unittests/Architecture/CMakeLists.txt
A lldb/unittests/Architecture/RISCV/ArchitectureRISCVTest.cpp
A lldb/unittests/Architecture/RISCV/CMakeLists.txt
M lldb/unittests/CMakeLists.txt
Log Message:
-----------
[RISCV][LLDB] Add RISC-V Architecture plugin for trap validation (#207675)
Add a minimal `RISC-V Architecture` plugin and implement
`IsValidTrapInstruction` for trap opcodes. The plugin recognizes riscv32
and riscv64 targets and validates 32-bit `EBREAK` and 16-bit `C.EBREAK`.
On RISC-V, `EBREAK` traps with the PC still pointing at the `EBREAK`
instruction. A plain continue resumes from that same PC and traps again.
This issue was found while trying to run the `TestBuiltinDebugTrap` test
case locally on a `RISC-V QEMU`.
Added a cpp unit test to verify the behaviour of
`IsValidTrapInstruction`. I've chosen to verify `EBREAK` on `riscv32`
and `C.EBREAK` on `riscv64` so that there is some coverage for both
targets.
Assisted by gpt-5.5
Commit: 70646dd3eda3e64fc94b44d7403f946cd7455b92
https://github.com/llvm/llvm-project/commit/70646dd3eda3e64fc94b44d7403f946cd7455b92
Author: lianjinfeng2003 <101249452+mygitljf at users.noreply.github.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/AST/StmtPrinter.cpp
M clang/unittests/AST/StmtPrinterTest.cpp
M clang/unittests/AST/TypePrinterTest.cpp
Log Message:
-----------
[clang][AST] Qualify DeclRefExpr printing (#206041)
I updated DeclRefExpr printing so fully-qualified printing consistently
uses declaration ownership rather than only the written qualifier. This
also preserves existing behavior for local names and cleaned parameter
names.
The added tests cover both the direct expression printer behavior and
the original type-printing scenario that exposed the missing
qualification.
Fixes #205925
Commit: 64df722400e57118436776be2b897e70d12e8553
https://github.com/llvm/llvm-project/commit/64df722400e57118436776be2b897e70d12e8553
Author: walkerkd <keith.walker at arm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SchedC1Nano.td
Log Message:
-----------
[AArch64] C1-Nano scheduler cleanup in preparation for SME [NFC] (#207738)
Change are in preparation for a forthcoming addition of SME to the
C1-Nano scheduling model. This is restructuring of the code which does
not involve the actual SME changes. By separating out these NFC changes
it will make review of the SME specific changes easier.
- Defined resource names to match the form now used in the C1-Ultra
scheduling model which has the throughput information on the end of the
name rather than in the middle:
C1NanoWrite_1c_1r_2ALU => C1NanoWrite_1c_2ALU_1rc
- Moved definitions so that they more closely match the order they are
defined in the C1-Nano SWOG. This make it easier to match entries in the
code to the tables in the SWOG.
These changes also make the C1-Nano scheduling model more closely match
the forms and layout used in the C1-Ultra scheduling model.
Commit: ff518705c4c5d1e6e7a94d6ab7819618708d5bcd
https://github.com/llvm/llvm-project/commit/ff518705c4c5d1e6e7a94d6ab7819618708d5bcd
Author: Chandana Mudda <quic_csinderi at quicinc.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonPatterns.td
A llvm/test/CodeGen/Hexagon/sext-mul-splat-v2i16.ll
Log Message:
-----------
[Hexagon] Optimize sext + mul pattern for splatted scalar sext i16 (#206893)
Extend the existing vmpyh pattern to handle the case where one operand
of a v2i32 nsw mul is a splatted scalar sext i16 value. When the splat
is hoisted out of a loop, it arrives as assertsext v2i32, i16 in the DAG
rather than sext v2i16. The existing pattern did not match this form,
causing the multiply to expand to two scalar mpyi instructions.
Add a PatFrag assertsext_v2i32_i16 to match assertsext nodes of type
v2i32 extended from i16, and two new patterns (both operand orderings)
that recover the v2i16 using A2_combine_ll before feeding into
M2_vmpy2s_s0.
Commit: adc3969513100367bd4b2cf6add8935cd308432b
https://github.com/llvm/llvm-project/commit/adc3969513100367bd4b2cf6add8935cd308432b
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
[AMDGPU] Use APFloat::getOne instead of parsing "1.0" (NFC) (#207916)
Commit: 4e43cd6339934945e829ddc4ec3ef81c381a0423
https://github.com/llvm/llvm-project/commit/4e43cd6339934945e829ddc4ec3ef81c381a0423
Author: Mel Chen <mel.chen at sifive.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll
Log Message:
-----------
[LV][RISCV] Enable FSub reduction for scalable VFs (#207698)
#197134 introduced a change to FAdd reduction recognition, causing fsub
instructions to be classified as FSub reductions instead of FAdd
reductions. This patch fixes the regression by enabling FSub reduction
support for scalable VFs in TTI.
Commit: ec9e62cb609a0382c817112e983c461827056dfd
https://github.com/llvm/llvm-project/commit/ec9e62cb609a0382c817112e983c461827056dfd
Author: Artem Kroviakov <71938912+akroviakov at users.noreply.github.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
Log Message:
-----------
[MLIR][XeGPU] Move arch-specific topology under uArch check (#207449)
Commit: 503f0ca19cfcc9c0c88d6918939a2c0038ad0498
https://github.com/llvm/llvm-project/commit/503f0ca19cfcc9c0c88d6918939a2c0038ad0498
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
Log Message:
-----------
[SPIR-V] Simplify and fix sign-extension bug in convertCharsToWord (#207769)
Commit: 81e317971d50396fc68a602a505eb85572c51373
https://github.com/llvm/llvm-project/commit/81e317971d50396fc68a602a505eb85572c51373
Author: DaanishD20 <daanish.dhillip at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/AST/ExprConstant.cpp
M clang/test/SemaCXX/constant-expression-cxx2a.cpp
Log Message:
-----------
[clang] Fix constant-evaluator crash on array new with no size (#207730)
An array new-expression whose bound is neither specified nor deducible
from its initializer (for example `new int[]()`) is ill-formed and is
already diagnosed by Sema with `error: cannot determine allocated array
size from initializer`. However, the constant evaluator still tried to
evaluate the recovery expression. In
`PointerExprEvaluator::VisitCXXNewExpr`
the array size is unavailable (`E->getArraySize()` is `nullopt`), so the
allocation fell through to the scalar-new path, producing an array
`APValue` stored under a scalar type. Reading that object later asserted
in `Type::castAsArrayTypeUnsafe()` (`isa<ArrayType>(CanonicalType)`)
from
`CheckEvaluationResult`.
This patch detects an array new-expression whose size could not be
determined and bails out of constant evaluation.
Fixes #200139
Commit: d6a4a97cb7a198121e5058d6c4c6b4552259a79d
https://github.com/llvm/llvm-project/commit/d6a4a97cb7a198121e5058d6c4c6b4552259a79d
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
Log Message:
-----------
[NFC][SPIRV] Remove dead helper `addStringImm(const StringRef &Str, IRBuilder<> &B, std::vector<Value *> &Args)` (#207923)
The helper was unused.
Commit: ee2f8649c1be2702a79d2249d2e4f7a9befb115b
https://github.com/llvm/llvm-project/commit/ee2f8649c1be2702a79d2249d2e4f7a9befb115b
Author: Luke Lau <luke at igalia.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/early-exit-live-out.ll
A llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses-i64-rv32.ll
A llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-i64-rv32.ll
Log Message:
-----------
[RISCV] Fix interleaved + strided costs for e64 elements on rv32 (#207927)
This is the same fix as #176105 for interleaved + strided memory op
costs.
We currently compute the cost of interleaved + strided ops as N *
scalar element memory ops, but on rv32 the scalar memory access will
be on an illegal type for 64 bit elements, even with zve64x. Prevent
it from overcosting by just using TCC_Basic.
Commit: 62cb33ee38d748e16e95bc6e90fa747ae7f6c49b
https://github.com/llvm/llvm-project/commit/62cb33ee38d748e16e95bc6e90fa747ae7f6c49b
Author: Mel Chen <mel.chen at sifive.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
Log Message:
-----------
[RISCV] Enumerate all RecurKind cases in isLegalToVectorizeReduction. nfc (#207932)
Commit: 5318bd4123261b716c8a0750076495b77e3614dc
https://github.com/llvm/llvm-project/commit/5318bd4123261b716c8a0750076495b77e3614dc
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libc/include/CMakeLists.txt
M libc/include/elf.yaml
M libc/include/llvm-libc-macros/sys-auxv-macros.h
Log Message:
-----------
[libc] Add auxiliary vector and note macros to elf.h (#207914)
Added missing macros to elf.h:
* sys-auxv-macros.h: Added AT_RSEQ_FEATURE_SIZE and AT_RSEQ_ALIGN.
* elf.yaml: Added PT_AARCH64_MEMTAG_MTE, PN_XNUM, ELFCLASSNUM, EV_NUM,
and AT_* macros (via sys-auxv-macros.h). Also added NN_* and NT_* note
macros (including NT_FPREGSET and NT_SIGINFO) to match system headers.
* CMakeLists.txt: Added sys_auxv_macros dependency to elf target.
Assisted-by: Automated tooling, human reviewed.
Commit: 6e0de1cea1c8c567304e5e539ba480cada3e28f5
https://github.com/llvm/llvm-project/commit/6e0de1cea1c8c567304e5e539ba480cada3e28f5
Author: Sergey Semenov <sergey.semenov at intel.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libsycl/docs/index.rst
M libsycl/include/sycl/__impl/async_handler.hpp
M libsycl/include/sycl/__impl/detail/obj_utils.hpp
M libsycl/include/sycl/__impl/queue.hpp
M libsycl/src/detail/offload/offload_topology.cpp
M libsycl/src/detail/platform_impl.cpp
M libsycl/src/detail/queue_impl.cpp
M libsycl/src/detail/queue_impl.hpp
M libsycl/src/queue.cpp
A libsycl/test/usm/memcpy.cpp
M libsycl/unittests/mock/helpers.cpp
M libsycl/unittests/mock/helpers.hpp
M libsycl/unittests/mock/mock.cpp
M libsycl/unittests/queue/CMakeLists.txt
A libsycl/unittests/queue/memcpy.cpp
Log Message:
-----------
[libsycl] Implement memcpy API (#205369)
Commit: fcd02ae7caf28f99357521cafaa6cc7be216ad02
https://github.com/llvm/llvm-project/commit/fcd02ae7caf28f99357521cafaa6cc7be216ad02
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir
Log Message:
-----------
[mlir][SPIRVToLLVM] Add spirv.Unreachable to llvm.unreachable conversion (#207762)
Commit: d8bc45049075791aa291ef0d6298061308506346
https://github.com/llvm/llvm-project/commit/d8bc45049075791aa291ef0d6298061308506346
Author: David Spickett <david.spickett at arm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M lldb/source/Plugins/Process/Utility/LinuxSignals.cpp
Log Message:
-----------
[lldb][Linux] Show si_addr for SIGBUS signals (#207718)
The general rule is if si_addr is the same as the PC, we don't show it
because it doesn't add any new information.
SIGBUS signals are caused by an instruction trying to do something, but
si_addr is not the address of the instruction. It's some virtual
address, which is the important bit so add it to the description.
https://man7.org/linux/man-pages/man7/signal.7.html
> SIGBUS <...> Bus error (bad memory access)
Before:
```
* thread #1, name = 'test.o', stop reason = signal SIGBUS: illegal address
* frame #0: 0x0000aaaaaaaa0b80 test.o`main at test.c:42:13
```
After:
```
* thread #1, name = 'test.o', stop reason = signal SIGBUS: illegal address (fault address=0xfffff7ff6000)
* frame #0: 0x0000aaaaaaaa0b80 test.o`main at test.c:42:13
```
I am not adding test cases for this because:
* They would be architecture specific.
* Reliably generating BUS_OBJERR seems difficult.
* Signal reporting has good coverage as it is, so we know that
si_code/si_addr are handled correctly.
Commit: 3f3276ea30babdca38cbfa1188c3b8302819641f
https://github.com/llvm/llvm-project/commit/3f3276ea30babdca38cbfa1188c3b8302819641f
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.h
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVMetadata.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
Log Message:
-----------
[NFC][SPIRV] Use `StringRef` by value (no `const`, no `&`) (#207940)
A `StringRef` is non-modifiable and it acts as a reference, so there is
no need to declare it as `const` nor `&`.
---------
Co-authored-by: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Commit: 5aa3f7d5ca15ef942e2735555724a65358d0a30d
https://github.com/llvm/llvm-project/commit/5aa3f7d5ca15ef942e2735555724a65358d0a30d
Author: Amit Tiwari <amtiwari at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopDistribute.cpp
M llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp
M llvm/lib/Transforms/Utils/LoopVersioning.cpp
A llvm/test/Transforms/LoopDistribute/non-lcssa-input.ll
A llvm/test/Transforms/LoopLoadElim/non-lcssa-input.ll
Log Message:
-----------
[LLE][LoopDistribution][LoopVersioning] Form LCSSA at Caller Invoking LoopVersioning Utility (#202296)
LoopVersioning utility `versionLoop()` expects the input form to be
LCSSA. However, passes like Loop distribution, Loop-load-elimination,
may invoke versioning with a non-LCSSA IR. Versioning updates exit-block
PHIs to handle both the original loop and the cloned loop. However, a
raw non-LCSSA use in the exit block (such as `switch i1 %C`) still
points to the original loop’s `%C`. On the cloned-loop path, control
reaches the exit block without executing the original `%C`, resulting in
error: `Instruction does not dominate all uses!`.
The fix is to form LCSSA at the caller pass.
Commit: d4cf0c375dadd830c27a2b16e0283c4e31beac1a
https://github.com/llvm/llvm-project/commit/d4cf0c375dadd830c27a2b16e0283c4e31beac1a
Author: David Green <david.green at arm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/GlobalISel/store-merging.mir
M llvm/test/CodeGen/AArch64/GlobalISel/store-wro-addressing-modes.mir
M llvm/test/CodeGen/AArch64/GlobalISel/subreg-copy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/uaddo-8-16-bits.mir
M llvm/test/CodeGen/AArch64/GlobalISel/vararg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir
M llvm/test/CodeGen/AArch64/GlobalISel/xro-addressing-mode-constant.mir
Log Message:
-----------
[AArch64][GlobalISel] Update some tests to use concrete types. NFC (#207960)
Commit: bc5d5f369d127f8b029a81e4fcd874d4b6454347
https://github.com/llvm/llvm-project/commit/bc5d5f369d127f8b029a81e4fcd874d4b6454347
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang-tools-extra/clang-tidy/misc/ThrowByValueCatchByReferenceCheck.cpp
M clang-tools-extra/docs/clang-tidy/checks/bugprone/command-processor.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/float-loop-counter.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/std-namespace-modification.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/throwing-static-initialization.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/unchecked-string-to-number-conversion.rst
M clang-tools-extra/docs/clang-tidy/checks/cert/dcl50-cpp.rst
M clang-tools-extra/docs/clang-tidy/checks/cert/dcl58-cpp.rst
M clang-tools-extra/docs/clang-tidy/checks/cert/env33-c.rst
M clang-tools-extra/docs/clang-tidy/checks/cert/err52-cpp.rst
M clang-tools-extra/docs/clang-tidy/checks/cert/err58-cpp.rst
M clang-tools-extra/docs/clang-tidy/checks/cert/fio38-c.rst
M clang-tools-extra/docs/clang-tidy/checks/cert/flp30-c.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/new-delete-overloads.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/non-copyable-objects.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/avoid-setjmp-longjmp.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/avoid-variadic-functions.rst
M clang-tools-extra/test/clang-tidy/checkers/bugprone/copy-constructor-mutates-argument.cpp
Log Message:
-----------
[clang-tidy][docs] Update CERT links to current SEI URLs. NFC. (#207893)
Commit: ac60c83fc60a86c01eaaafd82bb19bc41649bcfa
https://github.com/llvm/llvm-project/commit/ac60c83fc60a86c01eaaafd82bb19bc41649bcfa
Author: walkerkd <keith.walker at arm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-streaming-cme-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sve-sme-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Inputs/streaming-cme-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/sve-sme-instructions.s
Log Message:
-----------
[AArch64] llvm-mca C1-Ultra tests: SVE instructions added by SME when not streaming [NFC] (#207948)
In the C1-Ultra llvm-mca test, moves some instructions that were
incorrectly in the test file for "Instructions available with no SME but
will be sent to CME when in streaming SVE mode" into a file specifically
for instruction that are "SVE instructions added by SME and available
when not in Streaming SVE mode".
This is in preparation for forthcoming C1-Nano SME support to the
scheduling model that currently has no information about these
instruction due to lack of information in the C1-Nano SWOG.
This change is currently NFC because the C1-Ultra is still running the
the same tests, just from different test files.
Commit: baddc8f7778881120a2a206de817454e13f762bc
https://github.com/llvm/llvm-project/commit/baddc8f7778881120a2a206de817454e13f762bc
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_args.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_cwd.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_debuggerRoot.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_disableSTDIO.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_environment_with_array.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_environment_with_object.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_extra_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_failing_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_failing_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_invalid_launch_commands_and_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_invalid_program.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_no_lldbinit_flag.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_shellExpandArguments_disabled.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_shellExpandArguments_enabled.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_sourcePath.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection_and_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stopOnEntry.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_terminate_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_termination.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_version.py
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
Log Message:
-----------
[lldb-dap] Migrate DAP launch tests (#207023)
Migrate all the tests in `lldb-dap/launch` base directory only. Fixes
any grammar if needed.
Commit: 7b4fd8762aa76e8b256afb51043a1508af2646fe
https://github.com/llvm/llvm-project/commit/7b4fd8762aa76e8b256afb51043a1508af2646fe
Author: Connector Switch <c8ef at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libcxx/docs/Status/Cxx23Issues.csv
Log Message:
-----------
[libc++] Mark LWG3585 as resolved (#207717)
- Close: https://github.com/llvm/llvm-project/issues/104934.
- Commit:
https://github.com/llvm/llvm-project/commit/0d3d8de014f1012dd0b2c2c077099cf6face44e5
- Test:
https://github.com/llvm/llvm-project/blob/52271a5c11f6abde1fa1221db304212b5eb8ec7c/libcxx/test/std/utilities/variant/variant.variant/variant.assign/copy.pass.cpp#L29-L34
Commit: 38a4eef07180d1d9a3216a7ea9d71c50ee4f3c0e
https://github.com/llvm/llvm-project/commit/38a4eef07180d1d9a3216a7ea9d71c50ee4f3c0e
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
Log Message:
-----------
[AMDGPU] Save entry EXEC in whole-wave prologue with no WWM spills (#207924)
PR #207781 replaced the prologue S_XOR_SAVEEXEC (which set EXEC to
~entryEXEC) with a plain S_MOV EXEC, -1, but dropped the save of the
entry EXEC that the return restores from, leaving an undefined register
read
se S_OR_SAVEEXEC to both save entry EXEC and set EXEC to -1
Commit: 4db63ee847f2a9154a9869da51a8c575eb123923
https://github.com/llvm/llvm-project/commit/4db63ee847f2a9154a9869da51a8c575eb123923
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/hdr/CMakeLists.txt
A libc/hdr/inet-address-macros.h
M libc/include/arpa/inet.yaml
M libc/src/__support/net/CMakeLists.txt
M libc/src/__support/net/address.cpp
M libc/src/__support/net/address.h
M libc/src/arpa/inet/CMakeLists.txt
A libc/src/arpa/inet/inet_ntop.cpp
A libc/src/arpa/inet/inet_ntop.h
M libc/test/src/arpa/inet/CMakeLists.txt
A libc/test/src/arpa/inet/inet_ntop_test.cpp
Log Message:
-----------
[libc] Add inet_ntop (#204143)
The function converts from IPv4/6 addresses to their string forms. The
complication comes from the v6 part due to address compression and
v4-mapping.
The traditional implementation of this is to sprintf the address into a
temporary buffer. We cannot do that here due to the ban on calling other
entry points. Using the lower-level constructs is possible, but a
straight forward application of IntegerToString does not result in
particularly impressive performance: 50%-100% slower than what's in this
patch (and slower than glibc). It also doesn't make the code much
smaller as the majority of it is dedicated to v6 compression.
The IPv6 implementation uses a temporary buffer, but it also has a
fast-path which skips the buffer if its size is guaranteed to be
sufficient. The IPv4 implementation also has a fast path, but the
fallback here is to compute the precise length of the string instead
(the buffer option was slower and IPv4 makes it easier to compute the
precise length).
The v6 compression code is unrolled to make it easier to optimize. While
it is possible to write a single printing loop that handles all cases,
its branchiness does not make it amenable for optimization.
The resulting function is faster than its glibc counterpart, though the
exact ratio varies depending on the input:
- random IPv4: 15% faster
- random IPv6: 6% faster
- "::": 50% faster
Commit: de348bcd5f7898dc7478fed6bbd95c97a1848d98
https://github.com/llvm/llvm-project/commit/de348bcd5f7898dc7478fed6bbd95c97a1848d98
Author: Andrei Golubev <andrey.golubev at intel.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/lib/Dialect/Arith/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/MLProgram/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
Log Message:
-----------
[NFC][mlir][bufferization] Align alloc/memcpy/cast options hooks to the rest (#206966)
There are three hooks that have a different, more complicated API than
the other ones: allocationFn, memCpyFn, castFn. All three are called via
"helper" functions that check whether the hooks are set to call them and
fall back to default implementations otherwise.
Other hooks (e.g. unknownTypeConverterFn) in the bufferization options
have a different "API": they are always set to some default
implementation and can be overwritten by the user. This is a simpler API
overall and seems it can be universal.
Note for LLVM integration: BufferizationOptions::{createAlloc,
createMemCpy, createCast} functions are "replaced" with direct calls to
the underlying std::function objects. At any call-site that relied on
any of the removed APIs, a call to the respective hook should now be
used instead. The exception is the `allocationFn` hook which needs an
explicit "bufferAlignment" parameter. Beforehand, it was implicitly
taken from BufferizationOptions::bufferAlignment field, so a
non-functional migration path is to go from
`options.createAlloc(builder, loc, destType, value)` to
`options.allocationFn(builder, loc, destType, value,
options.bufferAlignment)`.
Commit: 8f7019acdd29270a0a51006a6cbdb43d6844dd20
https://github.com/llvm/llvm-project/commit/8f7019acdd29270a0a51006a6cbdb43d6844dd20
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/test/AST/ByteCode/typeid.cpp
Log Message:
-----------
[clang][bytecode] Fix getting typeid pointers of struct fields (#207946)
`getDeclPtr()` will return the declaration pointer, which might be
unrelated to the pointer we actually care about.
Commit: f8defb1033fefe4a62e2f71540e3bea16c20e09f
https://github.com/llvm/llvm-project/commit/f8defb1033fefe4a62e2f71540e3bea16c20e09f
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
Log Message:
-----------
[NFC][SPIRV] Remove dead helper `buildOpMemberDecorate(Register, MachineInstr &, ...)` (#207952)
Another dead helper.
Commit: b4c4fd9ee380b00000ab3fd6e71f9a8c807fb96a
https://github.com/llvm/llvm-project/commit/b4c4fd9ee380b00000ab3fd6e71f9a8c807fb96a
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
Log Message:
-----------
[NFC][SPIRV] Make `getVacantFunctionName` static (#207954)
The function is only used inside `SPIRVUtils.cpp`.
Commit: 12c36c7abb1600638d976258c1c0d3517df59226
https://github.com/llvm/llvm-project/commit/12c36c7abb1600638d976258c1c0d3517df59226
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/hdr/CMakeLists.txt
A libc/hdr/net_if_macros.h
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/struct_ifreq.h
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-macros/CMakeLists.txt
M libc/include/llvm-libc-macros/linux/CMakeLists.txt
A libc/include/llvm-libc-macros/linux/net-if-macros.h
A libc/include/llvm-libc-macros/net-if-macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/struct_ifreq.h
A libc/include/net/if.yaml
M libc/src/CMakeLists.txt
A libc/src/net/CMakeLists.txt
A libc/src/net/if_indextoname.h
A libc/src/net/if_nametoindex.h
A libc/src/net/linux/CMakeLists.txt
A libc/src/net/linux/if_indextoname.cpp
A libc/src/net/linux/if_nametoindex.cpp
M libc/test/src/CMakeLists.txt
A libc/test/src/net/CMakeLists.txt
A libc/test/src/net/linux/CMakeLists.txt
A libc/test/src/net/linux/if_indextoname_test.cpp
A libc/test/src/net/linux/if_nametoindex_test.cpp
Log Message:
-----------
[libc] Implement if_nametoindex and if_indextoname (#206082)
This patch implements if_nametoindex and if_indextoname for Linux.
Both functions work by creating a temporary AF_UNIX socket and issuing
ioctl calls (SIOCGIFINDEX and SIOCGIFNAME, respectively).
The main implementation details:
- for if_nametoindex, I check that the interface name fits within
IF_NAMESIZE before issuing the ioctl
- for if_indextoname, if the kernel returns ENODEV for an unknown index,
I map it to ENXIO to comply with POSIX requirements
- added the definition of struct ifreq to support these operations.
Similar to the other net structure definitions, I'm using an anonymous
union to avoid #defining members.
Assisted by Gemini.
Commit: 149e219bf87f31f0a209037e52b0412d0e8cb5a8
https://github.com/llvm/llvm-project/commit/149e219bf87f31f0a209037e52b0412d0e8cb5a8
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/test/AST/ByteCode/cxx2a.cpp
Log Message:
-----------
[clang][bytecode] Add more checks for pseudo dtors (#207959)
Rename the `EndLifetimePop` op (which was only used for pseudo dtors) to
`PseudoDtor` and call `checkDestructor()` in there, so we get the full
suite of checks.
Commit: 5506a59c7ff2a3a066d1ec6c3fb0ce69754923d4
https://github.com/llvm/llvm-project/commit/5506a59c7ff2a3a066d1ec6c3fb0ce69754923d4
Author: fengfeng <153487255+fengfeng09 at users.noreply.github.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp
M llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
M llvm/test/CodeGen/AMDGPU/barrier-signal-wait-latency.ll
M llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-var-delta.ll
A llvm/test/Transforms/StraightLineStrengthReduce/slsr-gep-sext-wrap.ll
Log Message:
-----------
[SLSR] Fix slsr gep stride delta miscompile (#204278)
Signed-off-by: feng.feng <feng.feng at iluvatar.com>
Commit: 132aa1fcb68f5bedc9e15d47a2d90b06ebf7727b
https://github.com/llvm/llvm-project/commit/132aa1fcb68f5bedc9e15d47a2d90b06ebf7727b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUBarrierLatency.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHWEvents.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCKernelDescriptor.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-av-none.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-global.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-local.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
M llvm/test/CodeGen/AMDGPU/tgsplit.ll
M llvm/test/MC/AMDGPU/hsa-tg-split.s
Log Message:
-----------
AMDGPU: Replace tgsplit subtarget feature with attribute (#204216)
This is a per-entrypoint property and has a corresponding
assembler directive, so it should not be baked into the
subtarget. I couldn't find much documentation on what this
actually does, so the description isn't great.
Fixes #204149
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
Commit: 8c97a2edd20343c7729f76f7b119e024eb6530cc
https://github.com/llvm/llvm-project/commit/8c97a2edd20343c7729f76f7b119e024eb6530cc
Author: Wenju He <wenju.he at intel.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/lib/Serialization/ASTReaderDecl.cpp
A clang/test/PCH/dllexport-ctor-closure-copy.cpp
Log Message:
-----------
[Clang] Fix null-pointer assertion reading CtorClosureDefaultArgs (#207917)
BuildCtorClosureDefaultArgs deliberately leaves the first default-arg
slot null for MS ABI copy-constructor closures (the closure itself
supplies that argument), and ASTWriterDecl.cpp serializes the null. But
e7924d50db0a deserialized it with cast<>, which asserts on null. This
only triggers under the MS C++ ABI, e.g. when throwing a class with a
non-trivial copy constructor by value across a PCH boundary, as in test
https://github.com/intel/llvm/blob/cb9b7b7/clang-tools-extra/clangd/test/sycl.test
Assisted by: Claude
Commit: e16f4895b18d4bac812326416dbb774d5b4162ad
https://github.com/llvm/llvm-project/commit/e16f4895b18d4bac812326416dbb774d5b4162ad
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
A llvm/test/CodeGen/SPIRV/malformed-mangled-builtin-name.ll
Log Message:
-----------
[SPIR-V] Avoid crash on malformed mangled builtin name length (#207939)
Replace the assert on invalid length parsing with a graceful bail-out
since malformed names can potentially come from outside, it is not
necessarily always an error
All usages of `getOclOrSpirvBuiltinDemangledName` are being checked for
emptiness where it is needed anyway
Commit: d8a9bfb0b39d2d331bd6e587016c779552caaffc
https://github.com/llvm/llvm-project/commit/d8a9bfb0b39d2d331bd6e587016c779552caaffc
Author: ayrai-gb <ayrai at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/test/CodeGen/X86/asm-modifier.ll
Log Message:
-----------
[X86] Fix inline asm modifier printing across dialects (#204558)
X86AsmPrinter handles several inline asm operand modifiers differently
depending on whether the asm block uses AT&T or Intel syntax.
For `%a` and `%A`, the scalar/register operand path used AT&T
punctuation unconditionally. In Intel-dialect inline asm this could
print invalid forms such as `(rdi)` for an address operand or `*rdi` for
an indirect call operand.
For `%P`, `PrintAsmMemoryOperand` passed `"disp-only"` to both the Intel
and AT&T memory printers, but only the Intel path honored it for
global/symbol displacements with a base register. The AT&T path could
therefore print `g(%rdi)` even though `%P` requested displacement-only
output.
Make the affected X86 asm-printer paths dialect-aware/consistent:
- print Intel `%a` register operands as `[reg]`
- print Intel `%A` register operands without AT&T `*`
- make AT&T `%P` honor `"disp-only"` for global/symbol displacements,
matching the existing Intel behavior
Found via @jlebar's X86 LLVM bug-hunt / FuzzX effort.
cc @jlebar
Co-authored-by: Ayush Rai <your-email at amd.com>
Commit: 670c3c0adc6487654d0fd857e6666fe5576f5a68
https://github.com/llvm/llvm-project/commit/670c3c0adc6487654d0fd857e6666fe5576f5a68
Author: Lang Hames <lhames at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M orc-rt/CMakeLists.txt
Log Message:
-----------
[orc-rt] Fix indentation in CMakeLists.txt. NFC. (#207980)
Commit: 17d7bf22294173609c3a711a223713780055ed66
https://github.com/llvm/llvm-project/commit/17d7bf22294173609c3a711a223713780055ed66
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
Log Message:
-----------
[clang][bytecode] Try to avoid temporaries in (compound) assignments (#207652)
This is only needed if the RHS has side-effects. If we can easily and
cheaply prove that it doesn't, avoid the temporary variable. This saves
memory and is slightly faster.
Commit: 7cb8692cc1455e983bdd7312d3bcc2f2f5222760
https://github.com/llvm/llvm-project/commit/7cb8692cc1455e983bdd7312d3bcc2f2f5222760
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
A llvm/test/CodeGen/AArch64/sve2-mull-acc.ll
Log Message:
-----------
[AArch64] Select SVE2 multiply-add long from mull and add/sub (#207951)
Both multiple-add long and multiple long are part of SVE2.
Commit: e0093262487e101d3c13773bf313cd3641544cd8
https://github.com/llvm/llvm-project/commit/e0093262487e101d3c13773bf313cd3641544cd8
Author: AZero13 <gfunni234 at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMInstrThumb2.td
M llvm/test/CodeGen/ARM/atomic-ops-v8.ll
A llvm/test/CodeGen/ARM/cmn-shift.ll
M llvm/test/CodeGen/ARM/cmp-peephole.ll
M llvm/test/CodeGen/ARM/umulo-32.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
Log Message:
-----------
[ARM] Swap sides of cmp/cmn based on folding ability (#191915)
If we can fold lsl, lsr, rotr, or asr into the right side of the
compare, we should do so.
Commit: 9588dfe546b81a76a79c571ca0740cab494ff707
https://github.com/llvm/llvm-project/commit/9588dfe546b81a76a79c571ca0740cab494ff707
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/InstCombine/select-abs-positive-mul.ll
Log Message:
-----------
[InstCombine] Recognize abs through positive-K nsw multiply. (#207539)
Generalize matchSelectPattern to also consider multiplies that do not
change sign when trying to from llvm.abs.
End-to-end, this allows vectorizing with narrower element types for code
such as below. This triggers in some ffmpeg kernels on AArch64.
```
void scaled_absdiff_u8(uint8_t * __restrict out,
const uint8_t * __restrict a,
const uint8_t * __restrict b,
size_t n) {
for (size_t i = 0; i < n; ++i) {
int32_t d = 4 * ((int32_t)a[i] - (int32_t)b[i]);
if (d < 0) d = -d;
if (d > 255) d = 255;
out[i] = (uint8_t)d;
}
}
```
Alive2 proof:
* Mul - https://alive2.llvm.org/ce/z/pGYQ36
* Shl - https://alive2.llvm.org/ce/z/WBU2mw
PR: https://github.com/llvm/llvm-project/pull/207539
Commit: 0d9f3f41d6a45e0673c04a01e64d24a76ccffe60
https://github.com/llvm/llvm-project/commit/0d9f3f41d6a45e0673c04a01e64d24a76ccffe60
Author: David Truby <david.truby at arm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M openmp/runtime/cmake/arm64x.cmake
M openmp/runtime/src/CMakeLists.txt
Log Message:
-----------
[openmp][arm64ec] Fix arm64x when PER_TARGET_RUNTIME_DIR=On (#207747)
This patch fixes an issue where the combination of LIBOMP_ENABLE_ARM64X
and LLVM_PER_TARGET_RUNTIME_DIR=On led to only the arm64 library being
installed. With this fix, the arm64ec and arm64 .lib files are both
installed, and the arm64x dll is the one installed to the binary dir.
Commit: 884d9277e89834a9a76a8891de6624c791e5ee08
https://github.com/llvm/llvm-project/commit/884d9277e89834a9a76a8891de6624c791e5ee08
Author: Hans Wennborg <hans at hanshq.net>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/docs/PDB/MsfFile.rst
Log Message:
-----------
[docs][pdb] Fix description of FileMagic (#207972)
There are no spaces around the slash:
https://github.com/microsoft/microsoft-pdb/blob/master/PDB/msf/msf.cpp#L962
Fixes #158492
Commit: d847e2f19b7dfb63c4f73fefcc69cf328b9c18d7
https://github.com/llvm/llvm-project/commit/d847e2f19b7dfb63c4f73fefcc69cf328b9c18d7
Author: Cyrus Ding <91178148+dingcyrus at users.noreply.github.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/include/clang/Basic/IdentifierTable.h
Log Message:
-----------
[Clang] Renumber TokenKey enum values to close gap left by KEYNOZOS removal (#207906)
The previous commit (#207132) removed the unused KEYNOZOS flag
(0x4000000) but left a gap between KEYZOS (0x2000000) and KEYHLSL
(0x8000000). This patch renumbers the subsequent TokenKey values to
close the gap:
KEYHLSL: 0x8000000 -> 0x4000000
KEYFIXEDPOINT: 0x10000000 -> 0x8000000
KEYDEFERTS: 0x20000000 -> 0x10000000
KEYNOHLSL: 0x40000000 -> 0x20000000
The ~0x4000000u exclusion in KEYALL and the associated reserved-bit
comment are removed, since the renumbering eliminates the orphaned bit.
This is a follow-up to #207132, as suggested by @perry-ca.
AI assistance was used for code review analysis and CI failure
debugging.
Co-authored-by: Chenguang Ding <dingchenguang at kylinos.cn>
Commit: 91578461e8a112941afeed18679efb168b81f796
https://github.com/llvm/llvm-project/commit/91578461e8a112941afeed18679efb168b81f796
Author: Mikołaj Piróg <mikolaj.maciej.pirog at intel.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/CodeGen/TargetBuiltins/X86.cpp
A clang/test/CodeGen/builtin-cpu-is-cputype.c
A clang/test/CodeGen/builtin-cpu-is-subtype.c
A clang/test/CodeGen/builtin-cpu-is-vendor.c
R clang/test/CodeGen/builtin-cpu-is.c
A clang/test/CodeGen/builtin-cpu-supports-all.c
M compiler-rt/lib/builtins/cpu_model/x86.c
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/TargetParser/X86TargetParser.h
M llvm/lib/TargetParser/X86TargetParser.cpp
Log Message:
-----------
[X86] Sync compiler-rt cpu subtypes and vendors with libgcc and refactor internal cpu type tables in LLVM (#171172)
This is a continuation of previous PR:
https://github.com/llvm/llvm-project/pull/168750
compiler-rt was synced with libgcc on ProcessorVendor and
ProcessorSubtype fields and so was llvm. Cpu type, subtype and vendor
entries in X86TargetParser.def were refactored to use ABI_VALUE.
LLVM doesn't set the ABI_VALUE for its enums -- clang now takes care of
that by reading the ABI_VALUE.
I've removed and added some comments to better explain what is going on.
While at it, I've added tests to check that right values are passed for
vendor, subtypes, types and features (the last ones weren't added in
feature sync PR: https://github.com/llvm/llvm-project/pull/168750)
Parts of the PR (test) have been realized using Claude Code
Commit: 5343b204252d7bf5bdfcacd664e78e9f7f9fd745
https://github.com/llvm/llvm-project/commit/5343b204252d7bf5bdfcacd664e78e9f7f9fd745
Author: Martin Storsjö <martin at martin.st>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libcxxabi/src/CMakeLists.txt
Log Message:
-----------
[libcxxabi] Don't enable -fvisibility=hidden on Windows (#207943)
This option is supported (and hence gets added by the
target_add_compile_flags_if_supported function) on Windows, but if using
dllexport, there's no point in using hidden visibility. (However if
building both static and shared libraries at the same time, it could be
beneficial to have hidden visibilty in the static libraries.)
In asserts enabled builds of Clang, building with -fvisibility=hidden
caused errors like this:
dllexport GlobalValue must have default or protected visibility
ptr @_ZTIv
[...]
fatal error: error in backend: Broken module found, compilation aborted!
Normally, combining -fvisibility=hidden with dllexport is not a problem,
but specifically for `__cxxabiv1:: __fundamental_type_info` it does make
Clang trigger an inconsistency, visible in asserts enabled builds of
Clang - see https://github.com/llvm/llvm-project/issues/207963.
This fixes Windows builds with Clang with asserts enabled, after
cb942d009a5ed029ce20d9b75b3604f551f0cb56.
Commit: 849d90b64e2a91892d45d2fa75f405fa075d3c3d
https://github.com/llvm/llvm-project/commit/849d90b64e2a91892d45d2fa75f405fa075d3c3d
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaType.cpp
M clang/test/C/C23/n3007.c
M clang/test/Parser/c2x-auto.c
Log Message:
-----------
[C23] Allow deducing restrict and _Atomic qualifiers (#207994)
We were limiting the logic to __auto_type when it should apply to auto
as well.
Fixes #207466
Commit: 980f51a9b264a836b1a145366f17cd1b6d843f7c
https://github.com/llvm/llvm-project/commit/980f51a9b264a836b1a145366f17cd1b6d843f7c
Author: Tomohiro Kashiwada <kikairoya at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonPostRAHandleQFP.cpp
Log Message:
-----------
[Hexagon] Don't use reserved identifiers (#207967)
All identifiers that begin with an underscore followed by a capital
letter or by another underscore are reserved.
Commit: 90dd76bf36f5d8c5ab4dccabee444229e461e7be
https://github.com/llvm/llvm-project/commit/90dd76bf36f5d8c5ab4dccabee444229e461e7be
Author: Barbara Mitic <bmitic at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
A llvm/test/CodeGen/AMDGPU/pack-half-to-lshl-or.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
Log Message:
-----------
[AMDGPU] Select the high-half 16-bit packing idiom to v_lshl_or_b32 (#206058)
The (hi << 16) | z high-half packing idiom is not fused by the existing
(or (shl x, y), z) selection. By the time it reaches ISel the DAG
combiner has rewritten (ext i16) << 16 into bitcast(build_vector (i16
0), hi), so there is no shl node left to match and the build_vector and
or are selected separately.
Add ISel patterns that match the build_vector form directly. On the
non-real-true16 path the high-half source is a VGPR_32, so fold into
v_lshl_or_b32. On the real-true16 path the high-half source is a VGPR_16
and 16-bit ops are native, so OR it into the high half of the other
operand with v_or_b16 and assemble the result with a REG_SEQUENCE.
Co-authored-by: Barbara Mitic <Barbara.Mitic at amd.com>
Commit: 0ac35389e9d47fb9aa2934cbfab274aa69d05317
https://github.com/llvm/llvm-project/commit/0ac35389e9d47fb9aa2934cbfab274aa69d05317
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/AST/ByteCode/cxx2a.cpp
M clang/test/CXX/dcl.decl/dcl.init/dcl.init.general/p16-cxx20.cpp
Log Message:
-----------
[clang][bytecode] Fix `getDynamicDecl()` wrt. multiple base classes (#207722)
The previous code did not consider that the base class we're getting
might not be on the path from `TypePtr` to `TypePtr.stripBaseCasts()` at
all, because of multiple bases.
Commit: 9f4c43747f86f29efa397ad7f172d21dee5ecbe1
https://github.com/llvm/llvm-project/commit/9f4c43747f86f29efa397ad7f172d21dee5ecbe1
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll
Log Message:
-----------
[NFC][AMDGPU] Fix orphaned SDAG/GISEL check prefixes in tests (#207964)
Commit: 5db2a39854f32632fb406b1b25a4b0df4842630e
https://github.com/llvm/llvm-project/commit/5db2a39854f32632fb406b1b25a4b0df4842630e
Author: unexpectedlydefined <91391114+unexpectedlydefined at users.noreply.github.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/docs/CommandGuide/llvm-dwarfdump.rst
M llvm/test/tools/llvm-dwarfdump/X86/coverage.test
M llvm/tools/llvm-dwarfdump/CMakeLists.txt
M llvm/tools/llvm-dwarfdump/Coverage.cpp
M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.h
Log Message:
-----------
Reapply: [llvm-dwarfdump][LineCov 3/3] Add IR analysis for variable coverage (#207974)
Reapplies 5f4940ef. The original patch caused failures on buildbots due to
adding uses of functions defined in LLVMCore and LLVMIRReader without
adding those libraries to the dwarfdump link components.
Patch 3 of 3 to add to llvm-dwarfdump the ability to measure DWARF
coverage of local variables in terms of source lines, as discussed in
this RFC:
https://discourse.llvm.org/t/rfc-debug-info-coverage-tool-v2/83266
This patch adds an IR-level analysis in order to more accurately compute
the defined ranges for each variable. This avoids the problem of the
more naïve approach relying on source scopes, which overcounts as
coverable those lines where the variable is not yet defined (e.g. stack
variables).
The IR analysis requires IR to be provided to llvm-dwarfdump as a
separate `--variable-coverage-bitcode-file` argument (either textual IR
or bitcode; can be produced by various means e.g. `--save-temps
--emit-llvm`, `-ffat-lto-objects`,
[wllvm](https://github.com/travitch/whole-program-llvm)). The
recommended way to obtain a whole-program bitcode file is to use wllvm
as follows:
```sh
$ export LLVM_COMPILER=clang
$ CC=wllvm make # build as usual, but replace clang/clang++ with wllvm/wllvm++
$ extract-bc binfile # produces binfile.bc, which can be passed to llvm-dwarfdump
```
Commit: 17c9f2ea943cb65e1afd02d60c67f7928c9b36c2
https://github.com/llvm/llvm-project/commit/17c9f2ea943cb65e1afd02d60c67f7928c9b36c2
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/semanticly-same.ll
Log Message:
-----------
[SLP][NFC]Add a new test for fadd/fsub combination, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/208004
Commit: d1cd1de72a8f88c3b44c2eacb18146ffd3adee2e
https://github.com/llvm/llvm-project/commit/d1cd1de72a8f88c3b44c2eacb18146ffd3adee2e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
A llvm/test/CodeGen/X86/apx/peephole-fold-subreg-tied-copy.mir
Log Message:
-----------
X86: Fix mishandling subregisters in ndd memory fold (#207997)
Defends against regressions in a future change.
Commit: 3c7727f1269e5986915aacf4ee1ae117843bd573
https://github.com/llvm/llvm-project/commit/3c7727f1269e5986915aacf4ee1ae117843bd573
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libc/src/spawn/linux/CMakeLists.txt
M libc/src/spawn/linux/posix_spawn.cpp
Log Message:
-----------
[libc] Use the dup2 syscall wrapper in posix_spawn (#207879)
posix_spawn's local dup2 helper fell back to a bare dup3 on targets
without SYS_dup2. dup3 fails with EINVAL when oldfd == newfd, where dup2
must instead return oldfd if it is valid, so
posix_spawn_file_actions_adddup2 with equal fds misbehaved on those
targets. linux_syscalls::dup2 already implements the correct fallback,
so call it directly and drop the local helper.
Commit: e16c737a52fa9c5144299282f4da519e898af2a5
https://github.com/llvm/llvm-project/commit/e16c737a52fa9c5144299282f4da519e898af2a5
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
A llvm/test/CodeGen/SPIRV/instructions/phi-aggregate-call.ll
A llvm/test/CodeGen/SPIRV/instructions/phi-aggregate-with-overflow-zeroinitializer.ll
A llvm/test/CodeGen/SPIRV/instructions/phi-aggregate-with-overflow.ll
A llvm/test/CodeGen/SPIRV/instructions/select-freeze-aggregate-with-overflow.ll
Log Message:
-----------
[SPIRV] Expand aggregate instructions with mutated-type uses (#206835)
This is a workaround for the problem in GH issue
https://github.com/llvm/llvm-project/issues/203586.
The problem is that we need to mutate aggregate-typed PHI nodes to
`i32`, however that means all incoming values need to have a matching
type, but we can't always easily mutate the incoming types to i32, as in
the case in the GH issue with a math intrinsic that returns a struct
by-value.
We do the same mutation for some other cases like `freeze`, the
workaround is the same.
The workaround is to expand the incoming values to a form that will also
be mutated to i32 so the types match. An example transformation is
below:
Before
```
...
bb1: ; preds = %entry
%0 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
br label %epilog
...
%2 = phi { i64, i1 } [ %1, %bb0 ], [ %0, %bb1 ]
```
After
```
...
bb1: ; preds = %entry
%0 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
%1 = extractvalue { i64, i1 } %0, 0
%2 = insertvalue { i64, i1 } poison, i64 %1, 0
%3 = extractvalue { i64, i1 } %0, 1
%4 = insertvalue { i64, i1 } %2, i1 %3, 1
br label %epilog
...
%10 = phi { i64, i1 } [ %9, %bb0 ], [ %4, %bb1 ]
```
`insertvalue` get replaced with a SPIR-V intrinsic later in the pass
which is also type-mutated, so the IR is correct:
```
...
bb1: ; preds = %entry
%0 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
call void @llvm.spv.value.md(metadata !0)
call void (...) @llvm.fake.use({ i64, i1 } %0)
%1 = extractvalue { i64, i1 } %0, 0
call void @llvm.spv.assign.type.i64(i64 %1, metadata i64 poison)
call void @llvm.spv.assign.type.i32(i32 undef, metadata { i64, i1 } poison)
%2 = call i32 (i32, i64, ...) @llvm.spv.insertv.i64(i32 undef, i64 %1, i32 0)
call void @llvm.spv.assign.type.i32(i32 %2, metadata { i64, i1 } poison)
%3 = extractvalue { i64, i1 } %0, 1
call void @llvm.spv.assign.type.i1(i1 %3, metadata i1 poison)
%4 = call i32 (i32, i1, ...) @llvm.spv.insertv.i1(i32 %2, i1 %3, i32 1)
call void @llvm.spv.assign.type.i32(i32 %4, metadata { i64, i1 } poison)
br label %epilog
...
%10 = phi i32 [ %9, %bb0 ], [ %4, %bb1 ]
```
This is the simplest change I could come up with, my other ideas were
much more complicated and/or risky.
This fix is important for us because this pattern comes up in libc's
implementation on FMA, so this is blocking SPIR-V libc support.
Fixes: https://github.com/llvm/llvm-project/issues/203586
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: cb668bb3632d06bbcd736ec8999811c8b6b06dd5
https://github.com/llvm/llvm-project/commit/cb668bb3632d06bbcd736ec8999811c8b6b06dd5
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
A llvm/test/CodeGen/SPIRV/capability-Int64Atomics-weak-cmpxchg.ll
Log Message:
-----------
[SPIR-V] Add missing Int64Atomics requirement for OpAtomicCompareExchangeWeak (#207965)
Commit: 250a554f05e54f2bf4f2c2ba736ed2e06429aba2
https://github.com/llvm/llvm-project/commit/250a554f05e54f2bf4f2c2ba736ed2e06429aba2
Author: Matthew Devereau <matthew.devereau at arm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-cmpeq.ll
Log Message:
-----------
[AArch64][InstCombine] Fold xor(cmpeq, pg) to cmpne (#207759)
Extend the existing xor(cmpne(pg, lhs, rhs), pg) fold to also handle
cmpeq to cmpne
Commit: 999b3cfbe21747aa952f79814e7dfd1a7b3fd891
https://github.com/llvm/llvm-project/commit/999b3cfbe21747aa952f79814e7dfd1a7b3fd891
Author: Ankit Kumar Tiwari <141545455+ankit-cybertron at users.noreply.github.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
A llvm/test/CodeGen/RISCV/rvv/vecreduce-add-constant-fold.ll
Log Message:
-----------
[SelectionDAG] Fold VECREDUCE_ADD of a constant BUILD_VECTOR (#207560)
This PR implements constant folding for ISD::VECREDUCE_ADD when the
input is a BUILD_VECTOR of integer constants. The fold computes the sum
at compile time using APInt arithmetic and returns a folded constant
scalar, instead of emitting real vector materialization and reduction
instructions for a value that's already known.
Folding is skipped if any element is undef or opaque, since the result
can't be assumed at compile time in that case.
Fixes #206743
Commit: 047b145c0cfe2ebcf73694f0ab39a0fc11dc9d09
https://github.com/llvm/llvm-project/commit/047b145c0cfe2ebcf73694f0ab39a0fc11dc9d09
Author: hulxv <hulxxv at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libc/shared/builtins.h
A libc/shared/builtins/mulsf3.h
M libc/src/__support/builtins/CMakeLists.txt
A libc/src/__support/builtins/mulsf3.h
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_builtins_test.cpp
Log Message:
-----------
[libc] add shared mulsf3 builtin (#205678)
Re-exposes LLVM-libc's `__mulsf3` as `shared::mulsf3` for reuse by
compiler-rt's builtins.
Stacked change - merge these first:
- #200094
- #205669
- #205670
- #205671
- #205672
- #205673
- #205674
- #205675
- #205676
- #205677
Part of #197824
Commit: 2f7a3a032cb0ff5347135c59914733fc04b20d35
https://github.com/llvm/llvm-project/commit/2f7a3a032cb0ff5347135c59914733fc04b20d35
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/signed_arithmetic_overflow.ll
Log Message:
-----------
[SPIR-V] Fix crash on direct aggregate return of an intrinsic call result (#206491)
Commit: 012523d96b30a9a6d7148825fe307919a9c4753c
https://github.com/llvm/llvm-project/commit/012523d96b30a9a6d7148825fe307919a9c4753c
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
Log Message:
-----------
[VPlan] Support VPInstruction for intrinsic calls in live-in folding. (#207836)
Use getIntrinsicID in getOpcodeOrIntrinsicID. This enables constant
folding for VPInstructions calling intrinsics.
PR: https://github.com/llvm/llvm-project/pull/207836
Commit: 3a6d3f77960b4dded18d15e28eaa3f953be18faa
https://github.com/llvm/llvm-project/commit/3a6d3f77960b4dded18d15e28eaa3f953be18faa
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
Log Message:
-----------
[mlir][LLVM] Add arithmetic fence intrinsic op (#207975)
Add a generated LLVM dialect op for llvm.arithmetic.fence, including
LLVM IR import and export coverage for scalar and vector floating-point
forms.
Assisted-by: Codex
Commit: 43ccdbc84774da0ae4cb5131f2245a9633d977b9
https://github.com/llvm/llvm-project/commit/43ccdbc84774da0ae4cb5131f2245a9633d977b9
Author: Scott Manley <rscottmanley at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/FIRToSCF.cpp
M flang/test/Fir/FirToSCF/do-loop.fir
Log Message:
-----------
[FIRToSCF] propagate acc.par_dims during fir.do_loop conversion (#207973)
Copy any OpenACC parallel dimensions from the fir.do_loop to the scf op
Commit: 35db7fd565138b4756193b36750f052e27359baf
https://github.com/llvm/llvm-project/commit/35db7fd565138b4756193b36750f052e27359baf
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.atomic.cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir
M llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
M llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
M llvm/test/CodeGen/AMDGPU/agpr-csr.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ptr.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/and.ll
M llvm/test/CodeGen/AMDGPU/andorn2.ll
M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_cond.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir
M llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir
M llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir
M llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2_a_v.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fceil64.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.simple.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-memops.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/siloadstoreopt-misaligned-regsequence.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/ssubo.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/structurize-hoist.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
M llvm/test/CodeGen/AMDGPU/swdev380865.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
M llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/valu-i1.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/wqm.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
Log Message:
-----------
[AMDGPU] Stop adding implicit def of superreg in copyPhysReg (#125255)
Previously when copyPhysReg expanded a COPY into multiple MOV
instructions it added an implicit def of the destination superreg to the
first MOV. Removing these does not cause any liveness verification
problems and still passes Vulkan CTS for correctness testing.
Commit: 863be135eb5261fc85007492a5f26de926802a81
https://github.com/llvm/llvm-project/commit/863be135eb5261fc85007492a5f26de926802a81
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libc/src/stdio/printf_core/float_hex_converter.h
Log Message:
-----------
[libc] Fix build failure with ASSUME_ROUND_NEAREST_ONLY (#207991)
Commit 03c62ca40d19ba0 moved some local variables of
`convert_float_hex_exp` into a struct called `properties`, but didn't
edit the #ifdef branch for `LIBC_MATH_HAS_ASSUME_ROUND_NEAREST_ONLY`, so
builds with that definition failed.
Commit: 5ee85101a70dd2628d5b65a6a8a1e5d697d6c757
https://github.com/llvm/llvm-project/commit/5ee85101a70dd2628d5b65a6a8a1e5d697d6c757
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/mul-shl-nsw-intmin.ll
Log Message:
-----------
[SLP][NFC]Add tests with mul to shl transformations, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/208020
Commit: 31fc40b0904861d33b926dfd6ea04432e7690c49
https://github.com/llvm/llvm-project/commit/31fc40b0904861d33b926dfd6ea04432e7690c49
Author: Benjamin Luke <benjamin.luke at sony.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/CodeGen/Targets/X86.cpp
M clang/test/CodeGen/X86/mmx-inline-asm-error.c
A clang/test/CodeGen/target-avx-abi-diag-knr.c
M clang/test/CodeGen/target-builtin-error-3.c
M clang/test/CodeGen/target-features-error-2.c
A clang/test/CodeGenCXX/target-avx-abi-diag.cpp
M libcxx/include/__algorithm/simd_utils.h
Log Message:
-----------
[clang][X86] Emit AVX level mismatch psABI warnings on function definitions (#199091)
Emit -WpsABI for x86_64 function definitions whose return type or
parameter type uses a vector wider than 128 bits without the required
ABI feature enabled. 256-bit vectors require avx, and 512-bit vectors
require avx512f.
Previously this diagnostic was only emitted at call sites, so
definitions with wide vector signatures could be introduced without a
warning until they were called. Use the function feature map so
attribute(target("avx/avx512f")) definitions are accepted, and emit no
warnings for prototype-only declarations.
Commit: e702ecb84930e1d7d8ed1869c713566de2262a63
https://github.com/llvm/llvm-project/commit/e702ecb84930e1d7d8ed1869c713566de2262a63
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
R llvm/test/Transforms/SLPVectorizer/X86/mul-shl-nsw-intmin.ll
Log Message:
-----------
Revert "[SLP][NFC]Add tests with mul to shl transformations, NFC"
This reverts commit 5ee85101a70dd2628d5b65a6a8a1e5d697d6c757, incorrect
checks in the test
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/208022
Commit: e390e6b7a64353c72dbe1ff3f4bd3382412daca5
https://github.com/llvm/llvm-project/commit/e390e6b7a64353c72dbe1ff3f4bd3382412daca5
Author: sohail <sohailraj.satapathy at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libc/docs/headers/stdfix.rst
R libc/src/stdfix/bitusk.cpp
M libc/test/src/stdfix/CMakeLists.txt
A libc/test/src/stdfix/IdivFxTest.h
R libc/test/src/stdfix/IdivTest.h
M libc/test/src/stdfix/idivk_test.cpp
M libc/test/src/stdfix/idivlk_test.cpp
M libc/test/src/stdfix/idivlr_test.cpp
M libc/test/src/stdfix/idivr_test.cpp
M libc/test/src/stdfix/idivuk_test.cpp
M libc/test/src/stdfix/idivulk_test.cpp
M libc/test/src/stdfix/idivulr_test.cpp
M libc/test/src/stdfix/idivur_test.cpp
Log Message:
-----------
[libc][stdfix] Fix idiv* doc table, rename idivfx test helpers and remove duplicate bitsuk source (#206729)
Two small cleanups in libc/src/stdfix.
1. `idiv*` in `stdfix.rst` was marked as implemented for all 12 type
variants but only the 8 non-short width variants (ur, r, ulr, lr, uk, k,
ulk, lk) exist in the directory and are built. Updated the table to
match.
2. Removed `bitusk.cpp` which is an orphaned duplicate of `bitsuk.cpp`
with a typo in the file name. It isn't referenced in the CMakeLists.txt
and has no corresponding .h file.
3. Rename the idivfx test header and helpers.
Commit: c1822d6104d7b2cb2093a5273d6ceccd9ebb2fb1
https://github.com/llvm/llvm-project/commit/c1822d6104d7b2cb2093a5273d6ceccd9ebb2fb1
Author: Yanzuo Liu <zwuis at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/lib/Sema/SemaCXXScopeSpec.cpp
Log Message:
-----------
[clang][Sema][NFC] Improve readability in `computeDeclContext` (#208010)
Split off from #190495.
Co-authored-by: Matheus Izvekov <mizvekov at gmail.com>
Commit: 93ff6992c68766a1def33a8a074f9bce544fc102
https://github.com/llvm/llvm-project/commit/93ff6992c68766a1def33a8a074f9bce544fc102
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/mul-shl-nsw-intmin.ll
Log Message:
-----------
[SLP][NFC]Add tests with mul to shl transformations, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/208027
Commit: cde011852d0b7d08c820f7d623655e5f354a50c8
https://github.com/llvm/llvm-project/commit/cde011852d0b7d08c820f7d623655e5f354a50c8
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/mul-shl-nsw-intmin.ll
Log Message:
-----------
[SLP] Drop nsw when mul by INT_MIN is converted to shl
mul nsw X, INT_MIN is valid, but shl X, BW-1 is not nsw-safe. Drop nsw on
the vector shl when a mul lane with INT_MIN is unified into shl during
opcode interchange.
Fixes #207990
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/208028
Commit: 94a8d4cbf13810e9f4fee03488312dee8869c074
https://github.com/llvm/llvm-project/commit/94a8d4cbf13810e9f4fee03488312dee8869c074
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll
Log Message:
-----------
[AMDGPU] Clear DS aggregate in inverted sched_barrier mask when LDSDMA allowed (#207779)
The DS clause was missing the LDSDMA check that the VMEM clause has
Commit: 6053d19eb3bc2391fcab76eb20a8ea0462568224
https://github.com/llvm/llvm-project/commit/6053d19eb3bc2391fcab76eb20a8ea0462568224
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/PhaseOrdering/X86/avg.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/long-non-power-of-2.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/partial-vec-invalid-cost.ll
M llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-postpone-for-dependency.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-reused-with-bv-subvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/commutable-node-with-non-sched-parent.ll
M llvm/test/Transforms/SLPVectorizer/X86/debug-info-salvage.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-subvectors-insert.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-parent-multi-copyables.ll
M llvm/test/Transforms/SLPVectorizer/X86/recalc-copyable-operand-deps-shared-inst.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-ordered-values-update.ll
Log Message:
-----------
[SLP] Retune look-ahead scores for constants
Rescale LookAheadHeuristics scores and add ScoreSameConstants /
ScoreConstantScaleFactor so identical constants no longer score the
same as same-opcode instruction matches, fixing suboptimal operand
reordering around repeated constants (shift amounts, splat values).
Also retry a SplitVectorize alt-shuffle build for copyable-element
bundles when scheduling fails, instead of always falling back to a
gather, to fix regressions.
Reviewers: hiraditya, bababuck, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/207548
Commit: a00f7be392d9468779af59d86bed12d17aa578c0
https://github.com/llvm/llvm-project/commit/a00f7be392d9468779af59d86bed12d17aa578c0
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
M llvm/test/Transforms/SLPVectorizer/X86/c-ray.ll
M llvm/test/Transforms/SLPVectorizer/X86/delayed-gather-emission.ll
M llvm/test/Transforms/SLPVectorizer/X86/poor-throughput-seeds.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-reorder-reshuffle.ll
Log Message:
-----------
[SLP]Use poor-throughput instructions as vectorization seeds
Seed vectorization from expensive poor-throughput ops (fdiv/frem/fsqrt
and target-expensive calls) even when they do not feed a store or reduction.
Compile time effect https://llvm-compile-time-tracker.com/compare.php?from=8cdf6346f46c505928a9fb9d3ef9e8ce125a2108&to=27a3f0a5c0489c91bf386e480289fdcc9dc9c8b7&stat=instructions:u
These compile time regressions are the side effects of the vectorization
vectorization gains and cannot be reduced further (note Bullet).
Fixes #38780
Reviewers: hiraditya, bababuck, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/206518
Commit: 29f1a71a8d3f12232ccd53bca2442e35396a11a3
https://github.com/llvm/llvm-project/commit/29f1a71a8d3f12232ccd53bca2442e35396a11a3
Author: Aditya Medhane <sherlockedaditya at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M openmp/runtime/src/kmp_dispatch.h
Log Message:
-----------
[OpenMP] Remove internal linkage from __kmp_wait template (NFC) (#207983)
__kmp_wait in kmp_dispatch.h is a static function template in a header,
so any TU that includes it without instantiating it trips
-Wunused-template (kmp_runtime.cpp, kmp_affinity.cpp, kmp_global.cpp,
kmp_settings.cpp). It is used by kmp_dispatch.cpp and
kmp_dispatch_hier.h. Drop static, which the comment above it already
suggests.
Part of #202945
Commit: 72e1037c32e22759b682a0e973af6b95b0630a01
https://github.com/llvm/llvm-project/commit/72e1037c32e22759b682a0e973af6b95b0630a01
Author: AnthonyCalandraGeotab <anthonycalandra at geotab.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libcxx/docs/ReleaseNotes/23.rst
M libcxx/include/__configuration/attributes.h
M libcxx/include/__mutex/lock_guard.h
M libcxx/include/__mutex/mutex.h
M libcxx/include/mutex
M libcxx/include/shared_mutex
A libcxx/test/extensions/clang/thread/thread.mutex/thread_safety_scoped_lock.pass.cpp
A libcxx/test/extensions/clang/thread/thread.mutex/thread_safety_scoped_lock.verify.cpp
Log Message:
-----------
[libc++][ThreadSafety] Add thread safety annotations for variadic std::scoped_lock (#204462)
The thread safety annotations on std::scoped_lock were previously only
applied to the empty and single-mutex specializations. The general
variadic specialization carried no annotations, so -Wthread-safety
considered none of the mutexes held inside a multi-mutex scoped_lock
block and reported the guarded data accessed there as unprotected.
Now that Clang supports pack expansion inside thread safety attributes
(landed for Clang 21), annotate the variadic scoped_lock with
acquire_capability/requires_capability on its constructors,
release_capability on its destructor, and scoped_lockable on the class.
Fixes #42000.
Co-authored-by: Anthony Calandra <anthony at anthony-calandra.com>
Commit: e4e2a9346b60e3805b63cec888f6de022db5b271
https://github.com/llvm/llvm-project/commit/e4e2a9346b60e3805b63cec888f6de022db5b271
Author: Jacob Crawley <jacob.crawley at arm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
A llvm/test/CodeGen/AArch64/sve-interleave-low-vf.ll
M llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence.ll
A llvm/test/Transforms/LoopVectorize/AArch64/sve-interleave-low-vf-cost.ll
A llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-access-low-vf.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
Log Message:
-----------
[AArch64][LV] Cost low-VF interleaved access (#205844)
Adds a case to getInterleavedMemoryOpCost to cost scalable interleaved
memory accesses where the interleave factor is larger than the VF.
Previously for these cases, memory operations would be costed as
individual gathers and scatters, which may result in the LoopVectorizer
choosing a wider VF than necessary.
This changes proposes an alternative approach of using a contiguous
load/store of the interleaved vector followed by shuffles to get
the elements into place.
Commit: 1045d1ebca559d7e6dee49b002142e52bb61b49e
https://github.com/llvm/llvm-project/commit/1045d1ebca559d7e6dee49b002142e52bb61b49e
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libcxx/include/__ranges/zip_view.h
M libcxx/test/libcxx/ranges/range.adaptors/range.zip.transform/nodiscard.verify.cpp
A libcxx/test/libcxx/ranges/range.adaptors/range.zip/nodiscard.verify.cpp
A libcxx/test/libcxx/ranges/range.adaptors/range_adaptor_types.h
Log Message:
-----------
[libc++][ranges] Applied `[[nodiscard]]` to `zip_view` (#207667)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html
- https://wg21.link/range.zip
Towards #172124
Commit: 3046fb3de4b067179bcb8f933942aafea2c0d46f
https://github.com/llvm/llvm-project/commit/3046fb3de4b067179bcb8f933942aafea2c0d46f
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
A offload/test/Inputs/declare-target-common-block-sub.f90
A offload/test/offloading/fortran/declare-target-common-block-2.f90
A offload/test/offloading/fortran/declare-target-common-block-main.f90
Log Message:
-----------
[Flang][OpenMP][Offload] Add Flang offload tests for common block and declare target (#202949)
This PR adds a couple of tests revolving around the usage of common
block with declare target in Fortran OpenMP.
Commit: 3b3f6b56dba47ce53afa6340b27355a94a483e8c
https://github.com/llvm/llvm-project/commit/3b3f6b56dba47ce53afa6340b27355a94a483e8c
Author: Frederik Harwath <frederik.harwath at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
Log Message:
-----------
[AMDGPU] SIFoldOperands: Print instructions/operands in debug output (NFC) (#207945)
Print instructions/operands instead of their addresses in debug output.
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: da9377fad1764dd7f654676aba1fef49205ccc6d
https://github.com/llvm/llvm-project/commit/da9377fad1764dd7f654676aba1fef49205ccc6d
Author: UebelAndre <github at uebelandre.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M utils/bazel/MODULE.bazel
M utils/bazel/MODULE.bazel.lock
Log Message:
-----------
[bazel] Sort bazel_deps into 'compat floor' and 'latest' sections (#207605)
Some dependencies have big knock-on effects and to the benefit of
consumers should best be tracked as min-supported-version. This change
divides the `MODULE.bazel` file into two sections where one contains
known sensitive dependencies that should only be bumped as needed and
the second are flex dependencies that can freely be updated with minimal
impact to external consumers.
Commit: 2bb0c2d1e86c6bd008c3dc23040fb9081289deff
https://github.com/llvm/llvm-project/commit/2bb0c2d1e86c6bd008c3dc23040fb9081289deff
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
Log Message:
-----------
PPC: Use SmallVector for tracking operands instead of DenseMap (#208034)
This is just tracking registers by operand index, which doesn't
need a heavy map.
Commit: 301060211315e9eadb39e17872c2b9d696d72fd6
https://github.com/llvm/llvm-project/commit/301060211315e9eadb39e17872c2b9d696d72fd6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
Log Message:
-----------
PPC: Fix querying TargetInstrInfo from PPCInstrInfo (#208030)
Commit: 3a9778bbf2d78d95bd1d330390187922c6956c78
https://github.com/llvm/llvm-project/commit/3a9778bbf2d78d95bd1d330390187922c6956c78
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M lldb/bindings/python/get-python-config.py
Log Message:
-----------
Revert "[lldb] Change Python site-packages path" (#207910)
Reverts llvm/llvm-project#207771.
`/usr/lib/pythonN.M/site-packages` is a standard path that everyone uses
to install python modules on posix systems. There is no such thing as
`/usr/lib/site-packages`. This change breaks lldb packaging for Linux
distros.
Commit: 17e8068444b58be6935b05200961c984e52989cb
https://github.com/llvm/llvm-project/commit/17e8068444b58be6935b05200961c984e52989cb
Author: Ivo Popov <popov.ivo at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/AST/ASTContext.cpp
A clang/test/Modules/modules-using-enum-class-scope.cppm
Log Message:
-----------
[clang][Modules] Support ODR merging of `UsingEnumDecl` (#207071)
Fixes https://github.com/llvm/llvm-project/issues/207066.
`UsingEnumDecl` (representing C++20 `using enum` declarations)
was not handled in `ASTContext::isSameEntity`.
Consequently, identical class definitions containing
a `using enum` statement failed to merge, resulting in spurious ODR
mismatch errors such as: `error: 'MyStruct::MyEnum' from module
'ModuleB' is not present in definition of 'MyStruct' in module
'ModuleA'`.
This patch implements merging support for `UsingEnumDecl` in
`ASTContext::isSameEntity` by comparing the nested-name-specifier
qualifiers and the underlying `EnumDecl` target.
---------
Co-authored-by: ipopov <ipopov at google.com>
Commit: 87a5682c92f69c87704487670d49db4ca65db21c
https://github.com/llvm/llvm-project/commit/87a5682c92f69c87704487670d49db4ca65db21c
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
Log Message:
-----------
[SLP][NFC]Update test checks, add some more tests, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/208048
Commit: 221cd6295224c93bed2bdfcc113eba5b64325c06
https://github.com/llvm/llvm-project/commit/221cd6295224c93bed2bdfcc113eba5b64325c06
Author: Folkert de Vries <folkert at folkertdev.nl>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp
A llvm/test/CodeGen/WebAssembly/f128-minmax.ll
Log Message:
-----------
[WebAssembly] support `f{min, max}imum.f128` and `f{min, max}imumnum.f128` (#207160)
fixes https://github.com/llvm/llvm-project/issues/207100
As far as I can see `wasi-libc` does not currently export the dedicated
libcalls, so I went with a custom expansion. It emits more code, but
will work without any linker errors etc.
The `long double` type is actually `f128` for webassembly, so at least
the libcalls should work.
Commit: 24688c6a67dc5293c2e75ca9ec991dd0c2a23e59
https://github.com/llvm/llvm-project/commit/24688c6a67dc5293c2e75ca9ec991dd0c2a23e59
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
Log Message:
-----------
PPC: Fix querying TargetRegisterInfo in PPCInstrInfo (#208031)
Use the direct PPCRegisterInfo member
Commit: 9e22a5950e51ace7f50729d7f556ca99d06fa8bb
https://github.com/llvm/llvm-project/commit/9e22a5950e51ace7f50729d7f556ca99d06fa8bb
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
M llvm/lib/Analysis/MemorySSA.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/test/Analysis/MemorySSA/invariant-load-intrinsic.ll
M llvm/test/Transforms/GVN/invariant-load-intrinsic.ll
M llvm/test/Transforms/InstCombine/invariant-load-like-sink.ll
M llvm/test/Transforms/Sink/invariant-load.ll
A llvm/test/Verifier/invariant-load-metadata-invalid.ll
Log Message:
-----------
[llvm] Support invariant.load on readonly intrinsics (#205916)
Update passes and analyses that look at invariant.load (ex. MemorySSA)
to also consider the possibility that `!invariant.load` may be present
on intrinsic calls.
Updates the verifier to indicate that `!invariant.load` is only legal
for loads and readonly intrinsics (and moves the definition of the
metadata out of the definition of `load`).
This has not been extended to arbitrary function calls since it's less
clear what the semantics of !invariant.load on them would be.
Furthermore, extension to read/write intrinsics like memcpy() is planned
as a followup.
This PR also deletes tests that were pre-committed in
https://github.com/llvm/llvm-project/pull/205894 but that become invalid
with the verifier changes in this PR
AI disclosure: I've reviewed the code but all the actual generation was
done by AI.
---------
Co-authored-by: Codex <codex at openai.com>
Commit: dda9dc50945006189f5fabe08a165640c289f0e7
https://github.com/llvm/llvm-project/commit/dda9dc50945006189f5fabe08a165640c289f0e7
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M .github/workflows/libcxx-run-benchmarks.yml
Log Message:
-----------
[libc++] Use a median-of-3 for the A/B comparison benchmarking job (#208023)
After a bit of testing, I think this provides a good tradeoff between
resource utilization and noise reduction. Furthermore, the comparison
script (which produces the output) will be augmented to surface the
variability of the results in a separate PR.
Commit: 0fba09ca6c856f7ec043689c62198166a0b0321e
https://github.com/llvm/llvm-project/commit/0fba09ca6c856f7ec043689c62198166a0b0321e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/ashr-main-opcode-copyables.ll
Log Message:
-----------
[SLP][NFC]Add an extra test with ashr vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/208057
Commit: 100a1fb9d628dc9969ca8f7aef774f61e168f9e9
https://github.com/llvm/llvm-project/commit/100a1fb9d628dc9969ca8f7aef774f61e168f9e9
Author: Chi-Chun, Chen <chichun.chen at hpe.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M flang/include/flang/Semantics/openmp-dsa.h
M flang/lib/Semantics/openmp-dsa.cpp
M flang/lib/Semantics/resolve-directives.cpp
Log Message:
-----------
[flang][OpenMP][NFC] Share SetSymbolDSA between semantics and lowering (#207826)
Move the DSA helper from the private OmpAttributeVisitor::SetSymbolDSA
into the public openmp-dsa header next to GetSymbolDSA, and share the
DSA flag set through a single GetDataSharingAttributeFlags().
This lets an upcoming metadirective lowering change reuse the helper to
set the predetermined DSA of the loop induction variables of a selected
variant. A loop-associated variant is resolved during lowering, so the
usual semantic DSA resolution never runs on its loop nest and lowering
must set those flags itself.
Assisted with Copilot.
Commit: 5da6b3c590792a069c40d8982c8b0fb3557f241a
https://github.com/llvm/llvm-project/commit/5da6b3c590792a069c40d8982c8b0fb3557f241a
Author: Alex Langford <alangford at apple.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M lldb/include/lldb/Target/DynamicRegisterInfo.h
M lldb/source/Target/DynamicRegisterInfo.cpp
Log Message:
-----------
[lldb] DynamicRegisterInfo::Dump should take a Stream argument (#207863)
Otherwise, it creates its own Stream dumping to stdout.
Commit: 679f63b7b4f3d0fb37afcbd24a95bb0d506fd008
https://github.com/llvm/llvm-project/commit/679f63b7b4f3d0fb37afcbd24a95bb0d506fd008
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M .ci/compute_projects.py
M .ci/compute_projects_test.py
R .github/workflows/libclang-python-tests.yml
M .github/workflows/libcxx-run-benchmarks.yml
M clang-tools-extra/clang-doc/CMakeLists.txt
A clang-tools-extra/clang-doc/markdown/CMakeLists.txt
A clang-tools-extra/clang-doc/markdown/Markdown.cpp
A clang-tools-extra/clang-doc/markdown/Markdown.h
M clang-tools-extra/clang-doc/support/CMakeLists.txt
R clang-tools-extra/clang-doc/support/Markdown.cpp
R clang-tools-extra/clang-doc/support/Markdown.h
M clang-tools-extra/clang-tidy/misc/DefinitionsInHeadersCheck.cpp
M clang-tools-extra/clang-tidy/misc/ThrowByValueCatchByReferenceCheck.cpp
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/refactor/tweaks/DefineInline.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/command-processor.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/float-loop-counter.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/std-namespace-modification.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/throwing-static-initialization.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/unchecked-string-to-number-conversion.rst
M clang-tools-extra/docs/clang-tidy/checks/cert/dcl50-cpp.rst
M clang-tools-extra/docs/clang-tidy/checks/cert/dcl58-cpp.rst
M clang-tools-extra/docs/clang-tidy/checks/cert/env33-c.rst
M clang-tools-extra/docs/clang-tidy/checks/cert/err52-cpp.rst
M clang-tools-extra/docs/clang-tidy/checks/cert/err58-cpp.rst
M clang-tools-extra/docs/clang-tidy/checks/cert/fio38-c.rst
M clang-tools-extra/docs/clang-tidy/checks/cert/flp30-c.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/new-delete-overloads.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/non-copyable-objects.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/avoid-bind.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/avoid-setjmp-longjmp.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/avoid-variadic-functions.rst
M clang-tools-extra/test/clang-tidy/checkers/bugprone/copy-constructor-mutates-argument.cpp
M clang-tools-extra/unittests/clang-doc/MarkdownParserTest.cpp
M clang/bindings/python/tests/cindex/test_source_range.py
M clang/bindings/python/tests/cindex/test_translation_unit.py
M clang/docs/LibASTMatchersReference.html
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/JSONNodeDumper.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/ASTMatchers/ASTMatchersInternal.h
M clang/include/clang/Basic/BuiltinsX86_64.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/IdentifierTable.h
M clang/include/clang/Basic/Specifiers.h
M clang/include/clang/Basic/TargetInfo.h
M clang/include/clang/Lex/MultipleIncludeOpt.h
M clang/include/clang/Options/Options.td
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTDumper.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/Comment.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/MicrosoftMangle.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/ASTMatchers/Dynamic/Registry.cpp
M clang/lib/Analysis/ExprMutationAnalyzer.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/ARM.h
M clang/lib/Basic/Targets/DirectX.h
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Basic/Targets/NVPTX.h
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Basic/Targets/SystemZ.h
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprConstant.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGVTables.cpp
M clang/lib/CodeGen/CodeGenTypes.cpp
M clang/lib/CodeGen/README.txt
M clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
M clang/lib/CodeGen/TargetBuiltins/X86.cpp
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/lib/CodeGen/Targets/X86.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/lib/Frontend/InitPreprocessor.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/__clang_gpu_builtin_vars.h
A clang/lib/Headers/__clang_gpu_device_functions.h
A clang/lib/Headers/__clang_gpu_intrinsics.h
R clang/lib/Headers/amxtf32intrin.h
M clang/lib/Headers/avx2intrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Index/IndexingContext.cpp
M clang/lib/InstallAPI/Visitor.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaCXXScopeSpec.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/SemaX86.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/StaticAnalyzer/Checkers/GenericTaintChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/NullabilityChecker.cpp
M clang/lib/StaticAnalyzer/Core/BugSuppression.cpp
M clang/lib/Tooling/Syntax/BuildTree.cpp
M clang/lib/Tooling/Tooling.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/AST/ByteCode/cxx2a.cpp
M clang/test/AST/ByteCode/typeid.cpp
M clang/test/AST/ast-dump-templates-pattern.cpp
M clang/test/Analysis/bstring.c
M clang/test/Analysis/malloc.c
M clang/test/Analysis/pr22954.c
M clang/test/C/C23/n3007.c
A clang/test/CIR/CodeGen/fp16-native-args.c
A clang/test/CIR/CodeGen/fp16.c
M clang/test/CXX/basic/basic.link/p11.cpp
M clang/test/CXX/dcl.decl/dcl.init/dcl.init.general/p16-cxx20.cpp
M clang/test/CXX/drs/cwg18xx.cpp
M clang/test/CXX/drs/cwg7xx.cpp
M clang/test/CXX/temp/temp.arg/temp.arg.template/p3-2a.cpp
M clang/test/CXX/temp/temp.constr/temp.constr.decl/p4.cpp
M clang/test/CXX/temp/temp.decls/temp.spec.partial/temp.spec.partial.member/p2.cpp
M clang/test/CXX/temp/temp.spec/temp.expl.spec/p7.cpp
A clang/test/CodeGen/RISCV/attr-rvv-vector-bits-struct-call.c
R clang/test/CodeGen/X86/amx_tf32.c
R clang/test/CodeGen/X86/amx_tf32_api.c
R clang/test/CodeGen/X86/amx_tf32_errors.c
R clang/test/CodeGen/X86/amx_tf32_inline_asm.c
M clang/test/CodeGen/X86/mmx-inline-asm-error.c
A clang/test/CodeGen/attr-counted-by-nested-structs.c
A clang/test/CodeGen/builtin-cpu-is-cputype.c
A clang/test/CodeGen/builtin-cpu-is-subtype.c
A clang/test/CodeGen/builtin-cpu-is-vendor.c
R clang/test/CodeGen/builtin-cpu-is.c
A clang/test/CodeGen/builtin-cpu-supports-all.c
M clang/test/CodeGen/builtin_float.c
M clang/test/CodeGen/builtin_float_strictfp.c
A clang/test/CodeGen/target-avx-abi-diag-knr.c
M clang/test/CodeGen/target-builtin-error-3.c
M clang/test/CodeGen/target-features-error-2.c
M clang/test/CodeGen/wasm-fp16.c
M clang/test/CodeGen/win64-i128.c
M clang/test/CodeGenCXX/default-arguments.cpp
M clang/test/CodeGenCXX/explicit-instantiation.cpp
M clang/test/CodeGenCXX/mangle-ms-md5.cpp
A clang/test/CodeGenCXX/riscv-rvv-fixed-length-struct-call.cpp
A clang/test/CodeGenCXX/target-avx-abi-diag.cpp
M clang/test/Driver/hexagon-toolchain-picolibc.c
M clang/test/Driver/hip-device-libs-llvm-env.hip
M clang/test/Driver/x86-target-features.c
A clang/test/Headers/gpu-device-functions.cpp
R clang/test/Interpreter/emulated-tls.cpp
A clang/test/Modules/modules-using-enum-class-scope.cppm
M clang/test/OffloadTools/clang-offload-bundler/zstd.c
A clang/test/PCH/dllexport-ctor-closure-copy.cpp
M clang/test/Parser/c2x-auto.c
M clang/test/Preprocessor/predefined-arch-macros.c
M clang/test/Preprocessor/predefined-macros.c
M clang/test/Preprocessor/x86_target_features.c
M clang/test/Sema/builtin-memcpy.c
M clang/test/Sema/builtin-object-size.c
M clang/test/Sema/warn-fortify-source.c
R clang/test/Sema/warn-stringop-overread.c
M clang/test/SemaCXX/GH195416.cpp
M clang/test/SemaCXX/constant-expression-cxx14.cpp
M clang/test/SemaCXX/constant-expression-cxx2a.cpp
M clang/test/SemaCXX/deduced-return-type-cxx14.cpp
M clang/test/SemaCXX/member-class-11.cpp
M clang/test/SemaCXX/warn-memset-bad-sizeof.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/test/SemaTemplate/friend-template.cpp
M clang/test/SemaTemplate/instantiate-scope.cpp
M clang/test/Templight/templight-default-func-arg.cpp
M clang/test/Templight/templight-empty-entries-fix.cpp
M clang/tools/libclang/CIndex.cpp
M clang/unittests/AST/ASTImporterTest.cpp
M clang/unittests/AST/StmtPrinterTest.cpp
M clang/unittests/AST/TypePrinterTest.cpp
M clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
M clang/unittests/Tooling/ToolingTest.cpp
M compiler-rt/lib/builtins/cpu_model/x86.c
M compiler-rt/lib/hwasan/hwasan_tag_mismatch_aarch64.S
M compiler-rt/lib/hwasan/hwasan_tag_mismatch_riscv64.S
M compiler-rt/lib/scudo/standalone/tests/chunk_test.cpp
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/lib/scudo/standalone/tests/flags_test.cpp
M compiler-rt/lib/scudo/standalone/tests/map_test.cpp
M compiler-rt/lib/scudo/standalone/tests/memtag_test.cpp
M compiler-rt/lib/scudo/standalone/tests/report_test.cpp
M compiler-rt/lib/scudo/standalone/tests/scudo_unit_test.h
M compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp
M compiler-rt/lib/scudo/standalone/tests/wrappers_c_test.cpp
M compiler-rt/lib/scudo/standalone/tests/wrappers_cpp_test.cpp
M compiler-rt/test/asan/TestCases/Windows/issue64990.cpp
M flang-rt/lib/runtime/CMakeLists.txt
M flang/docs/Semantics.md
M flang/include/flang/Semantics/openmp-dsa.h
M flang/include/flang/Semantics/semantics.h
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SeparateAllocatableAssign.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFFunctionRewrite.cpp
M flang/lib/Optimizer/Transforms/FIRToMemRef.cpp
M flang/lib/Optimizer/Transforms/FIRToSCF.cpp
M flang/lib/Optimizer/Transforms/LoopInvariantCodeMotion.cpp
M flang/lib/Semantics/openmp-dsa.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Driver/bbc-implicit-use-module.f90
M flang/test/Driver/fsave-optimization-record.f90
M flang/test/Fir/CUDA/cuda-function-rewrite.mlir
M flang/test/Fir/FirToSCF/do-loop.fir
M flang/test/HLFIR/separate-allocatable-assign.fir
M flang/tools/bbc/bbc.cpp
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/dev/printf_behavior.rst
M libc/docs/headers/stdfix.rst
M libc/hdr/CMakeLists.txt
A libc/hdr/dirent_overlay.h
A libc/hdr/inet-address-macros.h
A libc/hdr/net_if_macros.h
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/DIR.h
A libc/hdr/types/struct_dirent.h
A libc/hdr/types/struct_ifreq.h
M libc/include/CMakeLists.txt
M libc/include/arpa/inet.yaml
M libc/include/elf.yaml
M libc/include/llvm-libc-macros/CMakeLists.txt
M libc/include/llvm-libc-macros/linux/CMakeLists.txt
A libc/include/llvm-libc-macros/linux/net-if-macros.h
A libc/include/llvm-libc-macros/net-if-macros.h
M libc/include/llvm-libc-macros/sys-auxv-macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/struct_ifreq.h
A libc/include/net/if.yaml
M libc/shared/builtins.h
A libc/shared/builtins/mulsf3.h
A libc/shared/builtins/subsf3.h
M libc/src/CMakeLists.txt
M libc/src/__support/File/CMakeLists.txt
M libc/src/__support/File/dir.cpp
M libc/src/__support/File/dir.h
M libc/src/__support/File/linux/CMakeLists.txt
M libc/src/__support/File/linux/dir.cpp
M libc/src/__support/OSUtil/linux/stat/kernel_statx_types.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
A libc/src/__support/OSUtil/linux/syscall_wrappers/fcntl.h
M libc/src/__support/builtins/CMakeLists.txt
A libc/src/__support/builtins/mulsf3.h
A libc/src/__support/builtins/subsf3.h
M libc/src/__support/float_to_string.h
M libc/src/__support/net/CMakeLists.txt
M libc/src/__support/net/address.cpp
M libc/src/__support/net/address.h
M libc/src/arpa/inet/CMakeLists.txt
A libc/src/arpa/inet/inet_ntop.cpp
A libc/src/arpa/inet/inet_ntop.h
M libc/src/dirent/CMakeLists.txt
A libc/src/dirent/fdopendir.cpp
A libc/src/dirent/fdopendir.h
A libc/src/net/CMakeLists.txt
A libc/src/net/if_indextoname.h
A libc/src/net/if_nametoindex.h
A libc/src/net/linux/CMakeLists.txt
A libc/src/net/linux/if_indextoname.cpp
A libc/src/net/linux/if_nametoindex.cpp
M libc/src/spawn/linux/CMakeLists.txt
M libc/src/spawn/linux/posix_spawn.cpp
R libc/src/stdfix/bitusk.cpp
M libc/src/stdio/printf_core/converter_utils.h
M libc/src/stdio/printf_core/core_structs.h
M libc/src/stdio/printf_core/float_dec_converter.h
M libc/src/stdio/printf_core/float_dec_converter_limited.h
M libc/src/stdio/printf_core/float_hex_converter.h
M libc/src/stdio/printf_core/float_inf_nan_converter.h
M libc/src/stdio/printf_core/parser.h
M libc/src/stdio/printf_core/printf_config.h
M libc/src/stdio/printf_core/write_int_converter.h
M libc/src/string/memory_utils/arm/inline_memcpy.h
M libc/test/UnitTest/CMakeLists.txt
M libc/test/UnitTest/ErrnoSetterMatcher.h
M libc/test/UnitTest/PrintfMatcher.cpp
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_builtins_test.cpp
M libc/test/src/CMakeLists.txt
M libc/test/src/arpa/inet/CMakeLists.txt
A libc/test/src/arpa/inet/inet_ntop_test.cpp
M libc/test/src/dirent/CMakeLists.txt
A libc/test/src/dirent/fdopendir_test.cpp
A libc/test/src/net/CMakeLists.txt
A libc/test/src/net/linux/CMakeLists.txt
A libc/test/src/net/linux/if_indextoname_test.cpp
A libc/test/src/net/linux/if_nametoindex_test.cpp
M libc/test/src/stdfix/CMakeLists.txt
A libc/test/src/stdfix/IdivFxTest.h
R libc/test/src/stdfix/IdivTest.h
M libc/test/src/stdfix/idivk_test.cpp
M libc/test/src/stdfix/idivlk_test.cpp
M libc/test/src/stdfix/idivlr_test.cpp
M libc/test/src/stdfix/idivr_test.cpp
M libc/test/src/stdfix/idivuk_test.cpp
M libc/test/src/stdfix/idivulk_test.cpp
M libc/test/src/stdfix/idivulr_test.cpp
M libc/test/src/stdfix/idivur_test.cpp
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/sprintf_test.cpp
M libcxx/docs/DesignDocs/FeatureTestMacros.rst
M libcxx/docs/ReleaseNotes/23.rst
M libcxx/docs/Status/Cxx23Issues.csv
M libcxx/include/__algorithm/simd_utils.h
M libcxx/include/__configuration/attributes.h
M libcxx/include/__mutex/lock_guard.h
M libcxx/include/__mutex/mutex.h
M libcxx/include/__ranges/adjacent_transform_view.h
M libcxx/include/__ranges/join_view.h
M libcxx/include/__ranges/zip_transform_view.h
M libcxx/include/__ranges/zip_view.h
M libcxx/include/mutex
M libcxx/include/shared_mutex
A libcxx/test/extensions/clang/thread/thread.mutex/thread_safety_scoped_lock.pass.cpp
A libcxx/test/extensions/clang/thread/thread.mutex/thread_safety_scoped_lock.verify.cpp
A libcxx/test/libcxx/ranges/range.adaptors/range.adjacent.transform/nodiscard.verify.cpp
A libcxx/test/libcxx/ranges/range.adaptors/range.join/nodiscard.verify.cpp
A libcxx/test/libcxx/ranges/range.adaptors/range.zip.transform/nodiscard.verify.cpp
A libcxx/test/libcxx/ranges/range.adaptors/range.zip/nodiscard.verify.cpp
A libcxx/test/libcxx/ranges/range.adaptors/range_adaptor_types.h
M libcxx/test/std/ranges/range.adaptors/range_adaptor_types.h
M libcxx/test/support/test_iterators.h
M libcxxabi/src/CMakeLists.txt
M libsycl/docs/index.rst
M libsycl/include/sycl/__impl/async_handler.hpp
M libsycl/include/sycl/__impl/detail/obj_utils.hpp
M libsycl/include/sycl/__impl/queue.hpp
M libsycl/src/detail/offload/offload_topology.cpp
M libsycl/src/detail/platform_impl.cpp
M libsycl/src/detail/queue_impl.cpp
M libsycl/src/detail/queue_impl.hpp
M libsycl/src/queue.cpp
A libsycl/test/usm/memcpy.cpp
M libsycl/unittests/mock/helpers.cpp
M libsycl/unittests/mock/helpers.hpp
M libsycl/unittests/mock/mock.cpp
M libsycl/unittests/queue/CMakeLists.txt
A libsycl/unittests/queue/memcpy.cpp
M lld/test/ELF/gc-sections-keep-shared-start.s
M lld/test/ELF/lto/stats-file-option.ll
M lldb/include/lldb/Core/EmulateInstruction.h
M lldb/include/lldb/Core/Section.h
M lldb/include/lldb/Core/Value.h
M lldb/include/lldb/Expression/Materializer.h
M lldb/include/lldb/Host/common/NativeRegisterContext.h
M lldb/include/lldb/Symbol/UnwindPlan.h
M lldb/include/lldb/Target/DynamicRegisterInfo.h
M lldb/include/lldb/Target/RegisterContext.h
A lldb/include/lldb/Utility/RegisterInfo.h
M lldb/include/lldb/Utility/RegisterValue.h
M lldb/include/lldb/lldb-private-types.h
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
M lldb/source/API/SBModule.cpp
M lldb/source/API/SBSection.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Core/Section.cpp
M lldb/source/Host/freebsd/Host.cpp
M lldb/source/Plugins/Architecture/CMakeLists.txt
A lldb/source/Plugins/Architecture/RISCV/ArchitectureRISCV.cpp
A lldb/source/Plugins/Architecture/RISCV/ArchitectureRISCV.h
A lldb/source/Plugins/Architecture/RISCV/CMakeLists.txt
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOSXDYLD.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntime.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Platform/Android/PlatformAndroid.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M lldb/source/Plugins/Process/Utility/LinuxSignals.cpp
M lldb/source/Plugins/Process/Utility/RegisterFlagsDetector_arm64.h
M lldb/source/Plugins/Process/Utility/RegisterInfoInterface.h
M lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Target/DynamicRegisterInfo.cpp
M lldb/test/API/functionalities/scripted_frame_provider/circular_dependency/TestFrameProviderCircularDependency.py
M lldb/test/API/tools/lldb-dap/exception/TestDAP_exception.py
M lldb/test/API/tools/lldb-dap/exception/asan/TestDAP_asan.py
M lldb/test/API/tools/lldb-dap/exception/cpp/TestDAP_exception_cpp.py
M lldb/test/API/tools/lldb-dap/exception/cpp/main.cpp
M lldb/test/API/tools/lldb-dap/exception/objc/TestDAP_exception_objc.py
M lldb/test/API/tools/lldb-dap/exception/ubsan/TestDAP_ubsan.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_args.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_cwd.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_debuggerRoot.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_disableSTDIO.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_environment_with_array.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_environment_with_object.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_extra_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_failing_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_failing_launch_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_invalid_launch_commands_and_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_invalid_program.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_no_lldbinit_flag.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_shellExpandArguments_disabled.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_shellExpandArguments_enabled.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_sourcePath.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection_and_console.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stopOnEntry.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_terminate_commands.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_termination.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_version.py
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
A lldb/unittests/Architecture/CMakeLists.txt
A lldb/unittests/Architecture/RISCV/ArchitectureRISCVTest.cpp
A lldb/unittests/Architecture/RISCV/CMakeLists.txt
M lldb/unittests/CMakeLists.txt
M lldb/unittests/Core/ModuleTest.cpp
M lldb/unittests/ObjectFile/ELF/TestObjectFileELF.cpp
M lldb/unittests/Symbol/LineTableTest.cpp
M llvm/docs/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack.md
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CommandGuide/llvm-dwarfdump.rst
M llvm/docs/LangRef.rst
M llvm/docs/PDB/MsfFile.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/Remarks.rst
M llvm/docs/VectorizationPlan.rst
M llvm/docs/conf.py
M llvm/include/llvm/ADT/APInt.h
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFDie.h
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/Object/COFF.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/SandboxIR/PassManager.h
M llvm/include/llvm/Support/KnownFPClass.h
M llvm/include/llvm/Support/LEB128.h
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/TargetParser/X86TargetParser.h
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/lib/Analysis/BlockFrequencyInfoImpl.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
M llvm/lib/Analysis/MemorySSA.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.h
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/DebugInfo/DWARF/DWARFDebugAbbrev.cpp
M llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
M llvm/lib/DebugInfo/DWARF/DWARFDie.cpp
M llvm/lib/DebugInfo/DWARF/DWARFUnit.cpp
M llvm/lib/DebugInfo/GSYM/DwarfTransformer.cpp
M llvm/lib/ExecutionEngine/Orc/Layer.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Object/ArchiveWriter.cpp
M llvm/lib/Object/COFFObjectFile.cpp
M llvm/lib/Support/KnownFPClass.cpp
M llvm/lib/TableGen/StringToOffsetTable.cpp
M llvm/lib/Target/AArch64/AArch64CallingConvention.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SchedC1Nano.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUBarrierLatency.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHWEvents.h
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCKernelDescriptor.cpp
M llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/ARC/ARCISelLowering.cpp
M llvm/lib/Target/ARM/ARMCallingConv.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMInstrNEON.td
M llvm/lib/Target/ARM/ARMInstrThumb2.td
M llvm/lib/Target/AVR/AVRISelLowering.cpp
M llvm/lib/Target/BPF/BPFISelLowering.cpp
M llvm/lib/Target/CSKY/CSKYISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonPatterns.td
M llvm/lib/Target/Hexagon/HexagonPostRAHandleQFP.cpp
M llvm/lib/Target/Lanai/LanaiISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/M68k/M68kISelLowering.cpp
M llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXLowerAlloca.cpp
M llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
M llvm/lib/Target/NVPTX/NVPTXLowerUnreachable.cpp
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/NVPTX/NVVMProperties.cpp
M llvm/lib/Target/NVPTX/NVVMReflect.cpp
M llvm/lib/Target/PowerPC/PPCCallingConv.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.h
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVMetadata.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/VE/VEISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86CallingConv.cpp
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/XCore/XCoreISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
M llvm/lib/Transforms/Instrumentation/NumericalStabilitySanitizer.cpp
M llvm/lib/Transforms/Scalar/LoopDistribute.cpp
M llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp
M llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp
M llvm/lib/Transforms/Utils/LoopVersioning.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Analysis/CostModel/AArch64/arith-overflow.ll
M llvm/test/Analysis/CostModel/AArch64/arith.ll
M llvm/test/Analysis/CostModel/AArch64/div.ll
M llvm/test/Analysis/CostModel/AArch64/mul.ll
M llvm/test/Analysis/CostModel/AArch64/rem.ll
M llvm/test/Analysis/MemorySSA/invariant-load-intrinsic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AArch64/GlobalISel/store-merging.mir
M llvm/test/CodeGen/AArch64/GlobalISel/store-wro-addressing-modes.mir
M llvm/test/CodeGen/AArch64/GlobalISel/subreg-copy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/uaddo-8-16-bits.mir
M llvm/test/CodeGen/AArch64/GlobalISel/vararg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir
M llvm/test/CodeGen/AArch64/GlobalISel/xro-addressing-mode-constant.mir
M llvm/test/CodeGen/AArch64/aarch64-large-stack-spbump.mir
M llvm/test/CodeGen/AArch64/aarch64-vector-pcs.mir
M llvm/test/CodeGen/AArch64/addg_subg.mir
R llvm/test/CodeGen/AArch64/arm64-2013-02-12-shufv8i8.ll
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/bf16-shuffle.ll
M llvm/test/CodeGen/AArch64/build-vector-two-dup.ll
M llvm/test/CodeGen/AArch64/cfi_restore.mir
M llvm/test/CodeGen/AArch64/chkstk.ll
M llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
M llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir
M llvm/test/CodeGen/AArch64/emit-prologue-clobber-verification.mir
M llvm/test/CodeGen/AArch64/extra-callee-save.mir
M llvm/test/CodeGen/AArch64/framelayout-fpr128-spill.mir
M llvm/test/CodeGen/AArch64/framelayout-frame-record.mir
M llvm/test/CodeGen/AArch64/framelayout-offset-immediate-change.mir
M llvm/test/CodeGen/AArch64/framelayout-scavengingslot-stack-hazard.mir
M llvm/test/CodeGen/AArch64/framelayout-scavengingslot.mir
M llvm/test/CodeGen/AArch64/framelayout-split-sve.mir
M llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir
M llvm/test/CodeGen/AArch64/framelayout-sve-calleesaves-fix.mir
M llvm/test/CodeGen/AArch64/framelayout-sve-fixed-width-access.mir
M llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir
M llvm/test/CodeGen/AArch64/framelayout-sve-win.mir
M llvm/test/CodeGen/AArch64/framelayout-sve.mir
M llvm/test/CodeGen/AArch64/implicitly-set-zero-high-64-bits.ll
M llvm/test/CodeGen/AArch64/insert-subvector.ll
M llvm/test/CodeGen/AArch64/insertshuffleload.ll
M llvm/test/CodeGen/AArch64/large-stack-offset-calcs.mir
M llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
M llvm/test/CodeGen/AArch64/lr-reserved-for-ra-live-in.ll
M llvm/test/CodeGen/AArch64/machine-outliner-bti.mir
M llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
M llvm/test/CodeGen/AArch64/machine-outliner-no-noreturn-no-stack.mir
M llvm/test/CodeGen/AArch64/machine-outliner-noreturn-no-stack.mir
M llvm/test/CodeGen/AArch64/machine-outliner-regsave.mir
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir
M llvm/test/CodeGen/AArch64/machine-outliner-size-info.mir
M llvm/test/CodeGen/AArch64/machine-outliner.mir
M llvm/test/CodeGen/AArch64/memtag-stg-loop-reg-pressure.mir
M llvm/test/CodeGen/AArch64/neon-extracttruncate.ll
M llvm/test/CodeGen/AArch64/neon-shuffle-vector-tbl.ll
M llvm/test/CodeGen/AArch64/neon-wide-splat.ll
M llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
M llvm/test/CodeGen/AArch64/nested-iv-regalloc.mir
M llvm/test/CodeGen/AArch64/no-xzr-liveins.mir
M llvm/test/CodeGen/AArch64/pr157252.mir
M llvm/test/CodeGen/AArch64/preserve.ll
M llvm/test/CodeGen/AArch64/prologue-epilogue-remarks.mir
M llvm/test/CodeGen/AArch64/reg-scavenge-frame.mir
M llvm/test/CodeGen/AArch64/regcoal-physreg.mir
M llvm/test/CodeGen/AArch64/reloc-specifiers.mir
M llvm/test/CodeGen/AArch64/settag-merge.mir
M llvm/test/CodeGen/AArch64/shuffle-extend.ll
M llvm/test/CodeGen/AArch64/shuffle-slide-to-shift.ll
M llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
M llvm/test/CodeGen/AArch64/shuffles.ll
M llvm/test/CodeGen/AArch64/spill-stack-realignment.mir
M llvm/test/CodeGen/AArch64/stack-guard-reassign-sve.mir
M llvm/test/CodeGen/AArch64/stack-guard-reassign.mir
M llvm/test/CodeGen/AArch64/stack-guard-width.ll
M llvm/test/CodeGen/AArch64/stack-id-pei-alloc.mir
M llvm/test/CodeGen/AArch64/stack-id-stackslot-scavenging.mir
M llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir
M llvm/test/CodeGen/AArch64/stack-probing-no-scratch-reg.mir
M llvm/test/CodeGen/AArch64/stack-probing-shrink-wrap.mir
M llvm/test/CodeGen/AArch64/stack-tagging-epilogue-fold.mir
M llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir
M llvm/test/CodeGen/AArch64/statepoint-call-lowering-lr.ll
M llvm/test/CodeGen/AArch64/statepoint-call-lowering-sp.ll
M llvm/test/CodeGen/AArch64/sve-calling-convention.ll
A llvm/test/CodeGen/AArch64/sve-interleave-low-vf.ll
M llvm/test/CodeGen/AArch64/sve-ld1r.mir
M llvm/test/CodeGen/AArch64/sve-ldN.mir
M llvm/test/CodeGen/AArch64/sve-ldnf1.mir
M llvm/test/CodeGen/AArch64/sve-ldst-multi-vec.mir
M llvm/test/CodeGen/AArch64/sve-ldstnt1.mir
M llvm/test/CodeGen/AArch64/sve-stN.mir
A llvm/test/CodeGen/AArch64/sve2-mull-acc.ll
M llvm/test/CodeGen/AArch64/unreachable-emergency-spill-slot.mir
M llvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
M llvm/test/CodeGen/AArch64/wineh-frame-predecrement.mir
M llvm/test/CodeGen/AArch64/wineh-frame-scavenge.mir
M llvm/test/CodeGen/AArch64/wineh-frame0.mir
M llvm/test/CodeGen/AArch64/wineh-frame1.mir
M llvm/test/CodeGen/AArch64/wineh-frame2.mir
M llvm/test/CodeGen/AArch64/wineh-frame3.mir
M llvm/test/CodeGen/AArch64/wineh-frame4.mir
M llvm/test/CodeGen/AArch64/wineh-frame5.mir
M llvm/test/CodeGen/AArch64/wineh-frame6.mir
M llvm/test/CodeGen/AArch64/wineh-frame7.mir
M llvm/test/CodeGen/AArch64/wineh-frame8.mir
M llvm/test/CodeGen/AArch64/wineh-save-lrpair1.mir
M llvm/test/CodeGen/AArch64/wineh-save-lrpair2.mir
M llvm/test/CodeGen/AArch64/wineh-save-lrpair3.mir
M llvm/test/CodeGen/AArch64/wineh1.mir
M llvm/test/CodeGen/AArch64/wineh2.mir
M llvm/test/CodeGen/AArch64/wineh3.mir
M llvm/test/CodeGen/AArch64/wineh4.mir
M llvm/test/CodeGen/AArch64/wineh5.mir
M llvm/test/CodeGen/AArch64/wineh6.mir
M llvm/test/CodeGen/AArch64/wineh7.mir
M llvm/test/CodeGen/AArch64/wineh8.mir
M llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir
M llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.offset-split.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.atomic.cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
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M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir
M llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
M llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
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M llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ptr.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
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M llvm/test/CodeGen/AMDGPU/andorn2.ll
M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
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M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
M llvm/test/CodeGen/AMDGPU/barrier-signal-wait-latency.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
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M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_cond.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
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M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir
M llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir
M llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir
M llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir
M llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
M llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
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M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence.ll
M llvm/test/CodeGen/AMDGPU/dead_bundle.mir
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M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
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M llvm/test/CodeGen/AMDGPU/split-liverange-overlapping-copies.mir
M llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
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M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/ssubo.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll
M llvm/test/CodeGen/AMDGPU/structurize-hoist.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
M llvm/test/CodeGen/AMDGPU/swdev380865.ll
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M llvm/test/CodeGen/AMDGPU/track-spilled-vgpr-liveness.mir
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A llvm/test/CodeGen/ARM/cmn-shift.ll
M llvm/test/CodeGen/ARM/cmp-peephole.ll
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M llvm/test/CodeGen/ARM/interrupt-save-fp-attr-status-regs.mir
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M llvm/test/CodeGen/ARM/stack_frame_offset.mir
M llvm/test/CodeGen/ARM/tldrlit_ga_size.mir
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A llvm/test/CodeGen/AVR/cmp-sgt-i128.ll
M llvm/test/CodeGen/BPF/BTF/func-nocall-undef-dead-arg.ll
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M llvm/test/CodeGen/Hexagon/livephysregs-regmask-clobber.mir
A llvm/test/CodeGen/Hexagon/sext-mul-splat-v2i16.ll
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M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpermi.ll
M llvm/test/CodeGen/LoongArch/set-rounding.ll
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M llvm/test/CodeGen/LoongArch/statepoint-call-lowering-r1.ll
M llvm/test/CodeGen/M68k/CollapseMOVEM.mir
M llvm/test/CodeGen/M68k/is-pcrel-register-operand-legal.mir
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M llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir
A llvm/test/CodeGen/MIR/AMDGPU/lr-split-flag.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
M llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
M llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
M llvm/test/CodeGen/MIR/X86/diexpr-win32.mir
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A llvm/test/CodeGen/NVPTX/lower-byval-args-mem-attrs.ll
M llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
M llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
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M llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll
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M llvm/test/CodeGen/PowerPC/byval-agg-info.ll
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M llvm/test/CodeGen/PowerPC/mflr-store.mir
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M llvm/test/CodeGen/PowerPC/prolog_vec_spills.mir
M llvm/test/CodeGen/PowerPC/stack_pointer_vec_spills.mir
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M llvm/test/CodeGen/RISCV/live-sp.mir
M llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
M llvm/test/CodeGen/RISCV/pr176001.ll
M llvm/test/CodeGen/RISCV/pr53662.mir
M llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir
M llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv64.mir
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M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll
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M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
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M llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
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M llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
M llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
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A llvm/test/CodeGen/RISCV/rvv/vecreduce-add-constant-fold.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm.mir
M llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
M llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
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M llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ne.ll
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M llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_uge.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ult.ll
M llvm/test/CodeGen/RISCV/stack-inst-compress.mir
M llvm/test/CodeGen/RISCV/stack-probing-frame-setup.mir
M llvm/test/CodeGen/RISCV/xqccmp-cm-popretz.mir
M llvm/test/CodeGen/RISCV/xqccmp-cm-push-pop.mir
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M llvm/test/CodeGen/RISCV/zilsd-csr-duplicate.mir
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A llvm/test/CodeGen/SPIRV/capability-Int64Atomics-weak-cmpxchg.ll
A llvm/test/CodeGen/SPIRV/instructions/phi-aggregate-call.ll
A llvm/test/CodeGen/SPIRV/instructions/phi-aggregate-with-overflow-zeroinitializer.ll
A llvm/test/CodeGen/SPIRV/instructions/phi-aggregate-with-overflow.ll
A llvm/test/CodeGen/SPIRV/instructions/select-freeze-aggregate-with-overflow.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/signed_arithmetic_overflow.ll
A llvm/test/CodeGen/SPIRV/malformed-mangled-builtin-name.ll
A llvm/test/CodeGen/SPIRV/pointers/array-stride-subbyte.ll
M llvm/test/CodeGen/SystemZ/frame-26.mir
M llvm/test/CodeGen/SystemZ/frame-27.mir
M llvm/test/CodeGen/SystemZ/frame-28.mir
M llvm/test/CodeGen/SystemZ/scavenge-clobbered-reg.mir
M llvm/test/CodeGen/SystemZ/tls-11.mir
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M llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir
M llvm/test/CodeGen/Thumb2/frame-index-addrmode-t2i8s4.mir
M llvm/test/CodeGen/Thumb2/mve-stacksplot.mir
M llvm/test/CodeGen/Thumb2/scavenge-lr.mir
A llvm/test/CodeGen/WebAssembly/f128-minmax.ll
M llvm/test/CodeGen/X86/AMX/amx-greedy-ra-spill-shape.ll
R llvm/test/CodeGen/X86/amx-tf32-internal.ll
R llvm/test/CodeGen/X86/amx-tf32-intrinsics.ll
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A llvm/test/CodeGen/X86/apx/peephole-fold-subreg-tied-copy.mir
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M llvm/test/CodeGen/X86/cfi-epilogue-with-return.mir
M llvm/test/CodeGen/X86/cfi-epilogue-without-return.mir
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M llvm/test/CodeGen/X86/fp128-cast.ll
M llvm/test/CodeGen/X86/haddsub-undef.ll
M llvm/test/CodeGen/X86/ipra-inline-asm.ll
M llvm/test/CodeGen/X86/ipra-reg-usage.ll
M llvm/test/CodeGen/X86/phaddsub-undef.ll
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M llvm/test/CodeGen/X86/prologue-epilogue-remarks.mir
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M llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra.mir
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M llvm/test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll
M llvm/test/CodeGen/X86/win_coreclr_chkstk_liveins.mir
M llvm/test/CodeGen/X86/zero-call-used-regs-debug-info.mir
M llvm/test/DebugInfo/MIR/X86/bit-piece-dh.mir
M llvm/test/DebugInfo/MIR/X86/dvl-livedebugvars-movements.mir
M llvm/test/DebugInfo/MIR/X86/dvl-livedebugvars-stackptr.mir
M llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir
M llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir
M llvm/test/DebugInfo/X86/prolog-params.mir
M llvm/test/MC/AMDGPU/hsa-tg-split.s
R llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-tf32.txt
M llvm/test/MC/RISCV/rv32zclsd-invalid.s
R llvm/test/MC/X86/AMX/x86-64-amx-tf32-att.s
R llvm/test/MC/X86/AMX/x86-64-amx-tf32-intel.s
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M llvm/test/Transforms/GVN/invariant-load-intrinsic.ll
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-cmpeq.ll
M llvm/test/Transforms/InstCombine/add.ll
M llvm/test/Transforms/InstCombine/conditional-variable-length-signext-after-high-bit-extract.ll
A llvm/test/Transforms/InstCombine/frexp-implied-exponent-range-dominating-conditions.ll
M llvm/test/Transforms/InstCombine/invariant-load-like-sink.ll
M llvm/test/Transforms/InstCombine/masked-merge-add.ll
M llvm/test/Transforms/InstCombine/pr53357.ll
A llvm/test/Transforms/InstCombine/select-abs-positive-mul.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-ldexp.ll
A llvm/test/Transforms/InstSimplify/vector-interleave-deinterleave.ll
A llvm/test/Transforms/LoopDistribute/non-lcssa-input.ll
A llvm/test/Transforms/LoopLoadElim/non-lcssa-input.ll
M llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence.ll
A llvm/test/Transforms/LoopVectorize/AArch64/sve-interleave-low-vf-cost.ll
A llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-access-low-vf.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/early-exit-live-out.ll
A llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses-i64-rv32.ll
M llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll
A llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-i64-rv32.ll
M llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
M llvm/test/Transforms/PhaseOrdering/X86/avg.ll
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/long-non-power-of-2.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/partial-vec-invalid-cost.ll
A llvm/test/Transforms/SLPVectorizer/X86/ashr-main-opcode-copyables.ll
M llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-postpone-for-dependency.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-reused-with-bv-subvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/c-ray.ll
M llvm/test/Transforms/SLPVectorizer/X86/commutable-node-with-non-sched-parent.ll
M llvm/test/Transforms/SLPVectorizer/X86/debug-info-salvage.ll
M llvm/test/Transforms/SLPVectorizer/X86/delayed-gather-emission.ll
A llvm/test/Transforms/SLPVectorizer/X86/mul-shl-nsw-intmin.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-subvectors-insert.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-parent-multi-copyables.ll
M llvm/test/Transforms/SLPVectorizer/X86/poor-throughput-seeds.ll
M llvm/test/Transforms/SLPVectorizer/X86/recalc-copyable-operand-deps-shared-inst.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-ordered-values-update.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-reorder-reshuffle.ll
M llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
M llvm/test/Transforms/SLPVectorizer/semanticly-same.ll
M llvm/test/Transforms/Sink/invariant-load.ll
M llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/slsr-var-delta.ll
A llvm/test/Transforms/StraightLineStrengthReduce/slsr-gep-sext-wrap.ll
A llvm/test/Verifier/invariant-load-metadata-invalid.ll
M llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic1.macho.remarks.arm64.opt.yaml
M llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic2.macho.remarks.arm64.opt.yaml
M llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic3.macho.remarks.arm64.opt.yaml
M llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/fat.macho.remarks.x86_64.opt.yaml
M llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/fat.macho.remarks.x86_64h.opt.yaml
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A llvm/test/tools/llvm-ar/arm64x-split.yaml
A llvm/test/tools/llvm-dwarfdump/X86/array-type-lower-bound-dwarf6.s
M llvm/test/tools/llvm-dwarfdump/X86/coverage.test
A llvm/test/tools/llvm-lib/arm64x-hybridobj.yaml
M llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-streaming-cme-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sve-sme-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Inputs/streaming-cme-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/sve-sme-instructions.s
M llvm/test/tools/llvm-remarkutil/Inputs/two-remarks.bitstream
M llvm/test/tools/llvm-remarkutil/Inputs/two-remarks.yaml
M llvm/test/tools/llvm-remarkutil/convert.test
M llvm/test/tools/llvm-remarkutil/size-diff/Inputs/1-func-1-instr-1-stack.yaml
M llvm/test/tools/llvm-remarkutil/size-diff/Inputs/1-func-2-instr-2-stack.yaml
M llvm/test/tools/llvm-remarkutil/size-diff/Inputs/2-identical-func-1-instr-1-stack.yaml
M llvm/test/tools/llvm-remarkutil/size-diff/Inputs/inconvertible-integer.yaml
M llvm/test/tools/llvm-remarkutil/size-diff/Inputs/no-instruction-count-remarks.yaml
M llvm/test/tools/llvm-remarkutil/size-diff/Inputs/unexpected-key.yaml
M llvm/tools/llvm-dwarfdump/CMakeLists.txt
M llvm/tools/llvm-dwarfdump/Coverage.cpp
M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.h
M llvm/tools/llvm-exegesis/lib/Assembler.cpp
M llvm/tools/llvm-remarkutil/RemarkSizeDiff.cpp
M llvm/unittests/ADT/APIntTest.cpp
M llvm/unittests/Analysis/ValueTrackingTest.cpp
M llvm/unittests/DebugInfo/DWARF/DWARFDieTest.cpp
M llvm/unittests/ExecutionEngine/Orc/InProcessEPCTest.cpp
M llvm/unittests/SandboxIR/PassTest.cpp
M llvm/unittests/Support/LEB128Test.cpp
M llvm/utils/TableGen/CallingConvEmitter.cpp
M llvm/utils/UpdateTestChecks/mir.py
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ObjectYAML/BUILD.gn
M mlir/examples/standalone/pyproject.toml
M mlir/include/mlir/Dialect/Async/IR/AsyncOps.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.h
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPUOps.td
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/lib/Dialect/Arith/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/MLProgram/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
M mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
A offload/test/Inputs/declare-target-common-block-sub.f90
A offload/test/offloading/fortran/declare-target-common-block-2.f90
A offload/test/offloading/fortran/declare-target-common-block-main.f90
M openmp/runtime/cmake/arm64x.cmake
M openmp/runtime/src/CMakeLists.txt
M openmp/runtime/src/kmp_dispatch.h
M orc-rt/CMakeLists.txt
M polly/lib/External/isl/isl_union_map.c
M runtimes/cmake/config-Fortran.cmake
M utils/bazel/MODULE.bazel
M utils/bazel/MODULE.bazel.lock
M utils/bazel/llvm-project-overlay/clang-tools-extra/clang-doc/BUILD.bazel
M utils/bazel/llvm-project-overlay/clang-tools-extra/unittests/BUILD.bazel
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/Transforms/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/stdio/BUILD.bazel
M utils/docs/llvm_sphinx/__init__.py
Log Message:
-----------
Rebase
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/b8d89fe2de35...679f63b7b4f3
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