[all-commits] [llvm/llvm-project] 3b5b86: PPC: Fix extsw elimination when the input reads a ...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/ppc/mi-peehole-fix-fix-extsw-elim-subregister
  Home:   https://github.com/llvm/llvm-project
  Commit: 3b5b860adb99ebc513236b37493ff92cf0dc9cfd
      https://github.com/llvm/llvm-project/commit/3b5b860adb99ebc513236b37493ff92cf0dc9cfd
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-07-07 (Tue, 07 Jul 2026)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
    A llvm/test/CodeGen/PowerPC/peephole-elim-extsw-subreg-input.mir

  Log Message:
  -----------
  PPC: Fix extsw elimination when the input reads a subregister

The EXTSW_32_64 sign-extend elimination previously assumed its input
was a full register value. It would then try using that value as the
source of the new (unnecessary) INSERT_SUBREG.

The new test would then hit this verifier error:

```
bb.0:
  liveins: $x3
  %0:g8rc = COPY killed $x3
  %1:g8rc = RLDICL killed %0:g8rc, 0, 33
  %3:g8rc = IMPLICIT_DEF
  %2:g8rc = INSERT_SUBREG %3:g8rc(tied-def 0), %1:g8rc, %subreg.sub_32
  $x3 = COPY killed %2:g8rc
  BLR8 implicit $lr8, implicit $rm, implicit killed $x3

*** Bad machine code: INSERT_SUBREG expected inserted value to have equal or lesser size than the subreg it was inserted into ***
- function:    extsw_elim_subreg_input
- basic block: %bb.0  (0x13c834070)
- instruction: %2:g8rc = INSERT_SUBREG %3:g8rc(tied-def 0), %1:g8rc, %subreg.sub_32
```

This avoids verifier error regressions in a future change.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8, claude-opus-4-8)



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