[all-commits] [llvm/llvm-project] 884d92: [docs][pdb] Fix description of FileMagic (#207972)
David Truby via All-commits
all-commits at lists.llvm.org
Tue Jul 7 08:05:02 PDT 2026
Branch: refs/heads/users/DavidTruby/flang-rt-no-offload
Home: https://github.com/llvm/llvm-project
Commit: 884d9277e89834a9a76a8891de6624c791e5ee08
https://github.com/llvm/llvm-project/commit/884d9277e89834a9a76a8891de6624c791e5ee08
Author: Hans Wennborg <hans at hanshq.net>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/docs/PDB/MsfFile.rst
Log Message:
-----------
[docs][pdb] Fix description of FileMagic (#207972)
There are no spaces around the slash:
https://github.com/microsoft/microsoft-pdb/blob/master/PDB/msf/msf.cpp#L962
Fixes #158492
Commit: d847e2f19b7dfb63c4f73fefcc69cf328b9c18d7
https://github.com/llvm/llvm-project/commit/d847e2f19b7dfb63c4f73fefcc69cf328b9c18d7
Author: Cyrus Ding <91178148+dingcyrus at users.noreply.github.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/include/clang/Basic/IdentifierTable.h
Log Message:
-----------
[Clang] Renumber TokenKey enum values to close gap left by KEYNOZOS removal (#207906)
The previous commit (#207132) removed the unused KEYNOZOS flag
(0x4000000) but left a gap between KEYZOS (0x2000000) and KEYHLSL
(0x8000000). This patch renumbers the subsequent TokenKey values to
close the gap:
KEYHLSL: 0x8000000 -> 0x4000000
KEYFIXEDPOINT: 0x10000000 -> 0x8000000
KEYDEFERTS: 0x20000000 -> 0x10000000
KEYNOHLSL: 0x40000000 -> 0x20000000
The ~0x4000000u exclusion in KEYALL and the associated reserved-bit
comment are removed, since the renumbering eliminates the orphaned bit.
This is a follow-up to #207132, as suggested by @perry-ca.
AI assistance was used for code review analysis and CI failure
debugging.
Co-authored-by: Chenguang Ding <dingchenguang at kylinos.cn>
Commit: 91578461e8a112941afeed18679efb168b81f796
https://github.com/llvm/llvm-project/commit/91578461e8a112941afeed18679efb168b81f796
Author: Mikołaj Piróg <mikolaj.maciej.pirog at intel.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/CodeGen/TargetBuiltins/X86.cpp
A clang/test/CodeGen/builtin-cpu-is-cputype.c
A clang/test/CodeGen/builtin-cpu-is-subtype.c
A clang/test/CodeGen/builtin-cpu-is-vendor.c
R clang/test/CodeGen/builtin-cpu-is.c
A clang/test/CodeGen/builtin-cpu-supports-all.c
M compiler-rt/lib/builtins/cpu_model/x86.c
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/TargetParser/X86TargetParser.h
M llvm/lib/TargetParser/X86TargetParser.cpp
Log Message:
-----------
[X86] Sync compiler-rt cpu subtypes and vendors with libgcc and refactor internal cpu type tables in LLVM (#171172)
This is a continuation of previous PR:
https://github.com/llvm/llvm-project/pull/168750
compiler-rt was synced with libgcc on ProcessorVendor and
ProcessorSubtype fields and so was llvm. Cpu type, subtype and vendor
entries in X86TargetParser.def were refactored to use ABI_VALUE.
LLVM doesn't set the ABI_VALUE for its enums -- clang now takes care of
that by reading the ABI_VALUE.
I've removed and added some comments to better explain what is going on.
While at it, I've added tests to check that right values are passed for
vendor, subtypes, types and features (the last ones weren't added in
feature sync PR: https://github.com/llvm/llvm-project/pull/168750)
Parts of the PR (test) have been realized using Claude Code
Commit: 5343b204252d7bf5bdfcacd664e78e9f7f9fd745
https://github.com/llvm/llvm-project/commit/5343b204252d7bf5bdfcacd664e78e9f7f9fd745
Author: Martin Storsjö <martin at martin.st>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libcxxabi/src/CMakeLists.txt
Log Message:
-----------
[libcxxabi] Don't enable -fvisibility=hidden on Windows (#207943)
This option is supported (and hence gets added by the
target_add_compile_flags_if_supported function) on Windows, but if using
dllexport, there's no point in using hidden visibility. (However if
building both static and shared libraries at the same time, it could be
beneficial to have hidden visibilty in the static libraries.)
In asserts enabled builds of Clang, building with -fvisibility=hidden
caused errors like this:
dllexport GlobalValue must have default or protected visibility
ptr @_ZTIv
[...]
fatal error: error in backend: Broken module found, compilation aborted!
Normally, combining -fvisibility=hidden with dllexport is not a problem,
but specifically for `__cxxabiv1:: __fundamental_type_info` it does make
Clang trigger an inconsistency, visible in asserts enabled builds of
Clang - see https://github.com/llvm/llvm-project/issues/207963.
This fixes Windows builds with Clang with asserts enabled, after
cb942d009a5ed029ce20d9b75b3604f551f0cb56.
Commit: 849d90b64e2a91892d45d2fa75f405fa075d3c3d
https://github.com/llvm/llvm-project/commit/849d90b64e2a91892d45d2fa75f405fa075d3c3d
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaType.cpp
M clang/test/C/C23/n3007.c
M clang/test/Parser/c2x-auto.c
Log Message:
-----------
[C23] Allow deducing restrict and _Atomic qualifiers (#207994)
We were limiting the logic to __auto_type when it should apply to auto
as well.
Fixes #207466
Commit: 980f51a9b264a836b1a145366f17cd1b6d843f7c
https://github.com/llvm/llvm-project/commit/980f51a9b264a836b1a145366f17cd1b6d843f7c
Author: Tomohiro Kashiwada <kikairoya at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonPostRAHandleQFP.cpp
Log Message:
-----------
[Hexagon] Don't use reserved identifiers (#207967)
All identifiers that begin with an underscore followed by a capital
letter or by another underscore are reserved.
Commit: 90dd76bf36f5d8c5ab4dccabee444229e461e7be
https://github.com/llvm/llvm-project/commit/90dd76bf36f5d8c5ab4dccabee444229e461e7be
Author: Barbara Mitic <bmitic at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
A llvm/test/CodeGen/AMDGPU/pack-half-to-lshl-or.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
Log Message:
-----------
[AMDGPU] Select the high-half 16-bit packing idiom to v_lshl_or_b32 (#206058)
The (hi << 16) | z high-half packing idiom is not fused by the existing
(or (shl x, y), z) selection. By the time it reaches ISel the DAG
combiner has rewritten (ext i16) << 16 into bitcast(build_vector (i16
0), hi), so there is no shl node left to match and the build_vector and
or are selected separately.
Add ISel patterns that match the build_vector form directly. On the
non-real-true16 path the high-half source is a VGPR_32, so fold into
v_lshl_or_b32. On the real-true16 path the high-half source is a VGPR_16
and 16-bit ops are native, so OR it into the high half of the other
operand with v_or_b16 and assemble the result with a REG_SEQUENCE.
Co-authored-by: Barbara Mitic <Barbara.Mitic at amd.com>
Commit: 0ac35389e9d47fb9aa2934cbfab274aa69d05317
https://github.com/llvm/llvm-project/commit/0ac35389e9d47fb9aa2934cbfab274aa69d05317
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/AST/ByteCode/cxx2a.cpp
M clang/test/CXX/dcl.decl/dcl.init/dcl.init.general/p16-cxx20.cpp
Log Message:
-----------
[clang][bytecode] Fix `getDynamicDecl()` wrt. multiple base classes (#207722)
The previous code did not consider that the base class we're getting
might not be on the path from `TypePtr` to `TypePtr.stripBaseCasts()` at
all, because of multiple bases.
Commit: 9f4c43747f86f29efa397ad7f172d21dee5ecbe1
https://github.com/llvm/llvm-project/commit/9f4c43747f86f29efa397ad7f172d21dee5ecbe1
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll
Log Message:
-----------
[NFC][AMDGPU] Fix orphaned SDAG/GISEL check prefixes in tests (#207964)
Commit: 5db2a39854f32632fb406b1b25a4b0df4842630e
https://github.com/llvm/llvm-project/commit/5db2a39854f32632fb406b1b25a4b0df4842630e
Author: unexpectedlydefined <91391114+unexpectedlydefined at users.noreply.github.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/docs/CommandGuide/llvm-dwarfdump.rst
M llvm/test/tools/llvm-dwarfdump/X86/coverage.test
M llvm/tools/llvm-dwarfdump/CMakeLists.txt
M llvm/tools/llvm-dwarfdump/Coverage.cpp
M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.h
Log Message:
-----------
Reapply: [llvm-dwarfdump][LineCov 3/3] Add IR analysis for variable coverage (#207974)
Reapplies 5f4940ef. The original patch caused failures on buildbots due to
adding uses of functions defined in LLVMCore and LLVMIRReader without
adding those libraries to the dwarfdump link components.
Patch 3 of 3 to add to llvm-dwarfdump the ability to measure DWARF
coverage of local variables in terms of source lines, as discussed in
this RFC:
https://discourse.llvm.org/t/rfc-debug-info-coverage-tool-v2/83266
This patch adds an IR-level analysis in order to more accurately compute
the defined ranges for each variable. This avoids the problem of the
more naïve approach relying on source scopes, which overcounts as
coverable those lines where the variable is not yet defined (e.g. stack
variables).
The IR analysis requires IR to be provided to llvm-dwarfdump as a
separate `--variable-coverage-bitcode-file` argument (either textual IR
or bitcode; can be produced by various means e.g. `--save-temps
--emit-llvm`, `-ffat-lto-objects`,
[wllvm](https://github.com/travitch/whole-program-llvm)). The
recommended way to obtain a whole-program bitcode file is to use wllvm
as follows:
```sh
$ export LLVM_COMPILER=clang
$ CC=wllvm make # build as usual, but replace clang/clang++ with wllvm/wllvm++
$ extract-bc binfile # produces binfile.bc, which can be passed to llvm-dwarfdump
```
Commit: 17c9f2ea943cb65e1afd02d60c67f7928c9b36c2
https://github.com/llvm/llvm-project/commit/17c9f2ea943cb65e1afd02d60c67f7928c9b36c2
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/semanticly-same.ll
Log Message:
-----------
[SLP][NFC]Add a new test for fadd/fsub combination, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/208004
Commit: d1cd1de72a8f88c3b44c2eacb18146ffd3adee2e
https://github.com/llvm/llvm-project/commit/d1cd1de72a8f88c3b44c2eacb18146ffd3adee2e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
A llvm/test/CodeGen/X86/apx/peephole-fold-subreg-tied-copy.mir
Log Message:
-----------
X86: Fix mishandling subregisters in ndd memory fold (#207997)
Defends against regressions in a future change.
Commit: 3c7727f1269e5986915aacf4ee1ae117843bd573
https://github.com/llvm/llvm-project/commit/3c7727f1269e5986915aacf4ee1ae117843bd573
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libc/src/spawn/linux/CMakeLists.txt
M libc/src/spawn/linux/posix_spawn.cpp
Log Message:
-----------
[libc] Use the dup2 syscall wrapper in posix_spawn (#207879)
posix_spawn's local dup2 helper fell back to a bare dup3 on targets
without SYS_dup2. dup3 fails with EINVAL when oldfd == newfd, where dup2
must instead return oldfd if it is valid, so
posix_spawn_file_actions_adddup2 with equal fds misbehaved on those
targets. linux_syscalls::dup2 already implements the correct fallback,
so call it directly and drop the local helper.
Commit: e16c737a52fa9c5144299282f4da519e898af2a5
https://github.com/llvm/llvm-project/commit/e16c737a52fa9c5144299282f4da519e898af2a5
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
A llvm/test/CodeGen/SPIRV/instructions/phi-aggregate-call.ll
A llvm/test/CodeGen/SPIRV/instructions/phi-aggregate-with-overflow-zeroinitializer.ll
A llvm/test/CodeGen/SPIRV/instructions/phi-aggregate-with-overflow.ll
A llvm/test/CodeGen/SPIRV/instructions/select-freeze-aggregate-with-overflow.ll
Log Message:
-----------
[SPIRV] Expand aggregate instructions with mutated-type uses (#206835)
This is a workaround for the problem in GH issue
https://github.com/llvm/llvm-project/issues/203586.
The problem is that we need to mutate aggregate-typed PHI nodes to
`i32`, however that means all incoming values need to have a matching
type, but we can't always easily mutate the incoming types to i32, as in
the case in the GH issue with a math intrinsic that returns a struct
by-value.
We do the same mutation for some other cases like `freeze`, the
workaround is the same.
The workaround is to expand the incoming values to a form that will also
be mutated to i32 so the types match. An example transformation is
below:
Before
```
...
bb1: ; preds = %entry
%0 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
br label %epilog
...
%2 = phi { i64, i1 } [ %1, %bb0 ], [ %0, %bb1 ]
```
After
```
...
bb1: ; preds = %entry
%0 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
%1 = extractvalue { i64, i1 } %0, 0
%2 = insertvalue { i64, i1 } poison, i64 %1, 0
%3 = extractvalue { i64, i1 } %0, 1
%4 = insertvalue { i64, i1 } %2, i1 %3, 1
br label %epilog
...
%10 = phi { i64, i1 } [ %9, %bb0 ], [ %4, %bb1 ]
```
`insertvalue` get replaced with a SPIR-V intrinsic later in the pass
which is also type-mutated, so the IR is correct:
```
...
bb1: ; preds = %entry
%0 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
call void @llvm.spv.value.md(metadata !0)
call void (...) @llvm.fake.use({ i64, i1 } %0)
%1 = extractvalue { i64, i1 } %0, 0
call void @llvm.spv.assign.type.i64(i64 %1, metadata i64 poison)
call void @llvm.spv.assign.type.i32(i32 undef, metadata { i64, i1 } poison)
%2 = call i32 (i32, i64, ...) @llvm.spv.insertv.i64(i32 undef, i64 %1, i32 0)
call void @llvm.spv.assign.type.i32(i32 %2, metadata { i64, i1 } poison)
%3 = extractvalue { i64, i1 } %0, 1
call void @llvm.spv.assign.type.i1(i1 %3, metadata i1 poison)
%4 = call i32 (i32, i1, ...) @llvm.spv.insertv.i1(i32 %2, i1 %3, i32 1)
call void @llvm.spv.assign.type.i32(i32 %4, metadata { i64, i1 } poison)
br label %epilog
...
%10 = phi i32 [ %9, %bb0 ], [ %4, %bb1 ]
```
This is the simplest change I could come up with, my other ideas were
much more complicated and/or risky.
This fix is important for us because this pattern comes up in libc's
implementation on FMA, so this is blocking SPIR-V libc support.
Fixes: https://github.com/llvm/llvm-project/issues/203586
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: cb668bb3632d06bbcd736ec8999811c8b6b06dd5
https://github.com/llvm/llvm-project/commit/cb668bb3632d06bbcd736ec8999811c8b6b06dd5
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
A llvm/test/CodeGen/SPIRV/capability-Int64Atomics-weak-cmpxchg.ll
Log Message:
-----------
[SPIR-V] Add missing Int64Atomics requirement for OpAtomicCompareExchangeWeak (#207965)
Commit: 250a554f05e54f2bf4f2c2ba736ed2e06429aba2
https://github.com/llvm/llvm-project/commit/250a554f05e54f2bf4f2c2ba736ed2e06429aba2
Author: Matthew Devereau <matthew.devereau at arm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-cmpeq.ll
Log Message:
-----------
[AArch64][InstCombine] Fold xor(cmpeq, pg) to cmpne (#207759)
Extend the existing xor(cmpne(pg, lhs, rhs), pg) fold to also handle
cmpeq to cmpne
Commit: 999b3cfbe21747aa952f79814e7dfd1a7b3fd891
https://github.com/llvm/llvm-project/commit/999b3cfbe21747aa952f79814e7dfd1a7b3fd891
Author: Ankit Kumar Tiwari <141545455+ankit-cybertron at users.noreply.github.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
A llvm/test/CodeGen/RISCV/rvv/vecreduce-add-constant-fold.ll
Log Message:
-----------
[SelectionDAG] Fold VECREDUCE_ADD of a constant BUILD_VECTOR (#207560)
This PR implements constant folding for ISD::VECREDUCE_ADD when the
input is a BUILD_VECTOR of integer constants. The fold computes the sum
at compile time using APInt arithmetic and returns a folded constant
scalar, instead of emitting real vector materialization and reduction
instructions for a value that's already known.
Folding is skipped if any element is undef or opaque, since the result
can't be assumed at compile time in that case.
Fixes #206743
Commit: 047b145c0cfe2ebcf73694f0ab39a0fc11dc9d09
https://github.com/llvm/llvm-project/commit/047b145c0cfe2ebcf73694f0ab39a0fc11dc9d09
Author: hulxv <hulxxv at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M libc/shared/builtins.h
A libc/shared/builtins/mulsf3.h
M libc/src/__support/builtins/CMakeLists.txt
A libc/src/__support/builtins/mulsf3.h
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_builtins_test.cpp
Log Message:
-----------
[libc] add shared mulsf3 builtin (#205678)
Re-exposes LLVM-libc's `__mulsf3` as `shared::mulsf3` for reuse by
compiler-rt's builtins.
Stacked change - merge these first:
- #200094
- #205669
- #205670
- #205671
- #205672
- #205673
- #205674
- #205675
- #205676
- #205677
Part of #197824
Commit: 2f7a3a032cb0ff5347135c59914733fc04b20d35
https://github.com/llvm/llvm-project/commit/2f7a3a032cb0ff5347135c59914733fc04b20d35
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/signed_arithmetic_overflow.ll
Log Message:
-----------
[SPIR-V] Fix crash on direct aggregate return of an intrinsic call result (#206491)
Commit: 012523d96b30a9a6d7148825fe307919a9c4753c
https://github.com/llvm/llvm-project/commit/012523d96b30a9a6d7148825fe307919a9c4753c
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
Log Message:
-----------
[VPlan] Support VPInstruction for intrinsic calls in live-in folding. (#207836)
Use getIntrinsicID in getOpcodeOrIntrinsicID. This enables constant
folding for VPInstructions calling intrinsics.
PR: https://github.com/llvm/llvm-project/pull/207836
Commit: 3a6d3f77960b4dded18d15e28eaa3f953be18faa
https://github.com/llvm/llvm-project/commit/3a6d3f77960b4dded18d15e28eaa3f953be18faa
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
Log Message:
-----------
[mlir][LLVM] Add arithmetic fence intrinsic op (#207975)
Add a generated LLVM dialect op for llvm.arithmetic.fence, including
LLVM IR import and export coverage for scalar and vector floating-point
forms.
Assisted-by: Codex
Commit: 43ccdbc84774da0ae4cb5131f2245a9633d977b9
https://github.com/llvm/llvm-project/commit/43ccdbc84774da0ae4cb5131f2245a9633d977b9
Author: Scott Manley <rscottmanley at gmail.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/FIRToSCF.cpp
M flang/test/Fir/FirToSCF/do-loop.fir
Log Message:
-----------
[FIRToSCF] propagate acc.par_dims during fir.do_loop conversion (#207973)
Copy any OpenACC parallel dimensions from the fir.do_loop to the scf op
Commit: 35db7fd565138b4756193b36750f052e27359baf
https://github.com/llvm/llvm-project/commit/35db7fd565138b4756193b36750f052e27359baf
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.atomic.cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir
M llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
M llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
M llvm/test/CodeGen/AMDGPU/agpr-csr.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ptr.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/and.ll
M llvm/test/CodeGen/AMDGPU/andorn2.ll
M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_cond.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir
M llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir
M llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir
M llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2_a_v.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fceil64.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.simple.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-memops.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/siloadstoreopt-misaligned-regsequence.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/ssubo.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/structurize-hoist.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
M llvm/test/CodeGen/AMDGPU/swdev380865.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
M llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/valu-i1.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/wqm.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
Log Message:
-----------
[AMDGPU] Stop adding implicit def of superreg in copyPhysReg (#125255)
Previously when copyPhysReg expanded a COPY into multiple MOV
instructions it added an implicit def of the destination superreg to the
first MOV. Removing these does not cause any liveness verification
problems and still passes Vulkan CTS for correctness testing.
Commit: 8d5b800f1b59d07781dd3cbd84a242b71ff12274
https://github.com/llvm/llvm-project/commit/8d5b800f1b59d07781dd3cbd84a242b71ff12274
Author: David Truby <david.truby at arm.com>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/IdentifierTable.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/CodeGen/TargetBuiltins/X86.cpp
M clang/lib/Sema/SemaType.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/AST/ByteCode/cxx2a.cpp
M clang/test/C/C23/n3007.c
M clang/test/CXX/dcl.decl/dcl.init/dcl.init.general/p16-cxx20.cpp
A clang/test/CodeGen/builtin-cpu-is-cputype.c
A clang/test/CodeGen/builtin-cpu-is-subtype.c
A clang/test/CodeGen/builtin-cpu-is-vendor.c
R clang/test/CodeGen/builtin-cpu-is.c
A clang/test/CodeGen/builtin-cpu-supports-all.c
M clang/test/Parser/c2x-auto.c
M compiler-rt/lib/builtins/cpu_model/x86.c
M flang/lib/Optimizer/Transforms/FIRToSCF.cpp
M flang/test/Fir/FirToSCF/do-loop.fir
M libc/shared/builtins.h
A libc/shared/builtins/mulsf3.h
M libc/src/__support/builtins/CMakeLists.txt
A libc/src/__support/builtins/mulsf3.h
M libc/src/spawn/linux/CMakeLists.txt
M libc/src/spawn/linux/posix_spawn.cpp
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_builtins_test.cpp
M libcxxabi/src/CMakeLists.txt
M llvm/docs/CommandGuide/llvm-dwarfdump.rst
M llvm/docs/PDB/MsfFile.rst
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/TargetParser/X86TargetParser.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/Hexagon/HexagonPostRAHandleQFP.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.atomic.cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir
M llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
M llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
M llvm/test/CodeGen/AMDGPU/agpr-csr.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ptr.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/and.ll
M llvm/test/CodeGen/AMDGPU/andorn2.ll
M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-usub_cond.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir
M llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir
M llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir
M llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2_a_v.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fceil64.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.simple.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-memops.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
A llvm/test/CodeGen/AMDGPU/pack-half-to-lshl-or.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/siloadstoreopt-misaligned-regsequence.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/ssubo.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll
M llvm/test/CodeGen/AMDGPU/structurize-hoist.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
M llvm/test/CodeGen/AMDGPU/swdev380865.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
M llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/valu-i1.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/wqm.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
A llvm/test/CodeGen/RISCV/rvv/vecreduce-add-constant-fold.ll
A llvm/test/CodeGen/SPIRV/capability-Int64Atomics-weak-cmpxchg.ll
A llvm/test/CodeGen/SPIRV/instructions/phi-aggregate-call.ll
A llvm/test/CodeGen/SPIRV/instructions/phi-aggregate-with-overflow-zeroinitializer.ll
A llvm/test/CodeGen/SPIRV/instructions/phi-aggregate-with-overflow.ll
A llvm/test/CodeGen/SPIRV/instructions/select-freeze-aggregate-with-overflow.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/signed_arithmetic_overflow.ll
A llvm/test/CodeGen/X86/apx/peephole-fold-subreg-tied-copy.mir
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-cmpeq.ll
M llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
M llvm/test/Transforms/SLPVectorizer/semanticly-same.ll
M llvm/test/tools/llvm-dwarfdump/X86/coverage.test
M llvm/tools/llvm-dwarfdump/CMakeLists.txt
M llvm/tools/llvm-dwarfdump/Coverage.cpp
M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
Log Message:
-----------
Merge branch 'main' into users/DavidTruby/flang-rt-no-offload
Compare: https://github.com/llvm/llvm-project/compare/34c8105a3388...8d5b800f1b59
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