[all-commits] [llvm/llvm-project] 90dd76: [AMDGPU] Select the high-half 16-bit packing idiom...

[Barbara Mitic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 90dd76bf36f5d8c5ab4dccabee444229e461e7be
      https://github.com/llvm/llvm-project/commit/90dd76bf36f5d8c5ab4dccabee444229e461e7be
  Author: Barbara Mitic <bmitic at amd.com>
  Date:   2026-07-07 (Tue, 07 Jul 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
    M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
    M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll
    M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
    M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
    M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
    M llvm/test/CodeGen/AMDGPU/idot4u.ll
    M llvm/test/CodeGen/AMDGPU/idot8s.ll
    M llvm/test/CodeGen/AMDGPU/idot8u.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
    A llvm/test/CodeGen/AMDGPU/pack-half-to-lshl-or.ll
    M llvm/test/CodeGen/AMDGPU/permute_i8.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
    M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll

  Log Message:
  -----------
  [AMDGPU] Select the high-half 16-bit packing idiom to v_lshl_or_b32 (#206058)

The (hi << 16) | z high-half packing idiom is not fused by the existing
(or (shl x, y), z) selection. By the time it reaches ISel the DAG
combiner has rewritten (ext i16) << 16 into bitcast(build_vector (i16
0), hi), so there is no shl node left to match and the build_vector and
or are selected separately.

Add ISel patterns that match the build_vector form directly. On the
non-real-true16 path the high-half source is a VGPR_32, so fold into
v_lshl_or_b32. On the real-true16 path the high-half source is a VGPR_16
and 16-bit ops are native, so OR it into the high half of the other
operand with v_or_b16 and assemble the result with a REG_SEQUENCE.

Co-authored-by: Barbara Mitic <Barbara.Mitic at amd.com>



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