[all-commits] [llvm/llvm-project] 3226a4: [AArch64][llvm] Restrict luti6 (4 regs, 8-bit) to ...

[Jonathan Thackray via All-commits]

  Branch: refs/heads/users/jthackray/restrict_luti6_z0_z7
  Home:   https://github.com/llvm/llvm-project
  Commit: 3226a44617ef446529a4739cf210d98be024eeb0
      https://github.com/llvm/llvm-project/commit/3226a44617ef446529a4739cf210d98be024eeb0
  Author: Jonathan Thackray <jonathan.thackray at arm.com>
  Date:   2026-07-07 (Tue, 07 Jul 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    M llvm/test/MC/AArch64/SME2p3/luti6-diagnostics.s

  Log Message:
  -----------
  [AArch64][llvm] Restrict luti6 (4 regs, 8-bit) to 0 <= Zn <= 7

The `luti6` instruction (table, four registers, 8-bit) should only
allow `0 <= Zn <= 7`, since there's only 3 bits. It actually allows:
```
   luti6 { z0.b - z3.b }, zt0, { z8 - z10 }
```
which produces a duplicate encoding to the following:
```
   luti6 { z0.b - z3.b }, zt0, { z0 - z2 }
```

Fix tablegen to ensure Zn is only allowed in correct range of 0 to 7.


  Commit: 5d2a7c6bb1483a1ffda1d394c5e4706541a20050
      https://github.com/llvm/llvm-project/commit/5d2a7c6bb1483a1ffda1d394c5e4706541a20050
  Author: Jonathan Thackray <jonathan.thackray at arm.com>
  Date:   2026-07-07 (Tue, 07 Jul 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td

  Log Message:
  -----------
  fixup! Address CR comments


  Commit: 5f93ed5ac69a538d638cca7b0e3fca076145cf7e
      https://github.com/llvm/llvm-project/commit/5f93ed5ac69a538d638cca7b0e3fca076145cf7e
  Author: Jonathan Thackray <jonathan.thackray at arm.com>
  Date:   2026-07-07 (Tue, 07 Jul 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp

  Log Message:
  -----------
  fixup! Address more CR comments


  Commit: de4f258b390ce304ff04584d1cd3e61a50e137a2
      https://github.com/llvm/llvm-project/commit/de4f258b390ce304ff04584d1cd3e61a50e137a2
  Author: Jonathan Thackray <jonathan.thackray at arm.com>
  Date:   2026-07-07 (Tue, 07 Jul 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp

  Log Message:
  -----------
  fixup! implement Carol's suggestion


  Commit: 219d634fd8add3539451b0236deb2392fdc36828
      https://github.com/llvm/llvm-project/commit/219d634fd8add3539451b0236deb2392fdc36828
  Author: Jonathan Thackray <jonathan.thackray at arm.com>
  Date:   2026-07-07 (Tue, 07 Jul 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp

  Log Message:
  -----------
  fixup! Carol's suggestion


Compare: https://github.com/llvm/llvm-project/compare/c73526a5dd6e...219d634fd8ad

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