[all-commits] [llvm/llvm-project] b838b0: [RISCV][MC] Improve diagnostics for Zclsd RV32 GPR...

[Ying Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b838b0cc1c76c34e57d70d5d259382ac0d764cca
      https://github.com/llvm/llvm-project/commit/b838b0cc1c76c34e57d70d5d259382ac0d764cca
  Author: Ying Chen <chenying at inchitech.com>
  Date:   2026-07-06 (Mon, 06 Jul 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td
    M llvm/test/MC/RISCV/rv32zclsd-invalid.s

  Log Message:
  -----------
  [RISCV][MC] Improve diagnostics for Zclsd RV32 GPR pair operands (#207639)

Add dedicated assembler diagnostics for the RV32 GPR pair operands used
by
Zclsd compressed load/store pair instructions.

After the RISC-V asm parser started reporting multiple near-miss
reasons, these
operands still fell back to the generic "invalid operand for
instruction" note.
Give them explicit diagnostic types and messages so invalid register
pairs report
the expected pair constraints.



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