[all-commits] [llvm/llvm-project] 5cd8f2: [CodeGen] Rename prologpeilog to prolog-epilog (#2...

Mon Jul 6 18:26:28 PDT 2026

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5cd8f2f847101effad54a88936abe5e3bcb7e884
      https://github.com/llvm/llvm-project/commit/5cd8f2f847101effad54a88936abe5e3bcb7e884
  Author: Aiden Grossman <aidengrossman at google.com>
  Date:   2026-07-06 (Mon, 06 Jul 2026)

  Changed paths:
    M flang/test/Driver/fsave-optimization-record.f90
    M lld/test/ELF/lto/stats-file-option.ll
    M llvm/docs/Remarks.rst
    M llvm/include/llvm/Passes/MachinePassRegistry.def
    M llvm/lib/CodeGen/PrologEpilogInserter.cpp
    M llvm/test/CodeGen/AArch64/aarch64-large-stack-spbump.mir
    M llvm/test/CodeGen/AArch64/aarch64-vector-pcs.mir
    M llvm/test/CodeGen/AArch64/addg_subg.mir
    M llvm/test/CodeGen/AArch64/cfi_restore.mir
    M llvm/test/CodeGen/AArch64/chkstk.ll
    M llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
    M llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir
    M llvm/test/CodeGen/AArch64/emit-prologue-clobber-verification.mir
    M llvm/test/CodeGen/AArch64/extra-callee-save.mir
    M llvm/test/CodeGen/AArch64/framelayout-fpr128-spill.mir
    M llvm/test/CodeGen/AArch64/framelayout-frame-record.mir
    M llvm/test/CodeGen/AArch64/framelayout-offset-immediate-change.mir
    M llvm/test/CodeGen/AArch64/framelayout-scavengingslot-stack-hazard.mir
    M llvm/test/CodeGen/AArch64/framelayout-scavengingslot.mir
    M llvm/test/CodeGen/AArch64/framelayout-split-sve.mir
    M llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir
    M llvm/test/CodeGen/AArch64/framelayout-sve-calleesaves-fix.mir
    M llvm/test/CodeGen/AArch64/framelayout-sve-fixed-width-access.mir
    M llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir
    M llvm/test/CodeGen/AArch64/framelayout-sve-win.mir
    M llvm/test/CodeGen/AArch64/framelayout-sve.mir
    M llvm/test/CodeGen/AArch64/large-stack-offset-calcs.mir
    M llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
    M llvm/test/CodeGen/AArch64/lr-reserved-for-ra-live-in.ll
    M llvm/test/CodeGen/AArch64/machine-outliner-bti.mir
    M llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
    M llvm/test/CodeGen/AArch64/machine-outliner-no-noreturn-no-stack.mir
    M llvm/test/CodeGen/AArch64/machine-outliner-noreturn-no-stack.mir
    M llvm/test/CodeGen/AArch64/machine-outliner-regsave.mir
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir
    M llvm/test/CodeGen/AArch64/machine-outliner-size-info.mir
    M llvm/test/CodeGen/AArch64/machine-outliner.mir
    M llvm/test/CodeGen/AArch64/memtag-stg-loop-reg-pressure.mir
    M llvm/test/CodeGen/AArch64/no-xzr-liveins.mir
    M llvm/test/CodeGen/AArch64/pr157252.mir
    M llvm/test/CodeGen/AArch64/preserve.ll
    M llvm/test/CodeGen/AArch64/prologue-epilogue-remarks.mir
    M llvm/test/CodeGen/AArch64/reg-scavenge-frame.mir
    M llvm/test/CodeGen/AArch64/reloc-specifiers.mir
    M llvm/test/CodeGen/AArch64/settag-merge.mir
    M llvm/test/CodeGen/AArch64/spill-stack-realignment.mir
    M llvm/test/CodeGen/AArch64/stack-guard-reassign-sve.mir
    M llvm/test/CodeGen/AArch64/stack-guard-reassign.mir
    M llvm/test/CodeGen/AArch64/stack-id-pei-alloc.mir
    M llvm/test/CodeGen/AArch64/stack-id-stackslot-scavenging.mir
    M llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir
    M llvm/test/CodeGen/AArch64/stack-probing-no-scratch-reg.mir
    M llvm/test/CodeGen/AArch64/stack-probing-shrink-wrap.mir
    M llvm/test/CodeGen/AArch64/stack-tagging-epilogue-fold.mir
    M llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir
    M llvm/test/CodeGen/AArch64/statepoint-call-lowering-lr.ll
    M llvm/test/CodeGen/AArch64/statepoint-call-lowering-sp.ll
    M llvm/test/CodeGen/AArch64/sve-calling-convention.ll
    M llvm/test/CodeGen/AArch64/sve-ld1r.mir
    M llvm/test/CodeGen/AArch64/sve-ldN.mir
    M llvm/test/CodeGen/AArch64/sve-ldnf1.mir
    M llvm/test/CodeGen/AArch64/sve-ldst-multi-vec.mir
    M llvm/test/CodeGen/AArch64/sve-ldstnt1.mir
    M llvm/test/CodeGen/AArch64/sve-stN.mir
    M llvm/test/CodeGen/AArch64/unreachable-emergency-spill-slot.mir
    M llvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
    M llvm/test/CodeGen/AArch64/wineh-frame-predecrement.mir
    M llvm/test/CodeGen/AArch64/wineh-frame-scavenge.mir
    M llvm/test/CodeGen/AArch64/wineh-frame0.mir
    M llvm/test/CodeGen/AArch64/wineh-frame1.mir
    M llvm/test/CodeGen/AArch64/wineh-frame2.mir
    M llvm/test/CodeGen/AArch64/wineh-frame3.mir
    M llvm/test/CodeGen/AArch64/wineh-frame4.mir
    M llvm/test/CodeGen/AArch64/wineh-frame5.mir
    M llvm/test/CodeGen/AArch64/wineh-frame6.mir
    M llvm/test/CodeGen/AArch64/wineh-frame7.mir
    M llvm/test/CodeGen/AArch64/wineh-frame8.mir
    M llvm/test/CodeGen/AArch64/wineh-save-lrpair1.mir
    M llvm/test/CodeGen/AArch64/wineh-save-lrpair2.mir
    M llvm/test/CodeGen/AArch64/wineh-save-lrpair3.mir
    M llvm/test/CodeGen/AArch64/wineh1.mir
    M llvm/test/CodeGen/AArch64/wineh2.mir
    M llvm/test/CodeGen/AArch64/wineh3.mir
    M llvm/test/CodeGen/AArch64/wineh4.mir
    M llvm/test/CodeGen/AArch64/wineh5.mir
    M llvm/test/CodeGen/AArch64/wineh6.mir
    M llvm/test/CodeGen/AArch64/wineh7.mir
    M llvm/test/CodeGen/AArch64/wineh8.mir
    M llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir
    M llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
    M llvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir
    M llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
    M llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir
    M llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir
    M llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
    M llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir
    M llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir
    M llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-u32.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
    M llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir
    M llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll
    M llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi-gfx1250.mir
    M llvm/test/CodeGen/AMDGPU/frame-index-elimination-tied-operand.mir
    M llvm/test/CodeGen/AMDGPU/frame-index.mir
    M llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir
    M llvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir
    M llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
    M llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir
    M llvm/test/CodeGen/AMDGPU/machine-function-info-cwsr.ll
    M llvm/test/CodeGen/AMDGPU/mcinstlower-external-symbol-reloc.mir
    M llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir
    M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
    M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
    M llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
    M llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir
    M llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
    M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
    M llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir
    M llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir
    M llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir
    M llvm/test/CodeGen/AMDGPU/spillv16.mir
    M llvm/test/CodeGen/AMDGPU/spillv16Kernel.mir
    M llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir
    M llvm/test/CodeGen/AMDGPU/track-spilled-vgpr-liveness.mir
    M llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir
    M llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-dead-frame-in-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir
    M llvm/test/CodeGen/AMDGPU/wwm-reg-shift-down-gfx11plus.mir
    M llvm/test/CodeGen/ARM/execute-only-save-cpsr.mir
    M llvm/test/CodeGen/ARM/fpoffset_overflow.mir
    M llvm/test/CodeGen/ARM/interrupt-save-fp-attr-status-regs.mir
    M llvm/test/CodeGen/ARM/machine-outliner-calls.mir
    M llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-arm.mir
    M llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir
    M llvm/test/CodeGen/ARM/nonreserved-callframe-with-basereg.mir
    M llvm/test/CodeGen/ARM/noreturn-csr-skip.mir
    M llvm/test/CodeGen/ARM/pei-swiftself.mir
    M llvm/test/CodeGen/ARM/register-scavenger-exceptions.mir
    M llvm/test/CodeGen/ARM/stack_frame_offset.mir
    M llvm/test/CodeGen/ARM/tldrlit_ga_size.mir
    M llvm/test/CodeGen/BPF/BTF/func-nocall-undef-dead-arg.ll
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    M llvm/test/CodeGen/LoongArch/stack-probing-frame-setup.mir
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    M llvm/test/CodeGen/M68k/is-pcrel-register-operand-legal.mir
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    M llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir
    M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
    M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
    M llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
    M llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
    M llvm/test/CodeGen/MIR/X86/diexpr-win32.mir
    M llvm/test/CodeGen/Mips/copy-fp64.ll
    M llvm/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir
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    M llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic3.macho.remarks.arm64.opt.yaml
    M llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/fat.macho.remarks.x86_64.opt.yaml
    M llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/fat.macho.remarks.x86_64h.opt.yaml
    M llvm/test/tools/llvm-remarkutil/Inputs/two-remarks.bitstream
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    M llvm/test/tools/llvm-remarkutil/convert.test
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    M llvm/test/tools/llvm-remarkutil/size-diff/Inputs/2-identical-func-1-instr-1-stack.yaml
    M llvm/test/tools/llvm-remarkutil/size-diff/Inputs/inconvertible-integer.yaml
    M llvm/test/tools/llvm-remarkutil/size-diff/Inputs/no-instruction-count-remarks.yaml
    M llvm/test/tools/llvm-remarkutil/size-diff/Inputs/unexpected-key.yaml
    M llvm/tools/llvm-exegesis/lib/Assembler.cpp
    M llvm/tools/llvm-remarkutil/RemarkSizeDiff.cpp

  Log Message:
  -----------
  [CodeGen] Rename prologpeilog to prolog-epilog (#207870)

This is primarily to ensure consistenct with the new pass manager where
the name of the pass is already prolog-epilog, which is more consistent
with our existing naming scheme. This is necessary to be able to run
existing llc invocations that explicitly specify prolog-epilog under the
NewPM automatically.

Assisted by Gemini.

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