[all-commits] [llvm/llvm-project] f7f066: [RISCV] Pass structs containing riscv_rvv_vector_b...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f7f06613d4fc68620076a48341acf22dc05fbd82
      https://github.com/llvm/llvm-project/commit/f7f06613d4fc68620076a48341acf22dc05fbd82
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-07-06 (Mon, 06 Jul 2026)

  Changed paths:
    M clang/lib/CodeGen/Targets/RISCV.cpp
    A clang/test/CodeGen/RISCV/attr-rvv-vector-bits-struct-call.c
    A clang/test/CodeGenCXX/riscv-rvv-fixed-length-struct-call.cpp

  Log Message:
  -----------
  [RISCV] Pass structs containing riscv_rvv_vector_bits types using vector registers. (#203601)

The ABI for this isn't documented. The riscv_rvv_vector_bits feature was
copied from aarch_sve_vector_bits which passes the types in vector
registers. At the time I implemented RISC-V I didn't think about struct
arguments so no ABI support was added.

I think it makes sense to pass structs of these types in vector
registers similar to the vls_cc ABI. We already do use vector registers
for these types when the vls_cc ABI is enabled for a function(unclear if
that was intentional), but we should do it unconditionally.

I will work with gcc maintainers to see if they can do the same. In
practice, there probably isn't much compiler mixing with these types.

This patch was heavily assisted by AI, but I've reviewed it and the
changes seem reasonable to me.



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