[all-commits] [llvm/llvm-project] 6de2b5: [Hexagon] Lower vselect instruction (#206675)

[pkarveti via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6de2b5f8f45d88d25956a2536460d441cd07eeef
      https://github.com/llvm/llvm-project/commit/6de2b5f8f45d88d25956a2536460d441cd07eeef
  Author: pkarveti <pkarveti at qti.qualcomm.com>
  Date:   2026-07-03 (Fri, 03 Jul 2026)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
    A llvm/test/CodeGen/Hexagon/vselect.ll

  Log Message:
  -----------
  [Hexagon] Lower vselect instruction (#206675)

Selection fails with "Cannot select: vselect" when the condition and
both data operands of an HVX vselect are predicate vectors (e.g. v32i1,
v64i1, v128i1). This patch adds patterns for vselect on HVX predicate
vectors of all three element widths (VecQ8, VecQ16, VecQ32), expanding
them to V6_pred_or/V6_pred_and/V6_pred_and_n on Q registers.

Patch-By: @iajbar 
Fixes #206353



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