[all-commits] [llvm/llvm-project] 5fa41e: [X86] Use valign instead of vperm for float domain...

[Ganesh via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5fa41e26aaa01fb79c4c5d7ff71f027757e444ae
      https://github.com/llvm/llvm-project/commit/5fa41e26aaa01fb79c4c5d7ff71f027757e444ae
  Author: Ganesh <Ganesh.Gopalasubramanian at amd.com>
  Date:   2026-06-26 (Fri, 26 Jun 2026)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
    M llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
    M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll

  Log Message:
  -----------
  [X86] Use valign instead of vperm for float domain shuffles (#201624)

The X86 backend then lowers the shuffle through lowerV16F32Shuffle /
lowerV8F64Shuffle, which fall through to lowerShuffleWithPERMV (VPERMPS
/ VPERMPD). lowerShuffleAsVALIGN is asserted on i32 / i64 element types
only and is never called from the float-domain paths, even when the mask
is a clean concatenate-and-shift that VALIGN expresses exactly.

On znver5, VALIGN and VPERMPS / VPERMPD have identical latency (5 cycles
for zmm), throughput (2), and macro-op count (1). The real cost of
VPERMPS / VPERMPD is the extra zmm register required to hold the
permutation index vector.

Intrinsic path for _mm512_alignr_epi32 also gets a vperm. Its a win in
generic path as well as vpermps zmm1, zmm0, zmm3 requires a dedicated
zmm register to hold the permutation index vector. valignd zmm1, zmm3,
zmm3, 1 encodes the rotation count as an immediate (imm8 = 1), using no
extra registers.

Co-authored-by: Shivanshu



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