[all-commits] [llvm/llvm-project] af1c5a: [RISCV] Extend legal addressing modes to support 2...

[Garvit Gupta via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: af1c5a425a1e2f01e810cab06bdfa7c9199fd412
      https://github.com/llvm/llvm-project/commit/af1c5a425a1e2f01e810cab06bdfa7c9199fd412
  Author: Garvit Gupta <garvgupt at qti.qualcomm.com>
  Date:   2026-06-26 (Fri, 26 Jun 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/xqcilia-addimm-mulimm-loop.ll
    A llvm/test/CodeGen/RISCV/xqcilo-split-gep.ll
    A llvm/test/Transforms/CodeGenPrepare/RISCV/xqcilo.ll
    A llvm/test/Transforms/ConstantHoisting/RISCV/xqcilia.ll

  Log Message:
  -----------
  [RISCV] Extend legal addressing modes to support 26-bit addi/Xqcilo offsets (#204734)

Extend `RISCVTargetLowering::isLegalAddImmediate` and `isLegalAddressingMode` 
to accept 26-bit signed immediates/offsets when the corresponding Qualcomm uC
extensions are enabled

These callbacks are queried by some pre-ISel passes. Adding support for
the wider range lets those passes keep large immediates inline and large offsets
folded into addressing modes.



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